TW201810461A - Method for manufacturing semiconductor device, and semiconductor device - Google Patents

Method for manufacturing semiconductor device, and semiconductor device Download PDF

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Publication number
TW201810461A
TW201810461A TW106104751A TW106104751A TW201810461A TW 201810461 A TW201810461 A TW 201810461A TW 106104751 A TW106104751 A TW 106104751A TW 106104751 A TW106104751 A TW 106104751A TW 201810461 A TW201810461 A TW 201810461A
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Taiwan
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lead
inner lead
bonding wire
semiconductor device
end portion
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TW106104751A
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Chinese (zh)
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TWI646608B (en
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石井斉
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東芝記憶體股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

The embodiment of the invention provides a method for manufacturing a semiconductor device, and the semiconductor device, wherein the method can inhibit the useless deformation of a lead wire. The method comprises the following steps: pressing the first inner lead while pressing the first inner lead and pressing the pressing member against the wiring portion from the other side of the lead frame opposite to the side on which the first recess is formed, wherein the connecting portion between the end portion in the extending direction of the first inner lead and the wiring portion is cut off at the first concave portion, and the wiring portion is separated from the end portion, and the lead frame includes a first lead wire, a second lead wire, and a wiring portion connecting the second inner lead and the end portion in the extending direction of the first inner lead, and the connecting portion between the end portion in the extending direction of the first inner lead and the wiring portion is greater than the width and the inner side of the direction has a first concave portion.

Description

半導體裝置之製造方法及半導體裝置Manufacturing method of semiconductor device and semiconductor device

本發明之實施形態係關於一種半導體裝置之製造方法及半導體裝置。Embodiments of the present invention relate to a method for manufacturing a semiconductor device and a semiconductor device.

於具備包含外引線及內引線之引線、及半導體晶片之半導體裝置中，利用接合線將半導體晶片之電極墊與內引線之間電性連接。因此，電極墊與外引線之間之距離越長，則越必須使內引線較長地自外引線延伸至電極墊附近。 較長之內引線於半導體裝置之製造過程中容易變形。若內引線變形，則例如存在半導體晶片容易自內引線剝離之情況，或於打線接合時於接合線與內引線之間產生連接不良之情況。In a semiconductor device including a lead including an outer lead and an inner lead, and a semiconductor wafer, a bonding wire is used to electrically connect the electrode pad of the semiconductor wafer and the inner lead. Therefore, the longer the distance between the electrode pad and the outer lead, the longer the inner lead must extend from the outer lead to the vicinity of the electrode pad. The longer inner leads are easily deformed during the manufacturing process of the semiconductor device. When the inner lead is deformed, for example, the semiconductor wafer may be easily peeled from the inner lead, or a connection failure between the bonding wire and the inner lead may occur during wire bonding.

本發明之實施形態係提供一種可抑制引線之無謂之變形之半導體裝置之製造方法及半導體裝置。 實施形態之半導體裝置之製造方法具備如下步驟：一邊按壓第1內引線，一邊自引線框架之與形成著第1凹部之一面為相反側之另一面將推壓構件壓抵於配線部，使引線框架變形，以第1凹部為基點，剪切第1內引線之延伸方向之端部與配線部之連接部，並且使配線部與端部分離；上述引線框架包括：第1引線，其包含第1外引線及自第1外引線延伸之第1內引線；第2引線，其包含第2外引線及自第2外引線延伸之第2內引線；配線部，其將第2內引線與第1內引線之延伸方向之端部之間連接；及支持部，其連接於第1外引線及第2外引線，且第1內引線之延伸方向之端部與配線部之間之連接部於較寬度方向之端部更內側之區域具有第1凹部；將具備第1電極墊與第2電極墊之半導體晶片經由接著層而搭載於引線框架之另一面上；形成將第1電極墊與第1引線電性連接之第1接合線、及將第2電極墊與第2引線電性連接之第2接合線；形成將第1內引線、第2內引線、配線部、半導體晶片、第1接合線、及第2接合線密封之密封樹脂層；將支持部與第1外引線及第2外引線之間之連接部切斷。Embodiments of the present invention provide a method for manufacturing a semiconductor device and a semiconductor device capable of suppressing unnecessary deformation of a lead. A method of manufacturing a semiconductor device according to an embodiment includes the following steps: while pressing the first inner lead, pressing the pressing member against the wiring portion from the other side of the lead frame opposite to the side where the first recess is formed, and the lead is The frame is deformed, and the first recessed portion is used as a base point to cut the connecting portion between the end portion of the first inner lead in the extending direction and the wiring portion and separate the wiring portion from the end portion. The lead frame includes: a first lead including the first lead; 1 outer lead and first inner lead extending from the first outer lead; second lead including the second outer lead and second inner lead extending from the second outer lead; wiring section that connects the second inner lead and the first lead 1 between the ends in the extending direction of the inner lead; and a support portion connected to the first outer lead and the second outer lead, and the connecting portion between the end in the extending direction of the first inner lead and the wiring part is A region further inside than the end in the width direction has a first recessed portion; a semiconductor wafer including the first electrode pad and the second electrode pad is mounted on the other surface of the lead frame via an adhesive layer; and the first electrode pad and the first 1 lead for 1 lead electrical connection Wire, and a second bonding wire electrically connecting the second electrode pad to the second lead; forming a seal for the first inner lead, the second inner lead, the wiring portion, the semiconductor wafer, the first bonding wire, and the second bonding wire The sealing resin layer; the connection portion between the support portion and the first outer lead and the second outer lead is cut.

以下，參照附圖對實施形態進行說明。附圖中記載之各構成要素之厚度與平面尺寸之關係、各構成要素之厚度之比例等存在與實物不同之情況。另外，於實施形態中，對實質上相同之構成要素標註相同之符號並適當省略說明。 作為半導體裝置之製造方法例，參照圖1至圖8，對作為TSOP(Thin Small Outline Package，薄型小尺寸封裝)之半導體裝置之製造方法例進行說明。半導體裝置之製造方法例具備引線框架準備步驟、引線框架加工步驟、晶片搭載步驟、打線接合步驟、樹脂密封步驟、外裝鍍覆步驟、及修整成型(T/F)步驟。各步驟之順序並不限定於上述列舉順序。 圖1係表示引線框架之構造例之俯視模式圖。圖1表示包含X軸及與X軸正交之Y軸之引線框架之X-Y平面。 於引線框架準備步驟中，如圖1所示，準備包含複數根引線11及支持複數根引線11之支持部12之引線框架1。引線框架1係搭載半導體晶片等元件之金屬板。作為引線框架1，例如可列舉使用銅、銅合金、或42合金等鐵及鎳之合金等之引線框架。引線框架1利用衝切加工等而預先加工。 複數根引線11之各者包含外引線及自該外引線延伸之內引線。內引線係於樹脂密封步驟後由密封樹脂層支持之部分。於內引線，於引線框架1之上表面側之進行打線接合之區域設置著銀等鍍覆層。外引線係於樹脂密封步驟後自密封樹脂層突出之部分。複數根引線11之外引線之各者例如沿Y軸而並列設置於X-Y平面。 作為複數根引線11，例如可列舉輸入輸出信號(IO)、資料選通信號(DQS)、引線賦能信號(RE)、待命/忙碌信號(RB)、晶片賦能信號(CE)、位址閂賦能信號(ALE)、寫入賦能信號(WE)、寫入保護信號(RP)、或零商信號(ZQ)等信號用引線，或電源(VCC)、電源(VPP)、電源(VSS)等電源用引線等。作為上述信號，亦可使用差動信號。複數根引線11之至少一根亦可為未連接(NC)之引線。各種引線之排列順序根據半導體裝置之規格或標準等設定。 支持部12係以包圍複數根引線11之方式設置。支持部12與複數根引線11之外引線之一端之各者連結。再者，支持部12除支持複數根引線11以外，亦可支持用於另一半導體裝置之引線。 圖2係表示自引線框架1之下表面側觀察時之圖1所示之引線框架之一部分(區域100之一部分)之模式圖。於圖2中，將引線框架1之下表面圖示於上表面側，將引線框架1之上表面圖示於下表面側。圖2中之Z軸與X軸及Y軸正交，相當於引線框架1之厚度方向。於圖2中，作為複數根引線11之內引線，圖示內引線111、內引線112、內引線113、及內引線114。 內引線111及內引線112例如為輸入輸出信號(IO)或資料選通信號(DQS)用引線。內引線113及內引線114例如為電源(VSS)用引線。此時，藉由於內引線111與內引線112之間設置內引線113而可抑制內引線111之信號與內引線112之信號之間之干涉。 圖1所示之引線框架具有將內引線111至內引線113之延伸方向之端部與內引線114之一部分連接之配線部115。即，內引線111至內引線113利用支持部12及配線部115而固定。配線部115之形狀只要可將內引線111至內引線113與內引線114連接之形狀則並無特別限定。另外，亦可將配線部115視為內引線114之一部分。 內引線111至內引線114及配線部115具有設置於引線框架1之上表面側(圖2之下表面側)之鍍覆層20。鍍覆層20例如藉由使用包含銀等之鍍覆材料之鍍覆處理而形成。為了於下述打線接合時確保內引線111至內引線114與接合線之間之接合強度，或使與半導體晶片之連接電阻變小，鍍覆層20設置於進行打線接合之區域。 內引線111至內引線113之延伸方向(Y軸方向)之端部與配線部115之連接部於引線框架1之上表面側具有凹部(凹槽)116a。凹部116a設置於內引線111至內引線113之各者之較寬度方向(X軸方向)之端部更內側之區域。 內引線114與配線部115之連接部於引線框架1之上表面側具有凹部(凹槽)116b。圖2所示之凹部116b自內引線114之寬度方向之一端延伸至另一端，但並不限定於此，亦可與凹部116a同樣地設置於內引線114與配線部115之連接部之較寬度方向之端部更內側之區域。另外，凹部116b可設置複數個。 於圖2中，凹部116a及凹部116b於包含Y-Z平面之截面上具有V字形狀，亦可為其他形狀。另外，凹部116b之引線框架1之厚度方向之深度較佳為小於凹部116a之引線框架1之厚度方向之深度。 凹部116a及凹部116b例如係藉由壓印加工、雷射加工、或刀片加工等而形成。凹部116a及凹部116b較佳為於衝切步驟之前形成。若於衝切加工之後形成凹部116a及凹部116b，則存在引線框架1產生無謂之變形之情況。 凹部116a及凹部116b設置於引線框架1之下表面側、即具有鍍覆層20之面之相反側之面。鍍覆層20係於形成凹部116a及凹部116b後形成。因此，若於具有凹部116a及凹部116b之面形成鍍覆層20，則存在鍍覆材料於凹部116a及凹部116b堆積，因電場集中等而使可靠性降低之情況。 圖3及圖4係用以對引線框架加工步驟進行說明之剖視模式圖。圖3及圖4表示引線框架1之包含Y軸與Z軸之Y-Z截面。於圖3及圖4中，作為一例，圖示包含內引線113之截面。 於引線框架加工步驟中，於具有凹部51a之平台51上，以使凹部116a及凹部116b處於下側(平台51側)之方式載置引線框架1，利用按壓構件52按壓配線部115之兩端。此時，使配線部115與凹部51a重疊。 其次，使推壓構件53沿Z軸朝平台51側下降，將推壓構件53自引線框架1之形成有凹部116a及凹部116b之一面之相反側的另一面壓抵於配線部115而使配線部115之至少一部分變形，以凹部116a為基點剪切內引線113之延伸方向之端部與配線部115之間之連接部。具有凹部116a之部分較其他區域更容易剪切。又，由於凹部116a設置於較內引線113之寬度方向之端部更內側，故與凹部116a延伸至內引線113之寬度方向之端部之情況相比較，抑制因剪切而產生毛邊。 配線部115以將凹部116b作為基點自內引線113之延伸方向之端部分離之方式彎曲。具有凹部116b之部分較其他區域容易彎曲。因此，可抑制無謂之變形。 圖5係表示引線框架1之自上表面側觀察之變形後之區域100之構造例之模式圖。於圖5中，將引線框架1之上表面圖示於上表面側，將引線框架1之下表面圖示於下表面側。 連接部之剪切後之配線部115具有：第1端部，其連接於內引線114；及第2端部，其自與X-Y平面垂直之方向(Z軸方向)觀察時，與內引線111至內引線113之延伸方向之端部相鄰。第2端部係以當自與Y-Z截面垂直之方向觀察時沿內引線114之包含厚度方向之截面而與內引線111至內引線113分離之方式，以凹部116b為基點朝特定方向彎曲。 內引線111至內引線113之延伸方向之端部及配線部115之第2端部之各者藉由剪切凹部116a而於較寬度方向之端部更內側之區域具有凹部117。變形後之配線部115之形狀並無特別限定，亦可如圖5所示，配線部115具有與內引線111至內引線113之延伸方向平行之區域。藉由以上步驟，使內引線111之一部分至內引線114之一部分相互分離。同樣地，使其他連結之內引線之一部分亦藉由上述步驟而相互分離。 藉由使內引線111至內引線113與配線部115之間之連接部變薄，而可減小剪切所需之荷重。由此，作為推壓構件53，可應用設置於晶片搭載步驟中搭載半導體晶片時所使用之晶片接合裝置之複數個接合頭之一。 為了使內引線111至內引線114電性分離，考慮利用衝切加工去除上述連接部之一部分之方法。於利用衝切加工去除上述連接部之一部分之情形時，內引線111至內引線113中之一根所需之剪切部位為兩個部位以上。因此，衝切所需之荷重大於上述連接部之剪切所需之荷重。故，為了進行衝切加工，必須設置與剪切上述連接部之機構不同之、可賦予更高荷重之推壓機構。因此，加工裝置之構成變得複雜。另外，於進行衝切加工時，當對引線框架之一部分進行衝切時會產生切屑(經去除之部分)。引線之切屑不但會成為製造環境之污染源，而且需要用以排出引線之切屑之機構，因此較佳為不產生切屑。 於利用衝切加工對引線框架進行加工之情形時，係於加工後將引線框架搬送至晶片接合裝置並搭載半導體晶片，因而熱引線容易於搬送中變形。因此，必需設置固定複數根引線之固定帶。由於固定帶容易吸收水分，故容易自引線或後續設置之密封半導體晶片之樹脂剝離。另外，若具有固定帶則引線框架實質上變厚。因此，收容殼體可收容之引線框架數減少，故輸送成本增大。進而，固定帶容易發生枝晶狀之遷移。存在若發生遷移，則會引起引線間之短路等之情況。 針對於此，於使用晶片接合裝置剪切上述連接部並且使各內引線之一部分分離之情形時，可於引線框架加工步驟後使用相同之晶片接合裝置搭載半導體晶片。因此，可使引線框架之搬送變少。由此，即便不設置固定帶亦可抑制引線之無謂之變形。另外，可削減固定帶之材料費及加工費，從而可削減製造成本。進而，由於可保留配線部而使各內引線之一部分分離，因此與衝切加工相較可使引線之切屑變少。 圖6係表示可使用上述半導體裝置之製造方法例製造之半導體裝置之構造例之俯視模式圖。圖6表示半導體裝置之X-Y平面。圖7係表示自引線11之上表面側觀察之圖6所示之半導體裝置之一部分(區域101之一部分)之俯視模式圖。圖8係圖6所示之半導體裝置之一部分(區域101之一部分)之剖視模式圖。圖8表示包含內引線113之截面作為一例。再者，於圖7及圖8中，出於方便而透視地圖示密封樹脂層4之內部。對於與圖1至圖5共通之部分適當引用圖1至圖5之說明。 於晶片搭載步驟中，於內引線111至內引線114等複數根引線11之內引線上搭載半導體晶片2。如圖7所示，半導體晶片2具有包含電極墊211至電極墊215之複數個電極墊21。複數個電極墊21於半導體晶片2之表面露出。複數個電極墊21亦可沿半導體晶片2之一邊設置。藉由沿半導體晶片2之一邊設置複數個電極墊21，而可使晶片尺寸變小。作為半導體晶片2，例如可列舉NAND(Not AND，反及)型快閃記憶體等記憶體元件或記憶體控制器等所使用之半導體晶片。 半導體晶片2係使用例如內引線111至內引線113之延伸方向之端部與配線部115之間之連接部之剪切所使用之晶片接合裝置而搭載。 半導體晶片2係利用與推壓構件53不同之複數個接合頭中之另一個而搭載於內引線111至內引線114上。半導體晶片2經由具有絕緣性之晶粒接附膜(die attach film)等有機接著層6而搭載於內引線111至內引線114等複數根引線11之內引線中的、形成有凹部116a及凹部116b之一面之相反側之另一面。此時，複數根引線11之內引線接著於有機接著層6。由此，由於固定了複數根引線11之內引線，故於其後之步驟中可抑制引線之無謂之變形。 半導體晶片2較佳為於將內引線111至內引線113與配線部115之間之連接部剪切後搭載。若於搭載半導體晶片後剪切上述連接部，則存在對半導體晶片造成損傷之情況。例如於將引線框架1配置(裝載)於晶片接合裝置後，剪切連接部。其後，不自晶片接合裝置去除(卸載)引線框架1，而將下述半導體晶片2搭載於引線框架1。搭載半導體晶片2後，將引線框架1自晶片接合裝置去除(卸載)，執行後續步驟、例如下述打線接合步驟。 於打線接合步驟中，形成將複數個電極墊21與複數根引線11電性連接之複數根接合線3。於圖7中，圖示將內引線111與電極墊211經由鍍覆層20而電性連接之接合線31、將內引線112與電極墊212經由鍍覆層20而電性連接之接合線32、將內引線113與電極墊213經由鍍覆層20而電性連接之接合線33、將內引線114與電極墊214經由鍍覆層20而電性連接之接合線34、及將內引線114與電極墊215經由鍍覆層20而電性連接之接合線35。 作為接合線3，例如可列舉金線、銀線、銅線等。銅線之表面可由鈀膜被覆。接合線3藉由打線接合而電性連接於引線及電極墊。 於樹脂密封步驟中，形成將內引線111至內引線114等複數根引線11之內引線、半導體晶片2、及接合線31至接合線35等複數根接合線3密封之密封樹脂層4。密封樹脂層4係以覆蓋複數根引線之內引線之上表面及下表面之方式設置。另外，如圖8所示，密封樹脂層4亦填充於內引線111至內引線113之延伸方向之端部與配線部115之間。 密封樹脂層4含有SiO2 等無機填充材。另外，無機填充材除包含SiO2 以外，亦可包含例如氫氧化鋁、碳酸鈣、氧化鋁、氮化硼、氧化鈦、或鈦酸鋇等。無機填充材例如為粒狀，具有調整密封樹脂層4之黏度或硬度等之功能。密封樹脂層4中之無機填充材之含量例如為60%以上且90%以下。作為密封樹脂層4，例如可使用無機填充材與絕緣性之有機樹脂材料之混合物。作為有機樹脂材料，例如可列舉環氧樹脂。 作為密封樹脂層4之形成法，例如可列舉使用無機填充材與有機樹脂等之混合物之轉注成形法、壓縮成形法、射出成形法、片狀模造法、或樹脂點膠法等。 於鍍覆步驟中，對複數根引線11之表面實施鍍覆加工。例如使用包含錫等之焊接材料而進行電鍍等鍍覆加工。藉由實施鍍覆加工，而可抑制例如複數根引線11之氧化。 修整成型(T/F)步驟包含切斷複數根引線11與支持部12之間之連接部而切出半導體裝置10之步驟(修整步驟)、及使複數根引線11之外引線配合半導體裝置10之最終形狀而變形之步驟(成型步驟)。 藉由以上之步驟而可製造半導體裝置10。如圖6至圖8所示，半導體裝置10具備：複數根引線11，其分別包含外引線及自外引線延伸之內引線；半導體晶片2，其經由有機接著層6而搭載於複數根引線11上(例如內引線114之與彎曲之特定方向為相反側之面之至少一部分之上)，且具有複數個電極墊21；複數根接合線3，其將複數個電極墊21與複數根引線11連接；及密封樹脂層4，其將複數根引線11之內引線、半導體晶片2、及複數根接合線3密封。又，內引線111至內引線113之延伸方向之端部及與該端部相鄰之配線部115之第2端部之各者具有作為經剪切之凹部116a之一部分之凹部117。再者，半導體晶片2亦可搭載於圖8所示之半導體晶片2之與搭載面為相反側之複數根引線11之面。又，圖6至圖8所示之半導體裝置10為TSOP，亦可具有其他封裝構造。 上述實施形態係作為例而提出，並不意於限定發明之範圍。該等新穎之實施形態可由其他各種方式實施，於不脫離發明之主旨之範圍內，可進行各種省略、置換、變更。這些實施形態及其變化包含於發明之範圍或主旨內，並且包含於申請專利範圍所記載之發明及其均等範圍內。 [相關申請案] 本申請案享受以日本專利申請案2016-53321號(申請日：2016年3月17日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之所有內容。Hereinafter, embodiments will be described with reference to the drawings. The relationship between the thickness of each constituent element and the plane size, the ratio of the thickness of each constituent element, and the like described in the drawings may be different from the real thing. In the embodiment, substantially the same constituent elements are denoted by the same reference numerals, and descriptions thereof are appropriately omitted. As an example of a method for manufacturing a semiconductor device, an example of a method of manufacturing a semiconductor device as a TSOP (Thin Small Outline Package) will be described with reference to FIGS. 1 to 8. Examples of a method for manufacturing a semiconductor device include a lead frame preparation step, a lead frame processing step, a wafer mounting step, a wire bonding step, a resin sealing step, an exterior plating step, and a trimming (T / F) step. The order of the steps is not limited to the order listed above. FIG. 1 is a schematic plan view showing a structural example of a lead frame. FIG. 1 shows an XY plane of a lead frame including an X-axis and a Y-axis orthogonal to the X-axis. In the lead frame preparation step, as shown in FIG. 1, a lead frame 1 including a plurality of leads 11 and a support portion 12 supporting the plurality of leads 11 is prepared. The lead frame 1 is a metal plate on which elements such as a semiconductor wafer are mounted. Examples of the lead frame 1 include a lead frame using copper, a copper alloy, or an alloy of iron and nickel such as a 42 alloy. The lead frame 1 is processed in advance by die cutting or the like. Each of the plurality of leads 11 includes an outer lead and an inner lead extending from the outer lead. The inner lead is a portion supported by the sealing resin layer after the resin sealing step. A plating layer such as silver is provided on the inner lead in a region where wire bonding is performed on the upper surface side of the lead frame 1. The outer lead is a portion protruding from the sealing resin layer after the resin sealing step. Each of the leads other than the plurality of leads 11 is arranged in parallel on the XY plane along the Y axis, for example. Examples of the plurality of leads 11 include an input / output signal (IO), a data strobe signal (DQS), a lead enable signal (RE), a standby / busy signal (RB), a chip enable signal (CE), and an address. Leads for signals such as latch enable signal (ALE), write enable signal (WE), write protection signal (RP), or zero quotient signal (ZQ), or power supply (VCC), power supply (VPP), power supply ( VSS) and other power supply leads. As the signal, a differential signal may be used. At least one of the plurality of leads 11 may be an unconnected (NC) lead. The arrangement order of various leads is set according to the specifications or standards of the semiconductor device. The support portion 12 is provided so as to surround the plurality of leads 11. The support portion 12 is connected to each of one ends of the leads other than the plurality of leads 11. In addition, the support part 12 may support a lead for another semiconductor device in addition to the plurality of leads 11. FIG. 2 is a schematic diagram showing a part of the lead frame (a part of the area 100) shown in FIG. 1 when viewed from the lower surface side of the lead frame 1. FIG. In FIG. 2, the lower surface of the lead frame 1 is illustrated on the upper surface side, and the upper surface of the lead frame 1 is illustrated on the lower surface side. The Z axis in FIG. 2 is orthogonal to the X axis and the Y axis, and corresponds to the thickness direction of the lead frame 1. In FIG. 2, as the inner lead of the plurality of leads 11, the inner lead 111, the inner lead 112, the inner lead 113, and the inner lead 114 are illustrated. The inner lead 111 and the inner lead 112 are, for example, leads for input / output signals (IO) or data strobe signals (DQS). The inner lead 113 and the inner lead 114 are, for example, power supply (VSS) leads. At this time, since the inner lead 113 is provided between the inner lead 111 and the inner lead 112, interference between the signal of the inner lead 111 and the signal of the inner lead 112 can be suppressed. The lead frame shown in FIG. 1 has a wiring portion 115 that connects an end portion in the extending direction of the inner lead 111 to the inner lead 113 and a part of the inner lead 114. That is, the inner leads 111 to 113 are fixed by the support portion 12 and the wiring portion 115. The shape of the wiring portion 115 is not particularly limited as long as it can connect the inner lead 111 to the inner lead 113 and the inner lead 114. The wiring portion 115 may be regarded as a part of the inner lead 114. The inner leads 111 to 114 and the wiring portion 115 have a plating layer 20 provided on the upper surface side (lower surface side in FIG. 2) of the lead frame 1. The plating layer 20 is formed by, for example, a plating treatment using a plating material containing silver or the like. In order to ensure the bonding strength between the inner lead 111 to the inner lead 114 and the bonding wire during wire bonding described below, or to reduce the connection resistance with the semiconductor wafer, the plating layer 20 is provided in a region where wire bonding is performed. A connecting portion between an end portion in the extending direction (Y-axis direction) of the inner lead 111 to the inner lead 113 and the wiring portion 115 has a recessed portion (groove) 116 a on the upper surface side of the lead frame 1. The recessed portion 116 a is provided in a region that is more inside than the end in the width direction (X-axis direction) of each of the inner leads 111 to 113. A connection portion between the inner lead 114 and the wiring portion 115 has a recessed portion (groove) 116 b on the upper surface side of the lead frame 1. The recessed portion 116b shown in FIG. 2 extends from one end to the other end in the width direction of the inner lead 114, but it is not limited to this, and may be provided in the width of the connection portion of the inner lead 114 and the wiring portion 115 in the same manner as the recessed portion 116a The end of the direction is more inward. In addition, a plurality of recessed portions 116b may be provided. In FIG. 2, the recessed portion 116 a and the recessed portion 116 b have a V shape in a cross section including a YZ plane, and may have other shapes. In addition, the depth in the thickness direction of the lead frame 1 of the recessed portion 116b is preferably smaller than the depth in the thickness direction of the lead frame 1 of the recessed portion 116a. The recessed portions 116a and 116b are formed by, for example, embossing, laser processing, or blade processing. The recessed portion 116a and the recessed portion 116b are preferably formed before the punching step. If the recessed portion 116 a and the recessed portion 116 b are formed after the punching process, the lead frame 1 may be deformed unnecessarily. The recessed portion 116 a and the recessed portion 116 b are provided on the lower surface side of the lead frame 1, that is, on the surface opposite to the surface having the plating layer 20. The plating layer 20 is formed after forming the recessed part 116a and the recessed part 116b. Therefore, if the plating layer 20 is formed on the surface having the recessed portion 116a and the recessed portion 116b, the plating material may be deposited on the recessed portion 116a and the recessed portion 116b, and reliability may be reduced due to electric field concentration and the like. 3 and 4 are schematic cross-sectional views for explaining the processing steps of the lead frame. 3 and 4 show a YZ cross section including the Y-axis and the Z-axis of the lead frame 1. In FIGS. 3 and 4, as an example, a cross section including the inner lead 113 is illustrated. In the lead frame processing step, the lead frame 1 is placed on the platform 51 having the recessed portion 51 a so that the recessed portion 116 a and the recessed portion 116 b are on the lower side (the platform 51 side), and both ends of the wiring portion 115 are pressed by the pressing members 52. . At this time, the wiring portion 115 is overlapped with the recessed portion 51a. Next, the pressing member 53 is lowered along the Z axis toward the platform 51 side, and the pressing member 53 is pressed against the wiring portion 115 from the other side of the lead frame 1 on which the recessed portion 116a and the recessed portion 116b are formed on the opposite side to the wiring portion 115 to make wiring At least a part of the portion 115 is deformed, and a connection portion between the end portion in the extending direction of the inner lead 113 and the wiring portion 115 is cut with the recessed portion 116 a as a base point. The portion having the recess 116a is easier to cut than other regions. Moreover, since the recessed part 116a is provided inside more than the width direction end part of the inner lead 113, compared with the case where the recessed part 116a extended to the width direction end part of the inner lead 113, the generation | occurrence | production of the burr by cutting is suppressed. The wiring portion 115 is bent so as to be separated from the end portion in the extending direction of the inner lead 113 with the recessed portion 116 b as a base point. The portion having the recessed portion 116b is easier to bend than other regions. Therefore, unnecessary deformation can be suppressed. FIG. 5 is a schematic diagram showing a structural example of the deformed region 100 of the lead frame 1 as viewed from the upper surface side. In FIG. 5, the upper surface of the lead frame 1 is shown on the upper surface side, and the lower surface of the lead frame 1 is shown on the lower surface side. The cut wiring portion 115 of the connecting portion includes a first end portion connected to the inner lead 114 and a second end portion connected to the inner lead 111 when viewed from a direction perpendicular to the XY plane (Z-axis direction). The ends in the extending direction to the inner leads 113 are adjacent. The second end portion is bent from the inner lead 111 to the inner lead 111 along the cross section including the thickness direction of the inner lead 114 when viewed from a direction perpendicular to the YZ cross section, and is bent in a specific direction with the recess 116 b as a base point. Each of the end portion in the extending direction of the inner lead 111 to the inner lead 113 and the second end portion of the wiring portion 115 has a recessed portion 117 in a region more inward than the end portion in the width direction by cutting the recessed portion 116 a. The shape of the deformed wiring portion 115 is not particularly limited. As shown in FIG. 5, the wiring portion 115 has a region parallel to the extending direction of the inner lead 111 to the inner lead 113. Through the above steps, a part of the inner lead 111 to a part of the inner lead 114 are separated from each other. Similarly, a part of the inner leads of the other connections is separated from each other by the above steps. By making the connection portion between the inner lead 111 to the inner lead 113 and the wiring portion 115 thin, the load required for cutting can be reduced. Thus, as the pressing member 53, one of a plurality of bonding heads provided in a wafer bonding apparatus used when mounting a semiconductor wafer in the wafer mounting step can be applied. In order to electrically separate the inner lead 111 to the inner lead 114, a method of removing a part of the connection portion by a punching process is considered. In a case where a part of the connection portion is removed by punching, the required cutting position of one of the inner lead 111 to the inner lead 113 is two or more. Therefore, the load required for punching is greater than the load required for shearing of the above-mentioned connection portion. Therefore, in order to perform the punching process, it is necessary to provide a pressing mechanism which can provide a higher load, unlike a mechanism for cutting the connection portion. Therefore, the configuration of the processing device becomes complicated. In addition, when die-cutting is performed, when a part of the lead frame is die-cut, chips (a removed portion) are generated. Chips of the lead wire will not only become a source of pollution to the manufacturing environment, but also need a mechanism for discharging the chip of the lead wire. Therefore, it is preferable not to generate chips. When the lead frame is processed by die-cutting, the lead frame is transported to the wafer bonding apparatus and the semiconductor wafer is mounted after the processing, so that the hot lead is easily deformed during the transport. Therefore, it is necessary to provide a fixing tape for fixing a plurality of leads. Since the fixing tape easily absorbs moisture, it is easy to peel off the resin from the lead or the subsequent sealed semiconductor wafer. In addition, when the fixing tape is provided, the lead frame becomes substantially thick. Therefore, the number of lead frames that can be housed in the housing is reduced, so that the transportation cost is increased. Furthermore, dendritic migration easily occurs in the fixing band. In some cases, migration may cause a short circuit between the leads. In view of this, when the above-mentioned connection portion is cut using a wafer bonding apparatus and a part of each inner lead is separated, a semiconductor wafer can be mounted using the same wafer bonding apparatus after the lead frame processing step. Therefore, it is possible to reduce the transportation of the lead frame. Therefore, even if a fixing tape is not provided, it is possible to suppress unnecessary deformation of the lead. In addition, the material cost and processing cost of the fixing belt can be reduced, thereby reducing the manufacturing cost. Furthermore, since the wiring portion can be retained and a part of each inner lead can be separated, the chip of the lead can be reduced compared to the punching process. FIG. 6 is a schematic plan view showing a structural example of a semiconductor device that can be manufactured using the method of manufacturing a semiconductor device. FIG. 6 shows an XY plane of the semiconductor device. FIG. 7 is a schematic plan view showing a part (a part of the region 101) of the semiconductor device shown in FIG. 6 as viewed from the upper surface side of the lead 11. FIG. FIG. 8 is a schematic cross-sectional view of a part (a part of a region 101) of the semiconductor device shown in FIG. 6. FIG. FIG. 8 shows a cross section including the inner lead 113 as an example. In addition, in FIG. 7 and FIG. 8, the inside of the sealing resin layer 4 is shown perspectively for convenience. For the parts in common with FIGS. 1 to 5, the descriptions of FIGS. 1 to 5 are appropriately cited. In the wafer mounting step, the semiconductor wafer 2 is mounted on the inner leads of the plurality of leads 11 such as the inner leads 111 to 114. As shown in FIG. 7, the semiconductor wafer 2 includes a plurality of electrode pads 21 including an electrode pad 211 to an electrode pad 215. The plurality of electrode pads 21 are exposed on the surface of the semiconductor wafer 2. The plurality of electrode pads 21 may be provided along one side of the semiconductor wafer 2. By providing a plurality of electrode pads 21 along one side of the semiconductor wafer 2, the wafer size can be reduced. Examples of the semiconductor wafer 2 include semiconductor wafers used in a memory element such as a NAND (Not AND) type flash memory or a memory controller. The semiconductor wafer 2 is mounted using, for example, a wafer bonding device used for cutting a connection portion between an end portion in the extending direction of the inner lead 111 to the inner lead 113 and the wiring portion 115. The semiconductor wafer 2 is mounted on the inner leads 111 to 114 using another one of a plurality of bonding heads different from the pressing member 53. The semiconductor wafer 2 is provided with a recessed portion 116 a and a recessed portion among the inner leads 111 such as the inner leads 111 to 114 through an organic bonding layer 6 such as a die attach film having insulation properties. The other side of one side of 116b. At this time, the inner leads of the plurality of leads 11 are adhered to the organic bonding layer 6. Therefore, since the inner leads of the plurality of leads 11 are fixed, unnecessary deformation of the leads can be suppressed in the subsequent steps. The semiconductor wafer 2 is preferably mounted after cutting the connection portion between the inner lead 111 to the inner lead 113 and the wiring portion 115. If the connection portion is cut after the semiconductor wafer is mounted, the semiconductor wafer may be damaged. For example, after the lead frame 1 is placed (mounted) in a wafer bonding apparatus, the connection portion is cut. Thereafter, the lead frame 1 is not removed (unloaded) from the wafer bonding apparatus, and a semiconductor wafer 2 described below is mounted on the lead frame 1. After the semiconductor wafer 2 is mounted, the lead frame 1 is removed (unloaded) from the wafer bonding apparatus, and subsequent steps such as the following wire bonding step are performed. In the wire bonding step, a plurality of bonding wires 3 electrically connecting the plurality of electrode pads 21 and the plurality of leads 11 are formed. In FIG. 7, a bonding wire 31 for electrically connecting the inner lead 111 and the electrode pad 211 through the plating layer 20 and a bonding wire 32 for electrically connecting the inner lead 112 and the electrode pad 212 through the plating layer 20 are shown. , A bonding wire 33 for electrically connecting the inner lead 113 and the electrode pad 213 through the plating layer 20, a bonding wire 34 for electrically connecting the inner lead 114 and the electrode pad 214 through the plating layer 20, and the inner lead 114 A bonding wire 35 electrically connected to the electrode pad 215 through the plating layer 20. Examples of the bonding wire 3 include a gold wire, a silver wire, and a copper wire. The surface of the copper wire may be covered with a palladium film. The bonding wire 3 is electrically connected to the lead and the electrode pad by wire bonding. In the resin sealing step, a sealing resin layer 4 is formed which seals the inner leads of the plurality of leads 11 such as the inner leads 111 to 114, the semiconductor wafer 2, and the plurality of bonding wires 3 such as the bonding wires 31 to 35. The sealing resin layer 4 is provided so as to cover the upper and lower surfaces of the inner leads of the plurality of leads. In addition, as shown in FIG. 8, the sealing resin layer 4 is also filled between the end portion in the extending direction of the inner lead 111 to the inner lead 113 and the wiring portion 115. The sealing resin layer 4 contains an inorganic filler such as SiO 2 . The inorganic filler may include, for example, aluminum hydroxide, calcium carbonate, aluminum oxide, boron nitride, titanium oxide, or barium titanate, in addition to SiO 2 . The inorganic filler is granular, for example, and has a function of adjusting the viscosity, hardness, and the like of the sealing resin layer 4. The content of the inorganic filler in the sealing resin layer 4 is, for example, 60% or more and 90% or less. As the sealing resin layer 4, a mixture of an inorganic filler and an insulating organic resin material can be used, for example. Examples of the organic resin material include epoxy resin. Examples of the method for forming the sealing resin layer 4 include a transfer molding method using a mixture of an inorganic filler and an organic resin, a compression molding method, an injection molding method, a sheet molding method, and a resin dispensing method. In the plating step, the surface of the plurality of leads 11 is subjected to a plating process. For example, a plating process such as plating is performed using a solder material containing tin or the like. By performing the plating process, for example, oxidation of the plurality of leads 11 can be suppressed. The trimming (T / F) step includes a step of cutting out the semiconductor device 10 by cutting the connection portion between the plurality of leads 11 and the support portion 12 (trimming step), and fitting the leads other than the plurality of leads 11 to the semiconductor device 10 A step of deforming the final shape (forming step). The semiconductor device 10 can be manufactured by the above steps. As shown in FIGS. 6 to 8, the semiconductor device 10 includes a plurality of leads 11 each including an outer lead and an inner lead extending from the outer lead; and a semiconductor wafer 2 mounted on the plurality of leads 11 via an organic bonding layer 6. (For example, at least a part of the surface of the inner lead 114 that is opposite to the specific direction of the bending) and has a plurality of electrode pads 21; a plurality of bonding wires 3 that connect the plurality of electrode pads 21 and the plurality of leads 11 Connection; and a sealing resin layer 4 which seals the inner leads of the plurality of leads 11, the semiconductor wafer 2, and the plurality of bonding wires 3. Further, each of the end portion in the extending direction of the inner lead 111 to the inner lead 113 and the second end portion of the wiring portion 115 adjacent to the end portion has a recessed portion 117 as a part of the cutout recessed portion 116a. In addition, the semiconductor wafer 2 may be mounted on the surface of the plurality of leads 11 on the semiconductor wafer 2 shown in FIG. 8 opposite to the mounting surface. The semiconductor device 10 shown in FIGS. 6 to 8 is a TSOP, and may have other packaging structures. The above embodiments are proposed as examples, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and variations thereof are included in the scope or spirit of the invention, and are included in the invention described in the scope of patent application and its equivalent scope. [Related Applications] This application enjoys priority based on Japanese Patent Application No. 2016-53321 (application date: March 17, 2016). This application contains all contents of the basic application by referring to the basic application.

1‧‧‧引線框架
2‧‧‧半導體晶片
3‧‧‧接合線
4‧‧‧密封樹脂層
6‧‧‧有機接著層
10‧‧‧半導體裝置
11‧‧‧引線
12‧‧‧支持部
20‧‧‧鍍覆層
21‧‧‧電極墊
31～35‧‧‧接合線
51‧‧‧平台
51a‧‧‧凹部
52‧‧‧按壓構件
53‧‧‧推壓構件
100‧‧‧區域
101‧‧‧區域
111～114‧‧‧內引線
115‧‧‧配線部
116a‧‧‧凹部
116b‧‧‧凹部
117‧‧‧凹部
211～215‧‧‧電極墊
X、Y、Z‧‧‧方向1‧‧‧lead frame
2‧‧‧ semiconductor wafer
3‧‧‧ bonding wire
4‧‧‧sealing resin layer
6‧‧‧ Organic Adhesive Layer
10‧‧‧Semiconductor device
11‧‧‧ Lead
12‧‧‧Support Department
20‧‧‧Plating
21‧‧‧electrode pad
31 ～ 35‧‧‧bonding line
51‧‧‧platform
51a‧‧‧Concave
52‧‧‧Pressing member
53‧‧‧Pushing member
100‧‧‧ area
101‧‧‧area
111 ～ 114‧‧‧Inner lead
115‧‧‧wiring department
116a‧‧‧Concave
116b‧‧‧Concave
117‧‧‧ recess
211 ～ 215‧‧‧electrode pad
X, Y, Z‧‧‧ directions

圖1係表示引線框架之構造例之俯視模式圖。 圖2係表示引線框架之一部分之模式圖。 圖3係用以對引線框架加工步驟進行說明之剖視模式圖。 圖4係用以對引線框架加工步驟進行說明之剖視模式圖。 圖5係表示引線框架加工步驟後之引線框架之一部分之模式圖。 圖6係表示半導體裝置之構造例之俯視模式圖。 圖7係表示半導體裝置之一部分之俯視模式圖。 圖8係表示半導體裝置之一部分之構造例之剖視模式圖。FIG. 1 is a schematic plan view showing a structural example of a lead frame. Fig. 2 is a schematic view showing a part of a lead frame. FIG. 3 is a schematic cross-sectional view for explaining the processing steps of the lead frame. FIG. 4 is a schematic cross-sectional view for explaining the processing steps of the lead frame. FIG. 5 is a schematic diagram showing a part of the lead frame after the lead frame processing step. FIG. 6 is a schematic plan view showing a configuration example of a semiconductor device. FIG. 7 is a schematic plan view showing a part of a semiconductor device. FIG. 8 is a schematic cross-sectional view showing a configuration example of a part of a semiconductor device.

1‧‧‧引線框架 1‧‧‧lead frame

11‧‧‧引線 11‧‧‧ Lead

12‧‧‧支持部 12‧‧‧Support Department

100‧‧‧區域 100‧‧‧ area

X、Y‧‧‧方向 X, Y‧‧‧ directions

Claims (5)

一種半導體裝置之製造方法，其具備如下步驟：一邊按壓第1內引線，一邊自引線框架之與形成著第1凹部之一面為相反側之另一面將推壓構件壓抵於配線部，使上述引線框架變形，以上述第1凹部為基點，剪切上述第1內引線之延伸方向之端部與上述配線部之連接部，並且使上述配線部與上述端部分離；上述引線框架包括：第1引線，其包含第1外引線及自上述第1外引線延伸之上述第1內引線；第2引線，其包含第2外引線及自上述第2外引線延伸之第2內引線；上述配線部，其將上述第2內引線與上述第1內引線之延伸方向之端部之間連接；及支持部，其連接於上述第1外引線及上述第2外引線；且上述第1內引線之延伸方向之端部與上述配線部之間之連接部於較寬度方向之端部更內側之區域具有上述第1凹部； 將具備第1電極墊與第2電極墊之半導體晶片經由接著層而搭載於上述引線框架之上述另一面上； 形成將上述第1電極墊與上述第1引線電性連接之第1接合線、及將上述第2電極墊與上述第2引線電性連接之第2接合線； 形成將上述第1內引線、上述第2內引線、上述配線部、上述半導體晶片、上述第1接合線、及上述第2接合線密封之密封樹脂層； 將上述支持部與上述第1外引線及上述第2外引線之間之連接部切斷。A method for manufacturing a semiconductor device, comprising the steps of pressing a pressing member against a wiring portion from the other side of a lead frame opposite to a surface on which a first recess is formed while pressing a first inner lead, so that The lead frame is deformed, using the first recessed portion as a base point, cutting an end portion in the extending direction of the first inner lead and the wiring portion, and separating the wiring portion from the end portion; the lead frame includes: 1 lead including the first outer lead and the first inner lead extending from the first outer lead; second lead including the second outer lead and the second inner lead extending from the second outer lead; the wiring A portion that connects the second inner lead and an end in the extending direction of the first inner lead; and a support portion that connects the first outer lead and the second outer lead; and the first inner lead The connecting portion between the end portion in the extending direction and the wiring portion has the above-mentioned first recessed portion in an area more inward than the end portion in the width direction; a semiconductor wafer having the first electrode pad and the second electrode pad is passed through the bonding layer. Mounted on the other side of the lead frame; forming a first bonding wire for electrically connecting the first electrode pad to the first lead; and forming a second bonding wire for electrically connecting the second electrode pad to the second lead. Bonding wire; forming a sealing resin layer that seals the first inner lead, the second inner lead, the wiring portion, the semiconductor wafer, the first bonding wire, and the second bonding wire; and sealing the support portion with the first The connection between the 1 outer lead and the second outer lead is cut. 如請求項1之半導體裝置之製造方法，其中上述推壓構件為設置於將上述半導體晶片搭載於上述引線框架上之晶片接合裝置之複數個接合頭之一。The method for manufacturing a semiconductor device according to claim 1, wherein the pressing member is one of a plurality of bonding heads provided in a wafer bonding device in which the semiconductor wafer is mounted on the lead frame. 如請求項1或2之半導體裝置之製造方法，其中上述第2內引線與上述配線部之間之連接部具有較上述第1凹部之深度更淺之第2凹部，且 於上述分離步驟中，上述配線部係以將上述第2凹部作為基點而與上述第1內引線之延伸方向之端部分離之方式彎曲。For example, the method for manufacturing a semiconductor device according to claim 1 or 2, wherein the connection portion between the second inner lead and the wiring portion has a second recess portion having a shallower depth than the first recess portion, and in the separating step, The wiring portion is bent so that the second recessed portion is used as a base point and is separated from an end portion in the extending direction of the first inner lead. 如請求項3之半導體裝置之製造方法，其中上述第1內引線包含設置於上述另一面側之第1鍍覆層， 上述第2內引線包含設置於上述另一面側之第2鍍覆層， 上述第2凹部設置於上述一面側， 第1接合線經由上述第1鍍覆層而電性連接於上述第1引線，且 第2接合線經由上述第2鍍覆層而電性連接於上述第2引線。The method for manufacturing a semiconductor device according to claim 3, wherein the first inner lead includes a first plating layer provided on the other surface side, and the second inner lead includes a second plating layer provided on the other surface side, The second recessed portion is provided on the one surface side, the first bonding wire is electrically connected to the first lead through the first plating layer, and the second bonding wire is electrically connected to the first lead through the second plating layer. 2 leads. 一種半導體裝置，其包括： 第1引線，其包含第1外引線及自上述第1外引線延伸之第1內引線； 第2引線，其包含第2外引線及自上述第2外引線延伸之第2內引線； 配線部，其具有連接於上述第2內引線之一部分之第1端部、及與上述第1內引線之延伸方向之端部相鄰之第2端部，且上述第2端部以於上述第2內引線之包含厚度方向之截面上與上述第1內引線之延伸方向之端部分離之方式朝特定方向彎曲； 半導體晶片，其具有第1電極墊及第2電極墊，且經由接著層而搭載於上述第1及上述第2內引線之至少一者之與上述特定方向為相反側之面的至少一部分之上； 第1接合線，其將上述第1引線與上述第1電極墊之間電性連接； 第2接合線，其將上述第2引線與上述第2電極墊之間電性連接；及 密封樹脂層，其將上述第1內引線、上述第2內引線、上述配線部、上述半導體晶片、上述第1接合線、及上述第2接合線密封；且 上述第1內引線之延伸方向之端部及上述配線部之第2端部之各者於較寬度方向之端部更內側之區域具有凹部。A semiconductor device includes: a first lead including a first outer lead and a first inner lead extending from the first outer lead; a second lead including a second outer lead and a second lead extending from the second outer lead A second inner lead; a wiring portion having a first end connected to a portion of the second inner lead and a second end adjacent to an end in an extending direction of the first inner lead; and the second The end portion is bent in a specific direction so as to be separated from the end portion in the extending direction of the first inner lead on a section including the thickness direction of the second inner lead; the semiconductor wafer includes a first electrode pad and a second electrode pad And is mounted on at least a part of a surface of at least one of the first and second inner leads opposite to the specific direction through an adhesive layer; a first bonding wire that connects the first lead to the above The first electrode pads are electrically connected; the second bonding wire electrically connects the second lead and the second electrode pad; and a sealing resin layer that connects the first inner lead and the second inner lead. Lead, the wiring portion, the semiconductor wafer The first bonding wire and the second bonding wire are sealed; and each of the end portion in the extending direction of the first inner lead and the second end portion of the wiring portion is located in an area more inward than the end portion in the width direction. With a recess.
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