CN106531712B - Manufacturing method, semiconductor device and the lead frame of semiconductor device - Google Patents
Manufacturing method, semiconductor device and the lead frame of semiconductor device Download PDFInfo
- Publication number
- CN106531712B CN106531712B CN201610236159.2A CN201610236159A CN106531712B CN 106531712 B CN106531712 B CN 106531712B CN 201610236159 A CN201610236159 A CN 201610236159A CN 106531712 B CN106531712 B CN 106531712B
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- China
- Prior art keywords
- lead
- wiring portion
- extending direction
- semiconductor device
- electronic pads
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Embodiments of the present invention provide manufacturing method, semiconductor device and the lead frame of a kind of semiconductor device that can inhibit lead that extra deformation occurs.The manufacturing method of the semiconductor device of embodiment includes the following steps: that one side squeezes the 1st lead, so that biasing member is pressed against the upper surface of the wiring portion of the 2nd lead and is deformed at least part of wiring portion on one side, and by the end on the extending direction of the 1st lead and the linking part between wiring portion cut off and make wiring portion and end mutually from；Carry semiconductor chip；Form the 1st and the 2nd closing line；Form sealing resin layer；By the linking part cutting between support portion and the 1st and the 2nd outer lead.
Description
[related application]
Present application is enjoyed with Japanese patent application 2015-181479 (applying date: on September 15th, 2015) as basic Shen
Please case priority.Present application full content comprising basic application case by referring to the basis application case.
Technical field
Embodiments of the present invention are related to manufacturing method, semiconductor device and the lead frame of a kind of semiconductor device.
Background technique
In the semiconductor device with the lead comprising outer lead and lead and semiconductor chip, closing line is utilized
It will be electrically connected between the electronic pads of semiconductor chip and lead.Therefore, the distance between electronic pads and outer lead more it is long then more
Lead need be made to extend near electronic pads longlyer from outer lead.
Long lead is easily deformed in the manufacturing process of semiconductor device.It, can if lead deforms
There is following situation: for example, semiconductor chip is easy to peel off from lead, or closing line and lead when carrying out wire bonding
Between bad connection occurs.
Summary of the invention
Embodiments of the present invention provide a kind of manufacturing method of the semiconductor device of extra deformation that can inhibit lead, half
Conductor device and lead frame.
The manufacturing method of the semiconductor device of embodiment include the following steps: a face swaged lead frame the 1st in draw
Line will push against component on one side and be pressed against the upper surface of wiring portion and deform at least part of wiring portion, by end and wiring portion
Between linking part cutting and make wiring portion and end phase from, the lead frame include the 1st outer lead and from the 1st outer lead
Extend the 1st lead the 1st lead, including the 2nd outer lead and from the 2nd outer lead extend the 2nd lead the 2nd lead,
And it is linked to the support portion of the 1st outer lead and the 2nd outer lead, the 2nd lead includes and the end on the extending direction of the 1st lead
The wiring portion of portion's connection；It will include the semiconductor-chip-mounting of the 1st electronic pads and the 2nd electronic pads on lead frame；Being formed will
1st electronic pads the 1st closing line being electrically connected with the 1st lead and the 2nd closing line for being electrically connected the 2nd electronic pads with the 2nd lead；Shape
The sealing resin layer that pairs of 1st lead, the 2nd lead, semiconductor chip, the 1st closing line and the 2nd closing line are sealed；
And the linking part between support portion and the 1st outer lead and the 2nd outer lead is cut off.
Detailed description of the invention
Fig. 1 is the floor map for indicating the structure example of lead frame.
Fig. 2 is the enlarged drawing for indicating a part of lead frame shown in FIG. 1.
Fig. 3 is the schematic cross-section for illustrating lead frame procedure of processing.
Fig. 4 is the schematic cross-section for illustrating lead frame procedure of processing.
Fig. 5 is the floor map for indicating the structure example of semiconductor device.
Fig. 6 is the enlarged drawing for indicating a part of semiconductor device shown in fig. 5.
Fig. 7 is the schematic cross-section for indicating the structure example of a part of semiconductor device shown in fig. 5.
Specific embodiment
Hereinafter, being illustrated referring to schema to embodiment.The thickness and plane meter for each component recorded in schema
The very little ratio of thickness of relationship, each component etc. is different from material object sometimes.Moreover, in embodiment, for substance
Identical constituent element marks the same symbol and suitably omits the description.
As manufacturer's rule of semiconductor device, it is directed to TSOP (Thin Small Outline referring to Figure 1 to Figure 7
Packeage:TSOP, thin-type small-size installation) manufacturer's rule of type semiconductor device is illustrated.The system of semiconductor device
The method example of making includes that lead frame preparation process, lead frame procedure of processing, chip carrying step, wire bonding step, resin are close
Seal step, coating step, finishing molding (T/F) step.The sequence of each step is not limited to described enumerate sequentially.
Fig. 1 is the floor map for indicating the structure example of lead frame.Fig. 1 shows include X-axis and Y-axis orthogonal to X-axis
Lead frame X-Y plane.
In lead frame preparation process, as shown in Figure 1, preparing that there are multiple leads 11 and supporting the support of multiple leads 11
The lead frame 1 in portion 12.Lead frame 1 is the metal plate for carrying the elements such as semiconductor chip.As lead frame 1, can enumerate
For example, by using the lead frame of the alloy of the iron such as copper, copper alloy or 42 alloys and nickel etc..Lead frame 1 is added by punching press in advance
Work etc. is processed.
The lead that multiple leads 11 respectively contain outer lead and extend from the outer lead.Lead is walked in resin seal
Rapid rear support is in the part of sealing resin layer.Outer lead is after resin-sealing step from sealing resin layer part outstanding.It is more
The outer lead of a lead 11 is respectively for example arranged side by side along Y-axis in X-Y plane.
As multiple leads 11, it can be mentioned, for example input/output signal (IO), data strobe signal (DQS), lead are enabled
Signal (RE), Ready/Busy signal (RB), chip enable signal (CE), address latch enable signal (ALE), the enabled letter of write-in
The signals lead such as number (WE), write protect signal (RP) or zero quotient's signal (ZQ) or power supply (VCC), power supply (VPP),
Power supplys leads such as power supply (VSS) etc..As the signal, it is possible to use differential wave.Multiple leads 11, which can also have, not to be connected
Connect the lead of (NC).Putting in order for various leads can be set according to the specification of semiconductor device or pattern etc..
Support portion 12 is arranged in a manner of surrounding multiple leads 11.Support portion 12 is linked to the outer of multiple leads 11 respectively
Lead.In addition, support portion 12 also can support the lead of multiple semiconductor devices.
Fig. 2 is the enlarged drawing for indicating a part (a part in region 100) of lead frame shown in FIG. 1.In Fig. 2, make
For the lead of multiple leads 11, lead 111, lead 112, lead 113, lead 114 are illustrated.
Lead 111 and lead 112 are, for example, signal lead.Lead 113 and lead 114 are, for example, that power supply is used
Lead.At this point, being equipped with lead 113 between lead 111 and lead 112, the signal of lead 111 can be inhibited as a result,
Interference between the signal of lead 112.
Lead 114 has the wiring portion 115 with the end connection on the extending direction of lead 111 to lead 113.
That is, lead 111 to lead 113 is fixed by lead 114 and support portion 12.As long as the shape of wiring portion 115 is that can incite somebody to action
Lead 111 connects junction configuration with lead 114 to lead 113 and is then not particularly limited.
As shown in Fig. 2, the width of the linking part between the end on the extending direction of lead 111 and wiring portion 115 is excellent
Choosing is narrower than the maximum width of lead 111.Again it is preferred to be end and wiring on the extending direction of lead 112
The width of linking part between portion 115 is narrower than the maximum width of lead 112.Preferably on the extending direction of lead 113
End and wiring portion 115 between linking part width it is narrower than the maximum width of lead 113.The linking part can also be company
The most narrow region of the width for the lead being knotted.The width of the linking part for example can be by being added using press process or laser
Work etc. forms recess 116 in the linking part and is adjusted.
Fig. 3 is the schematic cross-section for being illustrated to lead frame procedure of processing.Fig. 3 indicates to include lead frame 1
Y-axis and the Z axis orthogonal with X-axis and Y-axis the section Y-Z.Z axis is equivalent to the thickness direction of lead frame 1.In Fig. 3, as one
Example and illustrate comprising the section including lead 113.
In lead frame procedure of processing, lead frame 1 is placed on the platform 51 with groove 51a, extruding is utilized
Both ends (lead 113 of the component 52 for the end on the extending direction of lead 113 and the linking part between wiring portion 115
And lead 114) squeezed.At this point, wiring portion 115 is made to be overlapped in groove 51a.
Then, decline biasing member 53 to 51 side of platform along Z axis, biasing member 53 is made to compress the upper of wiring portion 115
Surface and deform at least part of wiring portion 115.Between end on the extending direction of lead 113 and wiring portion 115
Linking part it is narrower than the maximum width of lead 113, so being easier to cut off than other regions.Therefore, if becoming wiring portion 115
Shape, then can be cut off the linking part between the end on the extending direction of lead 113 and wiring portion 115 and can make to be routed
Portion 115 on the extending direction of lead 113 end mutually from.Equally, by lead 111 and lead 112 and wiring portion 115
Between linking part cut off and make wiring portion 115 on the extending direction of lead 111 and lead 112 end phase from.
For wiring portion 115 after being switched off linking part, it is configured to adjacent when from the direction vertical with X-Y plane
End on the extending direction of lead 111 to lead 113.Moreover, be switched off for the wiring portion after linking part 115,
To draw along the section including the thickness direction comprising lead 114 with interior when from the direction vertical with the section Y-Z
Line 111 to 113 phase of lead from mode be bent.The shape of deformed wiring portion 115 is not particularly limited, can be such as Fig. 3 institute
Show, wiring portion 115 has the region parallel with the extending direction of lead 111 to lead 113.Using above step, make interior
A part of a part of lead 111 to lead 114 is separated from each other.Equally, still link other using the step
A part of lead is separated from each other.
By making lead 111 to the width of the linking part between lead 113 and wiring portion 115 narrow, it can reduce and cut
Required load when disconnected.It is used as biasing member 53 as a result, use when carrying semiconductor chip in chip carrying step can be used
Chip bonding device on an engaging head in set multiple engaging heads.
When being processed using punch process to lead frame, the required load of when punching press, which is greater than, cuts off the linking part
The load of Shi Suoxu.Therefore, the linking part is cut off in order to use the processing unit (plant) for carrying out punch process, in addition to punching press
Except mechanism, the dipper crowding gear that can assign the load less than punching press need be set.Therefore, the composition of processing unit (plant) becomes complicated.
Moreover, if being processed using the processing unit (plant) for carrying out punch process to lead frame, when to lead frame
A part carry out punching press when be easy to produce cutting bits.The cutting bits of lead can become the pollution sources of manufacturing environment, it is advantageous to
Be turned off bits it is less.
When being processed using punch process to lead frame, lead frame is transported to chip after processing and engages dress
It sets and carries semiconductor chip, so lead is easy to deform during conveying.Therefore, need be arranged to multiple leads into
The fixed fixing belt of row.Fixing belt is easy to absorb moisture, therefore is easy to peel off from lead.Moreover, if having fixing belt,
Lead frame meeting substance thickens.Therefore, the lead frame quantity that can be contained in accepting box is reduced, and therefore, conveying cost increases
Greatly.Moreover, fixing belt easily causes the migration of ingotism shape.If causing to migrate, cause between lead sometimes
Short circuit etc..
In this regard, drawing when cutting off the linking part using chip bonding device and separating a part of each lead
After wire frame procedure of processing semiconductor chip can be carried using identical chip bonding device.Therefore, it can be reduced lead frame
Conveying.Even if not set fixing belt as a result, it can also inhibit lead that extra deformation occurs.Moreover, the fee of material of fixing belt and add
Expenses of labour is cut down, so as to cut down manufacturing cost.In addition, wiring portion can be retained and separate a part of each lead, therefore, with
Punch process is compared, and can be reduced the cutting bits of lead.
The shape of the linking part between end and wiring portion 115 on lead 111 to the extending direction of lead 113 is simultaneously
It is not limited to shape shown in Fig. 2.Fig. 4 is the section signal being illustrated for other examples to lead frame procedure of processing
Figure.The section Y-Z for indicating lead frame 1 same as Fig. 3 Fig. 4.
As shown in figure 4, the thickness of the linking part between the end on the extending direction of lead 113 and wiring portion 115
It is thin than the maximum gauge of lead 113.Equally, the end on the extending direction of lead 111 and the company between wiring portion 115
Maximum gauge of the thickness of knot also than lead 111 is thin.End and wiring portion 115 on the extending direction of lead 112
Between linking part maximum gauge of the thickness also than lead 112 it is thin.The thickness of the linking part can be by, for example,
Coining processing, laser processing or scraper processing etc. form recess 116 along the depth direction of the linking part and are adjusted
It is whole.The linking part can also be the most thin region on the lead linked.In the width and thickness of the linking part extremely
Few one is adjusted as described above.
As shown in figure 4, when the thickness of the end on the extending direction of lead 113 and the linking part between wiring portion 115
When maximum gauge than lead 113 is thin, the linking part is easier to cut off than other regions.It therefore, can be by lead 113
Linking part cutting between end on extending direction and wiring portion 115, and the extension of wiring portion 115 Yu lead 113 can be made
End on direction mutually from.Equally, can by between the end on the extending direction of lead 111 and wiring portion 115 linking part,
And the linking part cutting between the end on the extending direction of lead 112 and wiring portion 115.
Fig. 5 is to indicate that the plane of the structure example for the semiconductor device that the manufacturing method of semiconductor device can be used to manufacture is illustrated
Figure.The X-Y plane of Fig. 5 expression semiconductor device.Fig. 6 is a part (region 101 for indicating semiconductor device shown in fig. 5
A part) enlarged drawing.Fig. 7 is the section signal of a part (a part in region 101) of semiconductor device shown in fig. 5
Figure.It is indicated as an example comprising the section including lead 113 in Fig. 7.In addition, for convenience, transmission is close in Fig. 5 and Fig. 6
The inside of envelope resin layer 4 is illustrated.The explanation of Fig. 1 to Fig. 4 is suitably continued to use for the part common with Fig. 1 to Fig. 4.
In chip carrying step, semiconductor chip 2 is equipped on lead 111 to multiple leads 11 such as lead 114
Lead on.As shown in fig. 6, semiconductor chip 2 has the multiple electrode pads 21 comprising electronic pads 211 to electronic pads 215.It is more
A electronic pads 21 are exposed to the surface of semiconductor chip 2.Multiple electrode pads 21 can also be set along one side of semiconductor chip 2.
By the multiple electrode pads of setting on one side 21 along semiconductor chip 2, chip size can be reduced.As semiconductor chip 2, can arrange
Citing semiconductor chip as used in the memory elements such as NAND-type flash memory or storage control etc..
As semiconductor chip 2, can be used for example when by the end on the extending direction of lead 111 to lead 113
The chip bonding device that uses when linking part cutting between wiring portion 115 and carried.For example, semiconductor chip 2 can
Lead 111 is equipped on to lead 114 using another engaging head in the multiple engaging heads for being different from biasing member 53
On.Semiconductor chip 2 can be equipped on lead 111 to lead via organic bondings layers 6 such as bonding die films with insulating properties
On the lead of multiple leads 11 such as 114.At this point, the lead of multiple leads 11 is adhered to organic bonding layer 6.It is multiple as a result,
The lead of lead 11 is fixed, so extra deformation occurs for lead in the step of capable of inhibiting hereafter.
Semiconductor chip 2 is preferably cut by lead 111 to the linking part between lead 113 and wiring portion 115
It is carried after disconnected.If cutting off the linking part after carrying semiconductor chip, semiconductor chip is damaged sometimes.
In online engagement step, the multiple closing lines 3 for being electrically connected multiple electrode pads 21 with multiple leads 11 are formed.Fig. 6
In, it illustrates and is electrically connected by closing line 31 that lead 111 is electrically connected with electronic pads 211, by lead 112 with electronic pads 212
Closing line 32, be electrically connected by closing line 33 that lead 113 is electrically connected with electronic pads 213, by lead 114 and electronic pads 214
The closing line 34 connect and the closing line 35 for being electrically connected lead 114 with electronic pads 215.
As closing line 3, it can be mentioned, for example gold thread, silver wire, copper wire etc..The surface of copper wire can also cover palladium film.Closing line 3
Lead and electronic pads are electrically connected to using wire bonding.
In resin-sealing step, forms the lead to lead 111 to multiple leads 11 such as lead 114, partly leads
The sealing resin layer 4 that body chip 2 and closing line 31 are sealed to multiple closing lines 3 such as closing line 35.Sealing resin layer 4 is
It is arranged in a manner of covering the upper surface and the lower surface of lead of multiple leads.Moreover, as shown in fig. 7, sealing resin layer 4
Between the end being filled on lead 111 to the extending direction of lead 113 and wiring portion 115.
Sealing resin layer 4 contains SiO2Equal inorganic fills material.Moreover, as inorganic fill material, in addition to SiO2Except, may be used also
Including, for example, aluminium hydroxide, calcium carbonate, aluminium oxide, boron nitride, titanium oxide or barium titanate etc..Inorganic fill material is, for example, grain
Shape, and have the function of adjusting the viscosity of sealing resin layer 4 or hardness etc..The content of inorganic fill material in sealing resin layer 4
For example, 60% or more 90% or less.As sealing resin layer 4, such as inorganic fill material and insulating properties organic resin material can be used
The mixture of material.As organic resin material, it can be mentioned, for example epoxy resin.
As the formation method of sealing resin layer 4, it can be mentioned, for example the mixtures for using inorganic fill material and organic resin etc.
, transfer moudling, compression molding, injection molding, sheet molding method or resin distribution method etc..
In coating step, plating processing is implemented to the surface of multiple leads 11.It can be such as using the welding material stanniferous
Material carries out the plating processing such as being electroplated.By implementing plating processing, it can for example inhibit the oxidation of multiple leads 11.
Finishing molding (T/F) step includes that the linking part cutting between multiple leads 11 and support portion 12 is cut and partly led
The step of body device 10 (pre-shaping step) and make multiple leads 11 outer lead conjunction with semiconductors device 10 final shape and become
The step of shape (forming step).
Semiconductor device 10 can be manufactured by above step.As shown in Figures 5 to 7, semiconductor device 10 includes: multiple draws
Line 11, the lead for separately including outer lead and extending from outer lead；Semiconductor chip 2 is equipped on multiple leads 11, and is had
There are multiple electrode pads 21；Multiple electrode pads 21 are connect by multiple closing lines 3 with multiple leads 11；And sealing resin layer 4, to more
Lead, semiconductor chip 2 and the multiple closing lines 3 of a lead 11 are sealed.In addition, semiconductor chip 2 can also be equipped on
Mounting surface with semiconductor chip 2 shown in Fig. 7 is the face of multiple leads 11 of opposite side.Moreover, Fig. 5 to shown in Fig. 7 half
Conductor device 10 is TSOP type, but can also have other packaging structures.
The embodiment is to propose as example, but be not intended to limit the range of invention.These novel implementations
Mode can be implemented by other various forms, and various omissions, displacement, change can be carried out in the range of without departing from invention objective.
These embodiments and modifications thereof belong to the range or objective of invention, also belong to the invention recorded in claims and same with it
Deng range.
[explanation of symbol]
1 lead frame
2 semiconductor chips
3 closing lines
4 sealing resin layers
6 organic bonding layers
10 semiconductor devices
11 leads
12 support portions
21 electronic pads
31~35 closing lines
51 platforms
51a groove
52 extruded members
53 biasing members
100 regions
101 regions
111~114 leads
115 wiring portions
116 recesses
211~215 electronic pads
Claims (5)
1. a kind of manufacturing method of semiconductor device, it is characterised in that include the following steps:
1st lead of one face swaged lead frame, will push against component on one side and is pressed against the upper surface of wiring portion and makes the cloth
At least part in line portion deforms, by the end on the extending direction of the 1st lead and the connection between the wiring portion
Portion's cutting, and makes the wiring portion far from the end, which includes the 1st outer lead and outside the described 1st
1st lead of the 1st lead that lead extends draws including the 2nd outer lead and out of the 2nd outer lead extends the 2nd
2nd lead of line and the support portion for being linked to the 1st outer lead and the 2nd outer lead, the 2nd lead include with
The wiring portion of end connection on the extending direction of 1st lead；
It will include the semiconductor-chip-mounting of the 1st electronic pads and the 2nd electronic pads on the lead frame；
Formed the 1st closing line that is electrically connected the 1st electronic pads with the 1st lead and by the 2nd electronic pads with it is described
2nd closing line of the 2nd lead electrical connection；
It is formed to the 1st lead, the 2nd lead, the semiconductor chip, the 1st closing line and the described 2nd
The sealing resin layer that closing line is sealed；And
By the linking part cutting between the support portion and the 1st outer lead and the 2nd outer lead.
2. the manufacturing method of semiconductor device according to claim 1, it is characterised in that:
The biasing member is by the semiconductor-chip-mounting in set on the chip bonding device on the lead frame
An engaging head in multiple engaging heads.
3. according to claim 1 or the manufacturing method of semiconductor device as claimed in claim 2, it is characterised in that:
Linking part between the end and the wiring portion has the width and ratio narrower than the maximum width of the 1st lead
Thin at least one of the thickness of the maximum gauge of 1st lead.
4. a kind of semiconductor device, characterized by comprising:
1st lead includes the 1st outer lead and the 1st lead extended from the 1st outer lead；
2nd lead, comprising the 2nd outer lead and the 2nd lead extended from the 2nd outer lead, the 2nd lead has cloth
Line portion, the wiring portion are arranged in a manner of the end being adjacent on the extending direction of the 1st lead and along comprising institute
State the section including the thickness direction of the 2nd lead and with the end on the extending direction of the 1st lead mutually from side
Formula bending；
Semiconductor chip has the 1st electronic pads and the 2nd electronic pads；
1st lead is electrically connected by the 1st closing line with the 1st electronic pads；
2nd lead is electrically connected by the 2nd closing line with the 2nd electronic pads；And
Sealing resin layer, to the 1st lead, the 2nd lead, the semiconductor chip, the 1st closing line and
2nd closing line is sealed；And
End on the end of the side towards the 1st lead and the extending direction of the 1st lead of the wiring portion
Portion has in the width and the thickness thinner than the maximum gauge of the 1st lead narrower than the maximum width of the 1st lead
At least one.
5. a kind of lead frame, characterized by comprising:
1st lead includes the 1st outer lead and the 1st lead extended from the 1st outer lead；
2nd lead, comprising the 2nd outer lead and the 2nd lead extended from the 2nd outer lead, the 2nd lead has cloth
Line portion, the wiring portion are arranged in a manner of the end being adjacent on the extending direction of the 1st lead and along comprising institute
State the section including the thickness direction of the 2nd lead and with the end on the extending direction of the 1st lead mutually from side
Formula bending；And
Support portion is linked to the 1st outer lead and the 2nd outer lead；And
End on the end of the side towards the 1st lead and the extending direction of the 1st lead of the wiring portion
Portion has in the width and the thickness thinner than the maximum gauge of the 1st lead narrower than the maximum width of the 1st lead
At least one.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015-181479 | 2015-09-15 | ||
| JP2015181479A JP6437406B2 (en) | 2015-09-15 | 2015-09-15 | Semiconductor device manufacturing method, semiconductor device, and lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106531712A CN106531712A (en) | 2017-03-22 |
| CN106531712B true CN106531712B (en) | 2019-04-26 |
Family
ID=58358033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610236159.2A Active CN106531712B (en) | 2015-09-15 | 2016-04-15 | Manufacturing method, semiconductor device and the lead frame of semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP6437406B2 (en) |
| CN (1) | CN106531712B (en) |
| TW (1) | TWI603406B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102017209904B4 (en) * | 2017-06-13 | 2023-09-21 | Infineon Technologies Ag | Electronic component, lead frame for an electronic component and method for producing an electronic component and a lead frame |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3842492A (en) * | 1970-12-17 | 1974-10-22 | Philips Corp | Method of providing conductor leads for a semiconductor body |
| US6917098B1 (en) * | 2003-12-29 | 2005-07-12 | Texas Instruments Incorporated | Three-level leadframe for no-lead packages |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02253648A (en) * | 1989-03-27 | 1990-10-12 | Nec Kyushu Ltd | Lead frame for semiconductor device |
| JPH03160749A (en) * | 1989-11-20 | 1991-07-10 | New Japan Radio Co Ltd | Lead frame and its manufacture |
| JPH08162585A (en) * | 1994-12-06 | 1996-06-21 | Hitachi Constr Mach Co Ltd | Lead frame processing method, lead frame and semiconductor device |
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2015
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- 2016-04-15 CN CN201610236159.2A patent/CN106531712B/en active Active
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Also Published As
| Publication number | Publication date |
|---|---|
| TW201711114A (en) | 2017-03-16 |
| CN106531712A (en) | 2017-03-22 |
| JP2017059614A (en) | 2017-03-23 |
| TWI603406B (en) | 2017-10-21 |
| JP6437406B2 (en) | 2018-12-12 |
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