CN106531712A - Method for manufacturing semiconductor device, semiconductor device and lead frame - Google Patents
Method for manufacturing semiconductor device, semiconductor device and lead frame Download PDFInfo
- Publication number
- CN106531712A CN106531712A CN201610236159.2A CN201610236159A CN106531712A CN 106531712 A CN106531712 A CN 106531712A CN 201610236159 A CN201610236159 A CN 201610236159A CN 106531712 A CN106531712 A CN 106531712A
- Authority
- CN
- China
- Prior art keywords
- lead
- wiring portion
- semiconductor device
- closing line
- trend
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The embodiment of the invention provides a method for manufacturing a semiconductor device capable of suppressing excessive deformation of leads, the semiconductor device and a lead frame. The method includes the steps of extruding a first inner lead while a pressing mechanism abutting against the upper surface of a wiring portion of a second inner lead to make at least the wiring portion to be deformed partially, cutting the connection portion between the end portion and the wiring portion on the extending direction of the first inner lead so separate the wiring portion and the end portion, loading a semiconductor chip, forming a first and second joint wire, forming a sealed resin layer, and cutting off a connection portion between a supporting portion and the first and second leads.
Description
[related application]
Subject application was enjoyed with No. 2015-181479 (applying date of Japanese patent application：On September 15th, 2015) based on Shen
Please case priority.Subject application includes the full content of basic application case by referring to the basic application case.
Technical field
Embodiments of the present invention are related to a kind of manufacture method of semiconductor device, semiconductor device and lead frame.
Background technology
In the semiconductor device with lead and semiconductor chip comprising outer lead and lead, will using closing line
Electrically connect between the electronic pads of semiconductor chip and lead.Therefore, electronic pads is more long then more with the distance between outer lead
Need make lead from outer lead it is longer extend near electronic pads.
Long lead is easily deformed in the manufacture process of semiconductor device.If lead deforms, then can go out
Existing following situation：For example, semiconductor chip is easily peeled off from lead, or closing line is drawn with interior when wire bonding is carried out
There is bad connection between line.
The content of the invention
Embodiments of the present invention provide a kind of manufacture method of the semiconductor device of the unnecessary deformation that can suppress lead, partly lead
Body device and lead frame.
The manufacture method of the semiconductor device of embodiment comprises the steps：1st lead of one face swaged lead framework
Simultaneously will push against component to be pressed against the upper surface of wiring portion and deform at least a portion of wiring portion, by end and wiring portion
Between linking part cut-out and make wiring portion with end from the lead frame includes the 1st outer lead and from outside the 1st
1st lead of the 1st lead that lead extends, the 2nd lead extended including the 2nd outer lead and from the 2nd outer lead
The 2nd lead and be linked to the supporting part of the 1st outer lead and the 2nd outer lead, the 2nd lead comprising with the 1st in draw
The wiring portion that end on the bearing of trend of line links；Semiconductor chip including the 1st electronic pads and the 2nd electronic pads is taken
It is loaded on lead frame；Formation the 1st closing line that the 1st electronic pads is electrically connected with the 1st lead and by the 2nd electronic pads and
2nd closing line of the 2nd lead electrical connection；Formation is connect to the 1st lead, the 2nd lead, semiconductor chip, the 1st
The sealing resin layer sealed by zygonema and the 2nd closing line；And by supporting part and the 1st outer lead and the 2nd outer lead it
Between linking part cut-out.
Description of the drawings
Fig. 1 is the floor map of the structure example for representing lead frame.
Fig. 2 is the enlarged drawing for the part for representing the lead frame shown in Fig. 1.
Fig. 3 is the schematic cross-section for illustrating lead frame procedure of processing.
Fig. 4 is the schematic cross-section for illustrating lead frame procedure of processing.
Fig. 5 is the floor map of the structure example for representing semiconductor device.
Fig. 6 is the enlarged drawing for the part for representing the semiconductor device shown in Fig. 5.
Fig. 7 is the schematic cross-section of the structure example for the part for representing the semiconductor device shown in Fig. 5.
Specific embodiment
Hereinafter, embodiment is illustrated with reference to schema.The thickness and planar dimension of each inscape described in schema
Relation, the ratio of the thickness of each inscape etc. it is different from material object sometimes.And, in embodiment, for essence
Property identical inscape mark same-sign and suitably omit the description.
As manufacturer's rule of semiconductor device, TSOP (Thin Small Outline are directed to referring to figs. 1 to Fig. 7
Packeage：TSOP, thin-type small-size are installed) manufacturer's rule of type semiconductor device illustrates.Semiconductor device
Manufacturer's rule include lead frame preparation process, lead frame procedure of processing, chip carrying step, wire bonding step,
Resin-sealing step, coating step, finishing shaping (T/F) step.The order of each step is not limited to described enumerating sequentially.
Fig. 1 is the floor map of the structure example for representing lead frame.Fig. 1 is represented comprising X-axis and Y orthogonal to X-axis
The X-Y plane of the lead frame of axle.
In lead frame preparation process, as shown in figure 1, preparing with multiple leads 11 and supporting propping up for multiple leads 11
The lead frame 1 of support part 12.Lead frame 1 is the metallic plate for carrying the elements such as semiconductor chip.As lead frame 1,
The lead frame of alloy for example with the iron such as copper, copper alloy or 42 alloys and nickel etc. can be enumerated.Lead frame 1
Processed by punch process etc. in advance.
The each self-contained outer lead of multiple leads 11 and the lead extended from the outer lead.Lead is walked in resin seal
Rapid rear support is in the part of sealing resin layer.Outer lead is the part projected from sealing resin layer after resin-sealing step.
The outer lead of multiple leads 11 is each for example arranged side by side in X-Y plane along Y-axis.
As multiple leads 11, such as input/output signal (IO), data strobe signal (DQS), lead can be enumerated and enabled
Signal (RE), Ready/Busy signal (RB), chip enable signal (CE), address latch enable signal (ALE), write and make
Can the signal lead such as signal (WE), write protect signal (RP) or zero business's signal (ZQ) or power supply (VCC),
Power supply leads such as power supply (VPP), power supply (VSS) etc..As the signal, it is possible to use differential wave.Multiple leads
11 leads also can with not connected (NC).Putting in order for various leads can be according to the specification of semiconductor device or pattern etc.
Setting.
Supporting part 12 is arranged in the way of surrounding multiple leads 11.Supporting part 12 is linked to multiple leads 11 respectively
Outer lead.In addition, supporting part 12 also can support the lead of multiple semiconductor devices.
Fig. 2 is the enlarged drawing for the part (part in region 100) for representing the lead frame shown in Fig. 1.In Fig. 2,
As the lead of multiple leads 11, it is illustrated that lead 111, lead 112, lead 113, lead 114.
Lead 111 and lead 112 are, for example, signal lead.Lead 113 and lead 114 are, for example, power supply
Use lead.Now, lead 113 is provided between lead 111 and lead 112, thus, can suppress lead
Interference between 111 signal and the signal of lead 112.
Lead 114 with the bearing of trend of lead 111 to lead 113 on end link wiring portion 115.
That is, lead 111 to lead 113 is fixed by lead 114 and supporting part 12.As long as the shape of wiring portion 115
Then it is not particularly limited for lead 111 being connected junction configuration to lead 113 with lead 114.
As shown in Fig. 2 the width of the linking part between the end on the bearing of trend of lead 111 and wiring portion 115 is excellent
Choosing is narrower than the Breadth Maximum of lead 111.Again it is preferred to be end on the bearing of trend of lead 112 with
The Breadth Maximum of the width ratio lead 112 of the linking part between wiring portion 115 is narrow.Preferably lead 113 prolongs
The Breadth Maximum for stretching the width ratio lead 113 of linking part between the end on direction and wiring portion 115 is narrow.The company
Knot is alternatively the most narrow region of the width of lead for linking.The width of the linking part for example can be by using compacting
Processing or Laser Processing etc. form recess 116 in the linking part and are adjusted.
Fig. 3 is the schematic cross-section for illustrating to lead frame procedure of processing.Fig. 3 is represented comprising lead frame 1
Y-axis and the Z axis orthogonal with X-axis and Y-axis Y-Z sections.Thickness direction of the Z axis equivalent to lead frame 1.
In Fig. 3, the section comprising lead 113 is illustrated as one.
In lead frame procedure of processing, lead frame 1 is placed on the platform 51 with groove 51a, using crowded
Pressure component 52 is for (inside drawing at the two ends of the linking part between the end on the bearing of trend of lead 113 and wiring portion 115
114) line 113 and lead are extruded.Now, wiring portion 115 is made to be overlapped in groove 51a.
Then, biasing member 53 is declined to 51 side of platform along Z axis, make biasing member 53 compress wiring portion 115
Upper surface and deform at least a portion of wiring portion 115.End and wiring portion on the bearing of trend of lead 113
Linking part between 115 is narrower than the Breadth Maximum of lead 113, so being more easy to cut-out than other regions.Therefore, if
Deform wiring portion 115, then can be by the link between the end on the bearing of trend of lead 113 and wiring portion 115
Portion cut off and can make end on wiring portion 115 and the bearing of trend of lead 113 from.Equally, by lead 111
And the linking part between lead 112 and wiring portion 115 cuts off and makes wiring portion 115 with lead 111 and lead
End on 112 bearing of trend from.
For being switched off the wiring portion after linking part 115, it is configured to adjacent when observing from the direction vertical with X-Y plane
End on the bearing of trend of lead 111 to lead 113.And, it is switched off the wiring portion after linking part 115
For, when observing from the direction vertical with Y-Z sections with along the section of the thickness direction comprising lead 114
And with lead 111 to lead 113 from mode bend.The shape of the wiring portion 115 after deformation has no especially limit
It is fixed, can as shown in figure 3, wiring portion 115 with lead 111 to the parallel region of the bearing of trend of lead 113.
Using above step, make the part of lead 111 a part of separated from one another to lead 114.Equally, still utilize
The step makes a part of separated from one another of other leads for linking.
By lead 111 being made to the narrowed width of the linking part between lead 113 and wiring portion 115, can reduce and cut
Required load when disconnected.Thus, as biasing member 53, can using in chip carrying step carry semiconductor chip when
An engaging head on the chip bonding device for using in set multiple engaging heads.
When being processed to lead frame using punch process, when during punching press, required load is more than the linking part is cut off
Required load.Therefore, in order that cutting off the linking part with for carrying out the processing unit (plant) of punch process, except punching
Outside press mechanism, the dipper crowding gear that can give the load less than punching press need be set.Therefore, the composition of processing unit (plant) becomes
It is complicated.And, if be processed to lead frame using for carrying out the processing unit (plant) of punch process, then when right
Cut-out bits are produced when a part for lead frame carries out punching press easily.The cut-out bits of lead can become the pollution of manufacturing environment
Source, it is preferred that cut-out bits are less.
When being processed to lead frame using punch process, lead frame is transported to chip bonding device after processing
And semiconductor chip is carried, so lead easily deforms during conveyance.Therefore, need arrange to multiple leads
The fixing band being fixed.Fixing band easily absorbs moisture, therefore easily peels off from lead.And, if having fixed
Band, then lead frame can be substantive thickening.Therefore, the lead frame quantity that can be contained in accepting box is reduced, therefore,
Conveying cost increase.And, fixing band easily causes the migration of ingotism shape.If causing migration, then sometimes
Short circuit between lead etc. can be caused.
In this regard, when the linking part is cut off using chip bonding device and make the part separation of each lead, in lead
Semiconductor chip can be carried using identical chip bonding device after framework procedure of processing.Accordingly, it is capable to reduce lead frame
Conveyance.Thus, even if being not provided with fixing band, can also suppress lead that unnecessary deformation occurs.And, the material of fixing band
Take and processing charges are cut down, so as to cut down manufacturing cost.In addition, wiring portion can be retained and make a part point for each lead
From, therefore, the cut-out bits of lead compared with punch process, can be reduced.
The shape of the linking part between end and wiring portion 115 on the bearing of trend of lead 111 to lead 113 is simultaneously
The shape being not limited to shown in Fig. 2.Fig. 4 is for showing to the section that other examples of lead frame procedure of processing are illustrated
It is intended to.Fig. 4 and Fig. 3 equally represents the Y-Z sections of lead frame 1.
As shown in figure 4, the thickness of the linking part between the end on the bearing of trend of lead 113 and wiring portion 115
It is thin than the maximum gauge of lead 113.Equally, the end on the bearing of trend of lead 111 and wiring portion 115 it
Between linking part thickness it is also thin than the maximum gauge of lead 111.End on the bearing of trend of lead 112 with
The thickness of the linking part between wiring portion 115 is also thin than the maximum gauge of lead 112.The thickness of the linking part can
Form recessed by, for example, impressing processing, Laser Processing or scraper processing etc. along the depth direction of the linking part
Mouthfuls 116 and be adjusted.The linking part is alternatively the most thin region on the lead for linking.The linking part
At least one of width and thickness are adjusted as mentioned above.
As shown in figure 4, when the thickness of the linking part between the end on the bearing of trend of lead 113 and wiring portion 115
When thinner than the maximum gauge of lead 113, the linking part is easily cut off than other regions.Accordingly, it is capable to by lead
Linking part cut-out between end on 113 bearing of trend and wiring portion 115, and wiring portion 115 and lead can be made
End on 113 bearing of trend from.Equally, can be by the end on the bearing of trend of lead 111 and wiring portion 115
Between linking part and lead 112 bearing of trend on end and wiring portion 115 between linking part cut-out.
Fig. 5 is that the plane of the structure example for representing the semiconductor device that the manufacture method of semiconductor device can be used to manufacture is illustrated
Figure.Fig. 5 represents the X-Y plane of semiconductor device.Fig. 6 is a part (area for representing the semiconductor device shown in Fig. 5
The part in domain 101) enlarged drawing.Fig. 7 is a part (part in region 101) for the semiconductor device shown in Fig. 5
Schematic cross-section.The section comprising lead 113 is represented in Fig. 7 as one.In addition, Fig. 5 and Fig. 6
In, for convenience, illustrated through the inside of sealing resin layer 4.It is appropriate for the part common with Fig. 1 to Fig. 4
Continue to use the explanation of Fig. 1 to Fig. 4.
In chip carrying step, semiconductor chip 2 is equipped on into lead 111 to the multiple leads such as lead 114 11
Lead on.As shown in fig. 6, semiconductor chip 2 has the multiple electrodes comprising electronic pads 211 to electronic pads 215
Pad 21.Multiple electrodes pad 21 is exposed to the surface of semiconductor chip 2.Multiple electrodes pad 21 also can be along semiconductor chip
2 one side and set.By multiple electrodes pad 21 being arranged along one side of semiconductor chip 2, can reduce chip size.Make
For semiconductor chip 2, the semiconductor that can be enumerated used in the memory elements such as such as NAND-type flash memory or storage control etc.
Chip.
As semiconductor chip 2, can be using for example when by the end on the bearing of trend of lead 111 to lead 113
The chip bonding device that uses when cutting off with the linking part between wiring portion 115 and carried.For example, semiconductor chip
2 are equipped on lead 111 and draw to interior using another engaging head being different from multiple engaging heads of biasing member 53
On line 114.Semiconductor chip 2 can be equipped on lead 111 via the organic bonding such as bonding die film with insulating properties layer 6
To the lead of the multiple leads such as lead 114 11.Now, the lead of multiple leads 11 is adhered to organic bonding
Layer 6.Thus, the lead of multiple leads 11 is fixed, so lead occurs unnecessary change in the step of suppressing hereafter
Shape.
Lead 111 is preferably being cut by semiconductor chip 2 to the linking part between lead 113 and wiring portion 115
Carry after disconnected.If cutting off the linking part after semiconductor chip is carried, then damage semiconductor chip sometimes.
In online engagement step, multiple closing lines 3 that multiple electrodes pad 21 is electrically connected with multiple leads 11 are formed.Figure
In 6, it is illustrated that the closing line 31 that electrically connects lead 111 with electronic pads 211, by lead 112 and electronic pads 212
The closing line 32 of electrical connection, the closing line 33 that lead 113 is electrically connected with electronic pads 213, by lead 114 with
The closing line 34 of the electrical connection of electronic pads 214, and closing line 35 that lead 114 is electrically connected with electronic pads 215.
As closing line 3, such as gold thread, silver wire, copper cash etc. can be enumerated.The surface of copper cash can also cover palladium film.Engagement
Line 3 is electrically connected to lead and electronic pads using wire bonding.
In resin-sealing step, form the lead to lead 111 to the multiple leads such as lead 114 11, partly lead
Body chip 2, and the sealing resin layer 4 that sealed to the multiple closing lines such as closing line 35 3 of closing line 31.Sealing tree
Lipid layer 4 is arranged in the way of covering the upper surface of the lead of multiple leads and lower surface.And, as shown in fig. 7,
Sealing resin layer 4 is also filled between the end on the bearing of trend of lead 111 to lead 113 and wiring portion 115.
Sealing resin layer 4 contains SiO2Deng inorganic fill material.And, as inorganic fill material, except SiO2Outside,
Such as aluminium hydroxide, calcium carbonate, aluminum oxide, boron nitride, titanium oxide or barium titanate etc. can also be included.Inorganic fill
Material is for example, granular, and the function of the viscosity with adjustment sealing resin layer 4 or hardness etc..Nothing in sealing resin layer 4
The content of machine filling material is, for example, less than more than 60% 90%.As sealing resin layer 4, such as inorganic fill material can be used
With the mixture of insulating properties organic resin material.As organic resin material, such as epoxy resin can be enumerated.
As the formation method of sealing resin layer 4, can enumerate for example use inorganic fill material and organic resin etc. it is mixture,
Transfer moudling, compression molding, injection molding, sheet molding method or resin distribution method etc..
In coating step, plating processing is implemented to the surface of multiple leads 11.Can for example using the welding material of stanniferous grade
Material carries out the plating processing such as electroplating.By implementing plating processing, can for example suppress the oxidation of multiple leads 11.
Finishing shaping (T/F) step includes for the linking part cut-out between multiple leads 11 and supporting part 12 cutting semiconductor
The step of device 10 (pre-shaping step), and make multiple leads 11 outer lead conjunction with semiconductors device 10 net shape and
The step of deformation (forming step).
Semiconductor device 10 can be manufactured by above step.As shown in Figures 5 to 7, semiconductor device 10 includes：It is many
Individual lead 11, the lead for extending comprising outer lead and from outer lead respectively；Semiconductor chip 2, is equipped on multiple leads
On 11, and there is multiple electrodes pad 21；Multiple closing lines 3, multiple electrodes pad 21 is connected with multiple leads 11；And
Sealing resin layer 4, the lead to multiple leads 11, semiconductor chip 2, and multiple closing lines 3 seal.Separately
Outward, semiconductor chip 2 can also be equipped on the multiple leads with the mounting surface of the semiconductor chip 2 shown in Fig. 7 for opposition side
11 face.And, the semiconductor device 10 shown in Fig. 5 to Fig. 7 is TSOP types, but can also have other encapsulation structures
Make.
The embodiment is to propose as an example, but is not intended to limit the scope of invention.These novel embodiment party
Formula can be implemented by other various forms, and can carry out various omissions, displacement, change in the range of without departing from invention objective.
These embodiments and its deformation belong to the scope or objective of invention, fall within invention described in claims and and its
Equal scope.
[explanation of symbol]
1 lead frame
2 semiconductor chips
3 closing lines
4 sealing resin layers
6 organic bonding layers
10 semiconductor devices
11 leads
12 supporting parts
21 electronic padses
31～35 closing lines
51 platforms
51a grooves
52 extruded members
53 biasing members
100 regions
101 regions
111～114 leads
115 wiring portions
116 recesses
211～215 electronic padses
Claims (5)
1. a kind of manufacture method of semiconductor device, it is characterised in that comprise the steps：
1st lead of one face swaged lead framework, simultaneously will push against the upper surface that component is pressed against the wiring portion
And deform at least a portion of the wiring portion, the linking part between the end and the wiring portion is cut off,
And the wiring portion is made away from the end, the lead frame includes the 1st outer lead and from outside the described 1st
Lead extend the 1st lead the 1st lead, including the 2nd outer lead and from the 2nd outer lead extend
The 2nd lead the 2nd lead and be linked to the supporting part of the 1st outer lead and the 2nd outer lead,
2nd lead comprising with the bearing of trend of the 1st lead on end link wiring portion；
By the semiconductor-chip-mounting including the 1st electronic pads and the 2nd electronic pads on the lead frame；
Formation the 1st closing line that the 1st electronic pads is electrically connected with the 1st lead and electric by the described 2nd
The 2nd closing line that polar cushion is electrically connected with the 2nd lead；
Formed to the 1st lead, the 2nd lead, the semiconductor chip, the 1st closing line,
And the sealing resin layer sealed by the 2nd closing line；And
Linking part between the supporting part and the 1st outer lead and the 2nd outer lead is cut off.
2. the manufacture method of semiconductor device according to claim 1, it is characterised in that：
The biasing member be by the semiconductor-chip-mounting on the chip bonding device on the lead frame
An engaging head in set multiple engaging heads.
3. the manufacture method of the semiconductor device according to claim 1 or claim 2, it is characterised in that：
Linking part between the end and the wiring portion is with narrower than the Breadth Maximum of the 1st lead
At least one of width and the thickness thinner than the maximum gauge of the 1st lead.
4. a kind of semiconductor device, it is characterised in that include：
1st lead, the 1st lead extended comprising the 1st outer lead and from the 1st outer lead；
2nd lead, the 2nd lead extended comprising the 2nd outer lead and from the 2nd outer lead, the described 2nd
Lead has wiring portion, and the wiring portion is with the side of the end being adjacent on the bearing of trend of the 1st lead
Formula arrange and along comprising the 2nd lead thickness direction section and with the 1st lead
End on bearing of trend from mode bend；
Semiconductor chip, with the 1st electronic pads and the 2nd electronic pads；
1st closing line, the 1st lead is electrically connected with the 1st electronic pads；
2nd closing line, the 2nd lead is electrically connected with the 2nd electronic pads；And
Sealing resin layer, to the 1st lead, the 2nd lead, the semiconductor chip, described
1 closing line and the 2nd closing line are sealed.
5. a kind of lead frame, it is characterised in that include：
1st lead, the 1st lead extended comprising the 1st outer lead and from the 1st outer lead；
2nd lead, the 2nd lead extended comprising the 2nd outer lead and from the 2nd outer lead, the described 2nd
Lead has wiring portion, and the wiring portion is with the side of the end being adjacent on the bearing of trend of the 1st lead
Formula arrange and along comprising the 2nd lead thickness direction section and with the 1st lead
End on bearing of trend from mode bend；And
Supporting part, is linked to the 1st outer lead and the 2nd outer lead.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015-181479 | 2015-09-15 | ||
| JP2015181479A JP6437406B2 (en) | 2015-09-15 | 2015-09-15 | Semiconductor device manufacturing method, semiconductor device, and lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106531712A true CN106531712A (en) | 2017-03-22 |
| CN106531712B CN106531712B (en) | 2019-04-26 |
Family
ID=58358033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610236159.2A Active CN106531712B (en) | 2015-09-15 | 2016-04-15 | Manufacturing method, semiconductor device and the lead frame of semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP6437406B2 (en) |
| CN (1) | CN106531712B (en) |
| TW (1) | TWI603406B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109087903A (en) * | 2017-06-13 | 2018-12-25 | 英飞凌科技股份有限公司 | The method of electronic device, the lead frame for electronic device and manufacture electronic device and lead frame |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109087903A (en) * | 2017-06-13 | 2018-12-25 | 英飞凌科技股份有限公司 | The method of electronic device, the lead frame for electronic device and manufacture electronic device and lead frame |
| CN109087903B (en) * | 2017-06-13 | 2022-11-08 | 英飞凌科技股份有限公司 | Electronic device, lead frame for electronic device, and method of manufacturing electronic device and lead frame |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106531712B (en) | 2019-04-26 |
| TW201711114A (en) | 2017-03-16 |
| JP2017059614A (en) | 2017-03-23 |
| TWI603406B (en) | 2017-10-21 |
| JP6437406B2 (en) | 2018-12-12 |
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