CN104112673A - Chip packaging base board and manufacturing method thereof - Google Patents
Chip packaging base board and manufacturing method thereof Download PDFInfo
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- CN104112673A CN104112673A CN201310137349.5A CN201310137349A CN104112673A CN 104112673 A CN104112673 A CN 104112673A CN 201310137349 A CN201310137349 A CN 201310137349A CN 104112673 A CN104112673 A CN 104112673A
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- conducting wire
- wire layer
- glass
- substrate
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 14
- 239000011521 glass Substances 0.000 claims abstract description 98
- 239000000758 substrate Substances 0.000 claims description 78
- 238000000034 method Methods 0.000 claims description 32
- 238000003466 welding Methods 0.000 claims description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 16
- 238000009713 electroplating Methods 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 239000006071 cream Substances 0.000 claims description 2
- 239000003292 glue Substances 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract 3
- 229910000679 solder Inorganic materials 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 239000000945 filler Substances 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
Abstract
The invention relates to a chip packaging base board. The chip packaging base board comprises a circuit board core board, a first glue layer, a first glass base and a third conductive line layer, wherein the circuit board core board comprises an insulation base, and a first conductive line layer and a second conductive line layer which are arranged at two opposite sides of the insulation base, the first conductive line layer comprises multiple first electrical connection pads, the second conductive line layer comprises multiple second electrical connection pads, the first glue layer is formed on a surface of the first conductive line layer, the insulation base is exposed out of the surface of the first conductive line layer, the first glass base is pasted on the first glue layer, the third conductive line layer is formed on a surface of the first glass base and is electrically connected with the multiple first electrical connection pads through multiple first blind guide holes formed on the first glass base and the first glue layer. The invention further relates to a manufacturing method for the chip packaging base board.
Description
Technical field
The present invention relates to circuit board making field, relate in particular to a kind of chip package base plate and preparation method thereof.
Background technology
Chip package base plate can be chip the effects such as electrical connection, protection, support, heat radiation, assembling is provided, and to realize many pinizations, dwindles encapsulating products volume, improves the object of electrical property and thermal diffusivity, super-high density or multi-chip module.
Existing chip package base plate comprises one or more layers dielectric base and is formed at this dielectric base one side or the conducting wire layer of relative both sides.Growing along with chip technology, the line pitch in chip is more and more thinner, the spacing of the conducting wire in the chip package base plate of carries chips is also required more and more thinner, causes the manufacture difficulty of chip package base plate increasing, and manufacturing cost increases.Under the high-density packages demand of chip, industry also has the glass material of employing as dielectric base, adopts glass material to do the ultra fine-line requirement that dielectric base can be accomplished conducting wire layer.Yet the dielectric base of chip package base plate is generally all very thin, when glass material is made to very thin dielectric base, glass material is very easily cracked, causes the manufacture difficulty of chip package base plate large, makes yield low.
Summary of the invention
Therefore, be necessary to provide a kind of easy and chip package base plate that yield is high and preparation method thereof made.
A kind of manufacture method of chip package base plate, comprise step: provide circuit board central layer, comprise dielectric base and form the first conducting wire layer and the second conducting wire layer of these relative both sides of dielectric base, this the first conducting wire layer comprises a plurality of the first electric connection pads, and this second conducting wire layer comprises a plurality of the second electric connection pads; The surface that is exposed to this first conducting wire layer in this first conducting wire layer and this dielectric base arranges the first glue-line, and just the first substrate of glass is adhered on this first glue-line; And form the 3rd conducting wire layer at this first glass basic surface, and form a plurality of the first guide holes of running through this first substrate of glass and the first glue-line, the one end in the plurality of the first guide hole is electrically connected on the 3rd conducting wire layer, the relative other end is electrically connected on respectively the plurality of the first electric connection pad, thereby forms chip package base plate.
A chip package base plate, comprises circuit board central layer, the first glue-line, the first substrate of glass and the 3rd conducting wire layer.This circuit board central layer comprises dielectric base and forms the first conducting wire layer and the second conducting wire layer of these relative both sides of dielectric base, this the first conducting wire layer comprises a plurality of the first electric connection pads, and this second conducting wire layer comprises a plurality of the second electric connection pads.This first glue-line is formed at this layer surface, the first conducting wire and this dielectric base is exposed on the surface of this first conducting wire layer, this first substrate of glass is adhered on this first glue-line, the 3rd conducting wire layer is formed at this first glass basic surface, and is electrically connected to respectively with the plurality of the first electric connection pad by being formed at a plurality of first guide holes of this first substrate of glass and the first glue-line.
In the present embodiment, while forming the first blind hole in the first substrate of glass, this first substrate of glass is supported by circuit board central layer, thereby prevents that the first substrate of glass from adding the cracked of man-hour, the making of chip package base plate is become easily, and improved the making yield of chip package base plate.In addition, in substrate of glass, can make ultra fine-line and line pitch also can do very carefully, therefore can reduce the number of plies of conducting wire layer of whole chip package base plate to reduce the thickness of chip package base plate, and make this first substrate of glass can be electrically connected to the semiconductor package part with high-density spot, thereby make the applicability of chip package base plate wider.
Accompanying drawing explanation
Fig. 1 is the circuit board central layer that provides of the embodiment of the present invention and the vertical view of substrate of glass.
Fig. 2 is the enlarged drawing of the II part of the central layer of circuit board shown in Fig. 1 and substrate of glass.
Fig. 3 is the circuit board central layer of Fig. 2 and the cutaway view of substrate of glass.
Fig. 4 forms the cutaway view after blind hole in the substrate of glass of Fig. 3.
Fig. 5 forms conducting wire layer and in blind hole, forms the cutaway view behind guide hole in the substrate of glass of Fig. 4.
Fig. 6 is the cutaway view increasing on the circuit board of Fig. 5 after layer.
Fig. 7 forms the cutaway view of the chip package base plate forming after welding resisting layer in the circuit board both sides of Fig. 6.
Fig. 8 arranges the cutaway view after chip on the chip package base plate of Fig. 7.
Fig. 9 encapsulates the chip of Fig. 8 the cutaway view of the chip-packaging structure of rear formation.
Figure 10 is another execution mode of the annexation of circuit board central layer in Fig. 3 and substrate of glass.
Main element symbol description
| Circuit board central layer | 10 |
| Dielectric base | 101 |
| The first substrate of glass | 20 |
| The second substrate of glass | 22 |
| The first conducting wire layer | 102 |
| The second conducting wire layer | 103 |
| First surface | 104 |
| Second surface | 105 |
| Central layer unit | 106 |
| The first electric connection pad | 107 |
| The second electric connection pad | 108 |
| The first glue-line | 30 |
| The second glue-line | 32 |
| The first blind hole | 24 |
| The second blind hole | 26 |
| The 3rd conducting wire layer | 44 |
| The 4th conducting wire layer | 46 |
| The first guide hole | 242 |
| The second guide hole | 262 |
| The 3rd electric connection pad | 442 |
| The 4th electric connection pad | 462 |
| The first dielectric layer | 50 |
| The 5th conducting wire layer | 52 |
| The second dielectric layer | 60 |
| The 6th conducting wire layer | 62 |
| The 3rd guide hole | 522 |
| The 4th guide hole | 622 |
| The 5th electric connection pad | 524 |
| The 6th electric connection pad | 624 |
| The first welding resisting layer | 70 |
| The second welding resisting layer | 72 |
| Surface-treated layer | 74 |
| Chip package base plate | 100 |
| Chip | 80 |
| Chip-packaging structure | 200 |
| Chip body | 82 |
| Solder projection | 84 |
| Soldered ball | 526，528 |
| Bottom filler | 530 |
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Refer to Fig. 1 to 9, the embodiment of the present invention provides a kind of manufacture method of chip-packaging structure, comprises the steps:
The first step, refer to Fig. 1 to Fig. 3, circuit board central layer 10 is provided, the first glue-line 30 and the second glue-line 32 are set respectively in the relative both sides of this circuit board central layer 10, and just a plurality of the first substrate of glass 20 are adhered on this first glue-line 30, a plurality of the second substrate of glass 22 are adhered on this second glue-line 32.
This circuit board central layer 10 comprises dielectric base 101 and is arranged at the first conducting wire layer 102 and the second conducting wire layer 103 of these dielectric base 101 relative both sides, this dielectric base 101 comprises relative first surface 104 and second surface 105, this the first conducting wire layer 102 and the second conducting wire layer 103 are formed at respectively this first surface 104 and second surface 105, and this first conducting wire layer 102 is electrically connected to by connecting the via (not shown) realization of this first conducting wire layer 102, dielectric base 101 and the second conducting wire layer 103 with the second conducting wire layer 103.In the present embodiment, this circuit board central layer 10 comprises a plurality of central layers unit 106 that array is arranged, and is used to form the chip package base plate of a plurality of same structures, and Fig. 1 and Fig. 2 separate with dotted line, and the quantity of the central layer unit 106 in actual production is not as limit.The structure of the conducting wire of the first conducting wire layer 102 in the plurality of central layer unit 106 is identical, and the second conducting wire layer 103 in the plurality of central layer unit 106 is identical.The first conducting wire layer 102 in each central layer unit 106 includes a plurality of the first electric connection pads 107, and the second conducting wire layer 103 in each central layer unit 106 includes a plurality of the second electric connection pads 108.
The first surface 104 that this first glue-line 30 covers this first conducting wire layer 102 and is exposed to this first conducting wire layer 102, the second surface 105 that this second glue-line 32 covers this second conducting wire layer 103 and is exposed to this second conducting wire layer 103, the plurality of the first substrate of glass 20 is adhered to respectively on this first glue-line 30 and the second glue-line 32 with a plurality of the second substrate of glass 22, and the relative both sides of each central layer unit 106 are respectively arranged with the first substrate of glass 20 and the second substrate of glass 22.This first glue-line 30 and the second glue-line 32 can be pure glue.In the present embodiment, the plurality of the first substrate of glass 20 is bonding and protruding in the surface of the first glue-line 30 respectively, and the plurality of the second substrate of glass 22 is bonding and protruding in the surface of the second glue-line 32 respectively.Be appreciated that as shown in figure 10, the plurality of the first substrate of glass 20 also can embed respectively in the first glue-line 30, and the plurality of the second substrate of glass 22 also can embed respectively in the second glue-line 32, with the present embodiment, is not limited.
For ease of explanation, the present embodiment starts to form to cutting a plurality of steps of separated a plurality of chip package base plates unit from the first step, for the processing procedure of the plurality of central layer unit 106 and corresponding a plurality of the first substrate of glass 20 and the second substrate of glass 22, be simultaneously and carry out.The present embodiment, for ease of explanation, forms the step of separated a plurality of chip package base plates unit from second step to cutting, all take and describes as example for one of them central layer unit 106 and the first substrate of glass 20 of correspondence thereof and the processing procedure of the second substrate of glass 22.
Second step, refer to Fig. 4, from these the first substrate of glass 20 sides, form a plurality of the first blind holes 24 that run through this first substrate of glass 20 and the first glue-line 30 and expose respectively the plurality of the first electric connection pad 107, in these the second substrate of glass 22 sides, form a plurality of the second blind holes 26 that run through this second substrate of glass 22 and the second glue-line 32 and expose respectively the plurality of the second electric connection pad 108.This first blind hole 24 and the second blind hole 26 can through hole laser pit method make and form.
The 3rd step, refer to Fig. 5, on this first substrate of glass 20 and the second substrate of glass 22 surfaces, make respectively and form the 3rd conducting wire layer 44 and the 4th conducting wire layer 46, and be electrically connected to the first guide hole 242 of this first conducting wire layer 102 and the 3rd conducting wire layer 44 and be electrically connected to the second guide hole 262 of this second conducting wire layer 103 and the 4th conducting wire layer 46 in this first blind hole 24 and the interior formation of the second blind hole 26.The 3rd conducting wire layer 44 comprises that a plurality of the 3rd electric connection pad 442, the four conducting wire layers 46 comprise a plurality of the 4th electric connection pads 462.
The 3rd conducting wire layer 44 and the first guide hole 242 can be adopted with the following method and be made and form: surface and this first substrate of glass 20 surfaces at the inwall of the plurality of the first blind hole 24, the plurality of the first electric connection pad 107 form continuous Seed Layer; The photoresist layer that forms patterning on these the first substrate of glass 20 surfaces, this photoresist layer exposes the plurality of the first blind hole 24; By electric plating method, on the surface that is exposed to the Seed Layer of this photoresist layer, form copper electroplating layer; And remove this photoresist layer, and remove the part that this Seed Layer is covered by this photoresist layer, the Seed Layer and the copper electroplating layer that remain in these the first substrate of glass 20 surfaces form the 3rd conducting wire layer 44, and the Seed Layer in the plurality of the first blind hole 24 and copper electroplating layer form the plurality of the first guide hole 242.This Seed Layer is by electroless copper or spatters the thin copper layer that copper coating forms.
Certainly, the 3rd conducting wire layer 44 and the first guide hole 242 can also be adopted with the following method and be made and form: at the interior filled conductive cream of the plurality of the first blind hole 24; On these the first substrate of glass 20 surfaces, form continuous Seed Layer; The photoresist layer that forms patterning on these the first substrate of glass 20 surfaces, the Seed Layer relative with the plurality of the first blind hole 24 is exposed to this photoresist layer; By electric plating method, on the surface that is exposed to the Seed Layer of this photoresist layer, form copper electroplating layer; And remove this photoresist layer, and remove the part that this Seed Layer is covered by this photoresist layer, the Seed Layer and the copper electroplating layer that remain in these the first substrate of glass 20 surfaces form the 3rd conducting wire layer 44, and the interior conductive paste of the plurality of the first blind hole 24 forms the plurality of the first guide hole 242.This Seed Layer is by electroless copper or spatters the thin copper layer that copper coating forms.
The manufacture method in the 4th conducting wire layer 46 and the second guide hole 262 is identical with the manufacture method in the 3rd conducting wire layer 44 and the first guide hole 242.
The 4th step, refer to Fig. 6, in the 3rd conducting wire layer 44 side, form successively the first dielectric layer 50 and the 5th conducting wire layer 52, in the 4th conducting wire layer 46 side, form successively the second dielectric layer 60 and the 6th conducting wire layer 62, and a plurality of the 4th guide holes 622 that form a plurality of the 3rd guide holes 522 of electrical connection the 3rd conducting wire layer 44 and the 5th conducting wire layer 52 and be electrically connected to the 4th conducting wire layer 46 and the 6th conducting wire layer 62.The 5th conducting wire layer 52 comprises that a plurality of the 5th electric connection pad 524, the six conducting wire layers 62 comprise a plurality of the 6th electric connection pads 624.
This first dielectric layer 50 and the second dielectric layer 60 can be solidify to form by the pressing of semi-solid preparation film, and this semi-solid preparation film can be epoxy resin.The manufacture method in the 5th conducting wire layer 52 and the 3rd guide hole 522 and the 6th conducting wire layer 62 and the 4th guide hole 622 and the manufacture method in the 3rd conducting wire layer 44 and the first guide hole 242 are similar.The one end in the plurality of the 3rd guide hole 522 is electrically connected to the 5th conducting wire layer 52, the relative other end is electrically connected to respectively the plurality of the 3rd electric connection pad 442, the one end in the plurality of the 4th guide hole 622 is electrically connected to the 6th conducting wire layer 62, and the relative other end is electrically connected to respectively the plurality of the 4th electric connection pad 462.
The 5th step, refer to Fig. 7, in the 5th conducting wire layer 52 side, form the first welding resisting layer 70, in the 6th conducting wire layer 62 side, form the second welding resisting layer 72, and form surface-treated layer 74 at the 5th electric connection pad 524 and the 6th electric connection pad 624 surfaces, form chip package base plate bar (not indicating).
This first welding resisting layer 70 covers the first dielectric layer 50 surfaces and part the 5th conducting wire layer 52 that is exposed to the 5th conducting wire layer 52, the plurality of the 5th electric connection pad 524 is exposed to this first welding resisting layer 70, this second welding resisting layer 72 covers the second dielectric layer 60 surfaces and part the 6th conducting wire layer 62 that is exposed to the 6th conducting wire layer 62, and the plurality of the 6th electric connection pad 624 is exposed to this second welding resisting layer 72.The plurality of the 5th electric connection pad 524 is for being electrically connected to chip to be packaged, and the plurality of the 6th electric connection pad 624 is for being electrically connected to as base plate for packaging or circuit board with other electronic device.
In the present embodiment, the mode that forms this surface-treated layer 74 is electrogilding.Be appreciated that the method that forms this surface-treated layer 74 also can be substituted by plating nickel gold, change nickel and soak gold, nickel plating porpezite, zinc-plated etc., with the present embodiment, be not limited, certainly, this surface-treated layer 74 also can omit.
In the first step to the of the present embodiment five steps, a plurality of central layers unit 106 links together and processes, and therefore, after the 5th step, formed chip package base plate bar comprises a plurality of array chip base plate for packaging unit.
The 6th step, cuts a plurality of chip package base plate bars that link together, and forms the chip package base plate 100 that a plurality of structures are identical.Cutting method can adopt laser cutting, machine cuts or the method such as die-cut.
Refer to Fig. 7, the chip package base plate 100 of the present embodiment comprises circuit board central layer 10, along this circuit board central layer 10 the first glue-line 30, the first substrate of glass 20, the 3rd conducting wire layer 44, the first dielectric layer 50, the 5th conducting wire layer 52 and the first welding resisting layer 70 that wherein a side is cascading, and the second glue-line 32, the second substrate of glass 22, the 4th conducting wire layer 46, the second dielectric layer 60, the 6th conducting wire layer 62 and the second welding resisting layer 72 that along the relative opposite side of this circuit board central layer 10, are cascading.This circuit board central layer 10 comprises dielectric base 101 and is arranged at the first conducting wire layer 102 and the second conducting wire layer 103 of these dielectric base 101 relative both sides, and this first conducting wire layer 102 and the second conducting wire layer 103 are realized and being electrically connected to by connecting the via of this first conducting wire layer 102, dielectric base 101 and the second conducting wire layer 103.The first surface 104 that this first glue-line 30 covers this first conducting wire layer 102 and is exposed to this first conducting wire layer 102, the second surface 105 that this second glue-line 32 covers this second conducting wire layer 103 and is exposed to this second conducting wire layer 103, this first substrate of glass 20 and the second substrate of glass 22 are adhered to respectively on this first glue-line 30 and the second glue-line 32, the 3rd conducting wire layer 44 and the 4th conducting wire layer 46 are formed at respectively this first substrate of glass 20 and the second substrate of glass 22 away from the surface of this circuit board central layer 10, the 3rd conducting wire layer 44 is electrically connected on this first conducting wire layer 102 by being formed at the first guide hole 242 of this first substrate of glass 20, the 4th conducting wire layer 46 is electrically connected on this second conducting wire layer 103 by being formed at the second guide hole 262 of this second substrate of glass 22.The 5th conducting wire layer 52 is electrically connected on the 3rd conducting wire layer 44, the six conducting wire layer 62 by the 3rd guide hole 522 and is electrically connected on the 4th conducting wire layer 46 by the 4th guide hole 622.This first welding resisting layer 70 covers the first dielectric layer 50 surfaces and part the 5th conducting wire layer 52 that is exposed to the 5th conducting wire layer 52, and the plurality of the 5th electric connection pad 524 is exposed to this first welding resisting layer 70; This second welding resisting layer 72 covers the second dielectric layer 60 surfaces and part the 6th conducting wire layer 62 that is exposed to the 6th conducting wire layer 62, and the plurality of the 6th electric connection pad 624 is exposed to this second welding resisting layer 72.
The 7th step, refers to Fig. 8 and Fig. 9, and chip 80 is provided, and by chip package in this chip package base plate 100, form chip-packaging structure 200.
The present embodiment be take chip package and is illustrated as example, this chip 80 comprises chip body 82 and a plurality of and the 5th electric connection pad 524 solder projection 84 one to one, this solder projection 84 is electrically connected to the internal wiring of this chip body 82, and the step that this chip 80 is packaged in this chip package base plate 100 is as follows:
First, on surface-treated layer 74 surfaces of the plurality of the 5th electric connection pad 524 correspondences, form respectively soldered ball 526, the general main tin that comprises of material of the plurality of soldered ball 526.
Secondly, chip 80 is arranged on chip package base plate 100, and the plurality of solder projection 84 is contacted with corresponding soldered ball 526 respectively.
Further, by this chip 80 together with chip package base plate 100 through Overwelding and rewelding furnace, make cooling curing after solder projection 84 and soldered ball 526 adhere, thereby make a plurality of solder projections 84 interconnect and conduct with corresponding soldered ball 526 respectively.As shown in Figure 9, after this solder projection 84 and soldered ball 526 adhere, form larger soldered ball 528.
Finally, bottom filler 530 is filled in the gap between this chip 80 and chip package base plate 100, thus this chip 80 is fixing with chip package base plate 100 encapsulation.The surface of bottom filler 530 bonding chips 80 and the surface of the first welding resisting layer 70, and surround by the soldered ball 528 forming after solder projection 84 and soldered ball 526 adhere, thereby chip-packaging structure 200 formed.The general epoxy resin that adopts of this bottom filler 530, as bottom filler material Loctite 3536.
The present embodiment, each chip package base plate 100 is respectively used to encapsulate a packaged chip 80, thereby forms a plurality of chip-packaging structures 200.Be appreciated that, the step that chip 80 is packaged in chip package base plate 100 also can be after the 5th step, before the 6th step, a plurality of chips 80 are packaged in after a plurality of chip package base plates 100, then carry out the cutting step of the 6th step, obtain a plurality of chip-packaging structures 200.
Be understandable that, this first dielectric layer 50 and the 5th conducting wire layer 52 also can omit, and the first welding resisting layer 70 is formed to this first substrate of glass 20 surface and part the 3rd conducting wire layer 44 surfaces, chip 80 is directly electrically connected on to the 3rd conducting wire layer 44; Certainly, this second dielectric layer 60 and the 6th conducting wire layer 62 also can omit, and the second welding resisting layer 72 is formed to this second substrate of glass 22 surface and part the 4th conducting wire layer 46 surfaces.Be appreciated that equally all continuing to increase layer between the 5th conducting wire layer 52 and the first welding resisting layer 70 and between the 6th conducting wire layer 62 and the second welding resisting layer 72, to form the chip package base plate with more multi-layered conducting wire layer.
With respect to prior art, in the present embodiment, when forming the first blind hole 24 and forming the second blind hole 26 in the first substrate of glass 20 in the second substrate of glass 22, this first substrate of glass 20 and the second substrate of glass 22 are all supported by circuit board central layer 10, thereby prevent that the first substrate of glass 20 and the second substrate of glass 22 from adding the cracked of man-hour, the making of chip package base plate 100 is become easily, and improved the making yield of chip package base plate 100.In addition, in substrate of glass, can make ultra fine-line and line pitch also can do very carefully, therefore can reduce the number of plies of conducting wire layer of whole chip package base plate 100 to reduce the thickness of chip package base plate 100, and make this first substrate of glass 20 and the second substrate of glass 22 can be electrically connected to the semiconductor package part with high-density spot, thereby make the applicability of chip package base plate 100 wider.
Be understandable that, for the person of ordinary skill of the art, can make other various corresponding changes and distortion by technical conceive according to the present invention, and all these change and distortion all should belong to the protection range of the claims in the present invention.
Claims (10)
1. a manufacture method for chip package base plate, comprises step:
Circuit board central layer is provided, comprise dielectric base and form the first conducting wire layer and the second conducting wire layer of these relative both sides of dielectric base, this the first conducting wire layer comprises a plurality of the first electric connection pads, and this second conducting wire layer comprises a plurality of the second electric connection pads;
The surface that is exposed to this first conducting wire layer in this first conducting wire layer and this dielectric base arranges the first glue-line, and just the first substrate of glass is adhered on this first glue-line; And
At this first glass basic surface, form the 3rd conducting wire layer, and form a plurality of the first guide holes of running through this first substrate of glass and the first glue-line, the one end in the plurality of the first guide hole is electrically connected on the 3rd conducting wire layer, the relative other end is electrically connected on respectively the plurality of the first electric connection pad, thereby forms chip package base plate.
2. the manufacture method of chip package base plate as claimed in claim 1, is characterized in that, the manufacture method in the 3rd conducting wire layer and the first guide hole comprises step:
By laser pit technique, in this first substrate of glass, form a plurality of the first blind holes that run through this first substrate of glass and the first glue-line, the plurality of the first blind hole exposes respectively the plurality of the first electric connection pad;
Surface and this first glass basic surface at the inwall of the plurality of the first blind hole, the plurality of the first electric connection pad form continuous Seed Layer;
The photoresist layer that forms patterning at this first glass basic surface, this photoresist layer exposes the plurality of the first blind hole;
By electric plating method, on the surface that is exposed to the Seed Layer of this photoresist layer, form copper electroplating layer; And
Remove this photoresist layer, and remove the part that this Seed Layer is covered by this photoresist layer, the Seed Layer and the copper electroplating layer that remain in this first glass basic surface form the 3rd conducting wire layer, and the Seed Layer in the plurality of the first blind hole and copper electroplating layer form the plurality of the first guide hole.
3. the manufacture method of chip package base plate as claimed in claim 1, is characterized in that, the manufacture method in the 3rd conducting wire layer and the first guide hole comprises step:
By laser pit technique, in this first substrate of glass, form a plurality of the first blind holes that run through this first substrate of glass and the first glue-line, the plurality of the first blind hole exposes respectively the plurality of the first electric connection pad;
Filled conductive cream in the plurality of the first blind hole;
At this first glass basic surface, form continuous Seed Layer;
The photoresist layer that forms patterning at this first glass basic surface, the Seed Layer relative with the plurality of the first blind hole is exposed to this photoresist layer;
By electric plating method, on the surface that is exposed to the Seed Layer of this photoresist layer, form copper electroplating layer; And
Remove this photoresist layer, and remove the part that this Seed Layer is covered by this photoresist layer, the Seed Layer and the copper electroplating layer that remain in this first glass basic surface form the 3rd conducting wire layer, and in the plurality of the first blind hole, conductive paste forms the plurality of the first guide hole.
4. the manufacture method of chip package base plate as claimed in claim 1, is characterized in that, after forming the 3rd conducting wire layer and the first guide hole, further comprises step:
In the 3rd conducting wire layer one side, stack gradually and form the first dielectric layer and the 5th conducting wire layer; And
In the 5th conducting wire layer side, form the first welding resisting layer, this the first welding resisting layer cover part the 5th conducting wire layer, the 5th conducting wire layer that is exposed to this first welding resisting layer forms the 5th electric connection pad, and the 5th electric connection pad is for being electrically connected to chip to be packaged.
5. the manufacture method of chip package base plate as claimed in claim 1, is characterized in that, this first substrate of glass protrudes from the surface of this first glue-line or embeds in this first glue-line.
6. the manufacture method of chip package base plate as claimed in claim 1, is characterized in that, the manufacture method of this chip package base plate further comprises step:
The surface that is exposed to this second conducting wire layer in the second conducting wire layer is surperficial and this dielectric base arranges the second glue-line, and the second substrate of glass is adhered on this second glue-line; And
At this second glass basic surface, form the 4th conducting wire layer, and form a plurality of the second guide holes of running through this second substrate of glass and the second glue-line, the one end in the plurality of the second guide hole is electrically connected on the 4th conducting wire layer, and the relative other end is electrically connected on respectively the plurality of the second electric connection pad.
7. the manufacture method of chip package base plate as claimed in claim 6, is characterized in that, the manufacture method of this chip package base plate further comprises step:
In the 4th conducting wire layer one side, stack gradually and form the second dielectric layer and the 6th conducting wire layer; And
In the 6th conducting wire layer side, form the second welding resisting layer, this the second welding resisting layer cover part the 6th conducting wire layer, the 6th conducting wire layer that is exposed to this second welding resisting layer forms the 6th electric connection pad, and the 6th electric connection pad is for being electrically connected to other base plate for packaging or circuit board.
8. a chip package base plate, comprising:
Circuit board central layer, comprises dielectric base and forms the first conducting wire layer and the second conducting wire layer of these relative both sides of dielectric base, this first conducting wire layer comprises a plurality of the first electric connection pads, and this second conducting wire layer comprises a plurality of the second electric connection pads; And
The first glue-line, the first substrate of glass and the 3rd conducting wire layer, this first glue-line is formed at this layer surface, the first conducting wire and this dielectric base is exposed on the surface of this first conducting wire layer, this first substrate of glass is adhered on this first glue-line, the 3rd conducting wire layer is formed at this first glass basic surface, and is electrically connected to respectively with the plurality of the first electric connection pad by being formed at a plurality of first guide holes of this first substrate of glass and the first glue-line.
9. chip package base plate as claimed in claim 8, it is characterized in that, this chip package base plate further comprises the second film, the second substrate of glass and the 4th conducting wire layer, this second glue-line is formed at this layer surface, the second conducting wire and this dielectric base is exposed on the surface of this second conducting wire layer, this second substrate of glass is adhered on this second glue-line, the 4th conducting wire layer is formed at this second glass basic surface, and be electrically connected to respectively with the plurality of the second electric connection pad by being formed at a plurality of second guide holes of this second substrate of glass and the second glue-line.
10. chip package base plate as claimed in claim 8, it is characterized in that, this chip package base plate further comprises the first dielectric layer that is cascadingly set on the 3rd conducting wire layer one side, the 5th conducting wire layer and the first welding resisting layer, and the second dielectric layer that is cascadingly set on the 4th conducting wire layer one side, the 6th conducting wire layer and the second welding resisting layer, the 5th conducting wire layer is formed on this first dielectric layer, this the first welding resisting layer cover part the 5th conducting wire layer, the 5th conducting wire layer that is exposed to this first welding resisting layer forms the 5th electric connection pad, the 6th conducting wire layer is formed on this second dielectric layer, this the second welding resisting layer cover part the 6th conducting wire layer, the 6th conducting wire layer that is exposed to this second welding resisting layer forms the 6th electric connection pad.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201310137349.5A CN104112673B (en) | 2013-04-19 | 2013-04-19 | Chip package base plate and preparation method thereof |
| TW102114782A TWI503941B (en) | 2013-04-19 | 2013-04-25 | Chip package substrate and method for manufacturing same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310137349.5A CN104112673B (en) | 2013-04-19 | 2013-04-19 | Chip package base plate and preparation method thereof |
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| CN104112673A true CN104112673A (en) | 2014-10-22 |
| CN104112673B CN104112673B (en) | 2017-06-23 |
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| CN201310137349.5A Active CN104112673B (en) | 2013-04-19 | 2013-04-19 | Chip package base plate and preparation method thereof |
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| TW (1) | TWI503941B (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN104112673B (en) | 2017-06-23 |
| TW201442181A (en) | 2014-11-01 |
| TWI503941B (en) | 2015-10-11 |
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