CN107180821A - 半导体元件 - Google Patents

半导体元件 Download PDF

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CN107180821A
CN107180821A CN201611007441.XA CN201611007441A CN107180821A CN 107180821 A CN107180821 A CN 107180821A CN 201611007441 A CN201611007441 A CN 201611007441A CN 107180821 A CN107180821 A CN 107180821A
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fin
epitaxy
substrate
resistance
exposure
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胡嘉欣
范学实
黄焕宗
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本揭露提供一种半导体元件，包含鳍、多个磊晶生长区，以及至少二接触点。鳍自基板向外延伸，且包含半导体材料。磊晶生长区沿着鳍的上表面配置，其中在鳍的上表面，磊晶生长区与不具有磊晶材料的多个区域交替排列。接触点配置于与鳍电接触，其中接触点之间的电阻值至少部分取决于磊晶生长区的排列。

Description

半导体元件
技术领域
本揭露是关于一种半导体元件，特别是关于一种电阻。
背景技术
电阻可制造在与场效晶体管(field effect transistors；FETs)相同的基板上，以作为相同集成电路的一部分。电阻一般而言具有两个接触点，两接触点透过一个经掺杂的半导体材料隔开。掺杂浓度及型态，以及接触点的形状，包含接触点之间的距离等，皆对电阻的电阻值扮演着重要的角色。由于制程上的一些限制，要达成极低电阻值是具有相当难度的。
发明内容
本揭露的一实施例为一种半导体元件，包含一鳍、多个磊晶生长区，以及至少二接触点。鳍自基板向外延伸，且包含半导体材料。磊晶生长区沿着鳍的上表面配置，其中在鳍的上表面，磊晶生长区与不具有磊晶材料的多个区域交替排列。接触点配置于与鳍电接触，其中接触点之间的电阻值至少部分取决于磊晶生长区的排列。
附图说明
阅读以下详细叙述并搭配对应的附图，可了解本揭露的多个态样。应注意，根据业界中的标准做法，多个特征并非按比例绘制。事实上，多个特征的尺寸可任意增加或减少以利于讨论的清晰性。
图1为本揭露的一实施例的鳍式电阻的立体视图；
图2为本揭露的一实施例的鳍式电阻的上视图；
图3为本揭露的一实施例的具有虚设结构的鳍式电阻的上视图；
图4A至图4G为本揭露的一实施例的鳍式电阻的制造流程图；
图5为不同电阻的量测数据的图表；
图6为本揭露的一实施例的方法的流程图。
具体实施方式
以下揭露提供众多不同的实施例或范例，用于实施本案提供的主要内容的不同特征。下文描述一特定范例的组件及配置以简化本揭露。当然，此范例仅为示意性，且并不拟定限制。举例而言，以下描述“第一特征形成在第二特征的上方或之上”，于实施例中可包括第一特征与第二特征直接接触，且亦可包括在第一特征与第二特征之间形成额外特征使得第一特征及第二特征无直接接触。此外，本揭露可在各范例中重复使用元件符号及/或字母。此重复的目的在于简化及厘清，且其自身并不规定所讨论的各实施例及/或配置之间的关系。
此外，空间相对术语，诸如“下方(beneath)”、“以下(below)”、“下部(lower)”、“上方(above)”、“上部(upper)”等等在本文中用于简化描述，以描述如附图中所图示的一个元件或特征结构与另一元件或特征结构的关系。除了描绘图示的方位外，空间相对术语也包含元件在使用中或操作下的不同方位。此设备可以其他方式定向(旋转90度或处于其他方位上)，而本案中使用的空间相对描述词可相应地进行解释。
一般而言，最常见的场效晶体管(field effect transistors；FET)为金属氧化物半导体场效晶体管(metal oxide semiconductor field effect transistor；MOSFET)。就以往的状况而言，金属氧化物半导体场效晶体管为平面结构，且制造于基板(如：晶圆)的平坦表面上。然而近期半导体制造的发展已可使用垂直结构。
词汇“鳍式场效晶体管”(fin field effect transistor；FinFET)意味着场效晶体管是形成在鳍的上方，且鳍相对于晶圆的平坦的表面为垂直的配置。
词汇“磊晶层”(epitaxial layer)意味着单晶材料层或结构。同样地，词汇“磊晶生长”(epitaxially grown)意味着单晶材料层或结构。
词汇“接触点”(contact)意味着一种用于将导体电连接至其他内连接层的结构。上述的词汇有时候用于描述绝缘体内的一开口，以用于形成后续完成的结构。亦可用于描述完成的结构。本揭露的“接触点”代表已完成的结构，而“接触孔”(contact hole)则是用于描述在绝缘体内形成结构(如：接触点)的一个或多个开口。
本揭露的不同实施例提供一种在鳍结构内形成电阻的设计。鳍结构可为半导体材料，且自基板的表面向外垂直延伸。接触点的形成是用于电接触鳍结构且形成电阻的接触点。
于部分实施例中，电阻包含将接触点形成为磊晶生长材料的型态。这些电阻的电阻值取决于磊晶层的几何形状。由于控制磊晶材料的生长具有难度，故对于电阻值的控制将不容易。一种可能的方法为，将接触点的磊晶生长材料局限在极小的区域，以限制生长的变异性，然而此方法亦限制了所能达到的电阻值。
为了影响结构的整体的电阻率，本揭露的部分实施例中，鳍结构的部分区域被蚀刻并填补磊晶生长材料。本揭露的实施例所描述的鳍式电阻对于最终的电阻值具有较好的控制性，而且可与标准的鳍式场效晶体管制程适当地结合。因此，集成电路的基板上可同时具有鳍式场效晶体管以及电阻。
图1为本揭露的一实施例的鳍式电阻100的立体视图。鳍式电阻100形成于鳍102中，且往基板104外延伸。基板104可为硅基板。或者，基板104可包含其他元素半导体，如锗(germanium)；化合物半导体，如碳化硅(silicon carbide)、砷化镓(gallium arsenic)、磷化镓(gallium phosphide)、磷化铟(indium phosphide)、砷化铟(indium arsenide)，及/或锑化铟(indium antimonide)；合金半导体，如硅锗(SiGe)、磷砷化镓(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、砷化铟镓(InGaAs)、磷化镓铟(GaInP)，及/或磷砷化铟镓(GaInAsP)；或上述的组合。于一实施例中，基板104为绝缘体上半导体(semiconductor oninsulator；SOI)。
鳍102与基板104可为相同材料，如经掺杂的硅。鳍102与基板104可具有相同的掺杂型态(如：N型掺杂剂或P型掺杂剂)。于另一范例中，鳍102包含N型掺杂剂而基板104包含P型掺杂剂，反之亦然。N型掺杂剂可包含磷或砷。P型掺杂剂可为硼或铟。鳍102可透过蚀刻基板104形成，并使用已知的蚀刻技术，例如反应式离子蚀刻或湿硅蚀刻。于其他范例中，鳍102是透过在基板104上蚀刻磊晶层或气相沉积半导体层。
鳍102的表面具有交替区，分别为磊晶生长材料区106以及暴露的鳍区108。磊晶生长材料区106的数量不限定于附图所描绘的数量。相同地，鳍区108的数量不限定于附图所描绘的数量。交替区的详细制造细节将于图4A至图4G中描述。
本揭露的部分实施例的鳍式电阻100亦包含两接触点110a及110b。于一实施例中，接触点110a与靠近端点(沿着X方向)的鳍102电性接触，而接触点110b与靠近另一侧的端点(沿着X方向)的鳍102电性接触。两接触点之间的电阻值至少部分取决于磊晶生长材料区106的配置。一个材料的电阻值一般而言可以下列方程式表示：
其中ρ为材料的电阻率，L为两接触点间材料的长度，而A为两接触点间材料的截面积。因此。材料的特性以及磊晶生长材料区106的大小以及鳍区108至少部分决定了电阻整体的电阻值。本揭露的实施例所描述的电阻相较于以往的设计具有更低的电阻值。例如，本揭露所描述的鳍式电阻设计的电阻值可达到约100欧姆/单位面积(ohms/sq.)。此外，磊晶材料的限制生长亦使得电阻结构之间的变异性降低。
磊晶生长材料区106可包含硅锗(SiGe)。硅锗可掺杂有硼(SiGeB)。磊晶生长材料区106的其他范例为碳化硅(SiC)、磷化硅(SiP)，或掺杂磷的碳化硅(SiCP)。
虽然此处仅绘制二个接触点，然而鳍102的上表面或任何侧表面可具有任意数量的接触点。于一实施例中，各接触点110a及110b与磊晶生长材料区106物理接触。
图2为一实施例的鳍102支由上而下的视图。图2亦为相同交替排列的磊晶生长材料区106及曝露的鳍区108。接触点100a及110b与磊晶生长材料区106物理接触。
如图2所示，于一实施例中，鳍102包含图案化的柱状结构202，配置于鳍102的相对两侧。柱状结构202可用于限定鳍102的交替区段，包含交替的磊晶生长材料区106及曝露的鳍区108。于一范例中，接触点110a及110b与柱状结构202相连。柱状结构202可图案化为任意数量。于一范例中，柱状结构202与其相邻的接触点形成端部结构204。端部结构204可于鳍102的一侧或两侧重复，使得多个接触点以及多个柱状结构202图案化于鳍102的端点。于一实施例中，柱状结构202为多晶硅(polysilicon)。于一实施例中，柱状结构202是由相同栅极材料所形成，栅极材料是用于形成同一基板上的鳍式场效晶体管的栅极。柱状结构202可包含侧壁结构，侧壁结构类似于形成于鳍式场效晶体管的栅极的侧壁的结构。
鳍102的不同特征的尺寸于图2中指示。鳍102的宽度w可为约5纳米(nm)至约5000纳米。曝露的鳍区108的沿着X方向的长度d1可为约10纳米至约1000纳米。磊晶生长材料区106的沿着X方向的长度d2可为约50纳米至约500纳米。这些尺寸仅为范例，亦可具有其他尺寸。
图3为本揭露的实施例的鳍102的上视图，并包含一列虚设结构302。词汇“虚设结构”是指不与基板上任何结构或任何接触点电性连接的结构。虚设结构302与柱状结构202可为相同材料。于一实施例中，虚设结构302与柱状结构202同时图案化。虚设结构302在基板上可排列与鳍102相邻。虚设结构302可为任意数量。虚设结构302可在制造鳍式电阻时执行的某些特定蚀刻或研磨步骤时降低有害的负载效应(loading effect)。
图4A至图4G为本揭露的一实施例的鳍式电阻100的制造流程。应了解部分未图示的制造步骤亦可执行。
于图4A中，在基板404上形成鳍402。鳍402可通过在基板404上进行非等向性(anisotropic)蚀刻形成。鳍402及基板404可为相同的半导体材料，且具有相同的掺杂剂(N型或P型)。于另一实施例中，鳍402及基板404具有不同掺杂型态。在鳍402及基板404具有相同掺杂型态的实施例中，可使用隔离结构以将电阻与其他图案化于基板404上的元件电性绝缘。这些隔离结构可包含浅沟槽隔离(shallow trench isolation；STI)，或基板404中相对的掺杂区以创造P-N接面。位于鳍402下方的基板404的一部分可为井区(well region)，井区的掺杂型态可与基板404其余部分的掺杂型态不同。鳍402的高度h的范围约25纳米至约80纳米。
于图4B中，形成柱状结构406。柱状结构406可为多晶硅。于一实施例中，柱状结构406可自相同的栅极材料形成，其中栅极材料是用于在同一基板上形成晶体管的栅极。柱状结构406可于基板404上的晶体管的栅极进行图案化步骤时同时进行图案化。其他晶体管可包含鳍式场效晶体管元件，如美国专利编号U.S.PatentNo.8,877,592中所描述。亦应了解柱状结构406是选择性加入的。
柱状结构406可使用任何标准光微影技术图案化形成。例如，多晶硅层的沉积可通过在对光阻图案化以在光阻内产生开口并曝露多晶硅层。暴露的多晶硅层的区域被蚀刻，以留下图案化的多晶硅区域，如柱状结构406。柱状结构406可通过图案化使得柱状结构对准鳍402的蚀刻边缘，或是小于200纳米。于部分实施例中，鳍402与柱状结构406间具有介电层(未图示)。介电层可为二氧化硅(silicon dioxide)，或高介电常数材料。
于图4C中，对鳍402执行第一掺杂操作。掺杂可为N型或P型，并降低鳍402的整体电阻率。于一实施例中，此步骤的掺杂可同时用于制造基板404上的轻掺杂漏极(lightlydoped drain；LDD)。
图4D为鳍402的上表面的图案化步骤。首先，沉积遮罩层并图案化，使得鳍402的上表面包含两交替区，分别为遮罩结构408所覆盖的区域，以及未被遮罩结构408所覆盖的区域410。遮罩结构408可为任何已知的遮罩材料，如氮化硅。可对执行标准光微影技术以图案化遮罩层。
于一实施例中，在形成遮罩结构408后，区域410被蚀刻。蚀刻可为等向性蚀刻或非等向性蚀刻。蚀刻的深度可调整，且会影响电阻的最终电阻值。于一实施例中，蚀刻的深度为约25纳米至约100纳米。可使用反应式离子蚀刻进行蚀刻。亦可使用二氟化氙(Xenondifluoride)气体。于其他范例中，使用湿蚀刻化学材料以蚀刻鳍402。
于图4E中，在区域410中生长磊晶结构412。磊晶结构412可通过区域410暴露的硅生长硅锗。于一实施例中，在磊晶结构412生长后，移除遮罩结构408(图4D)，以在具有磊晶结构412的区域之间形成曝露的鳍区413。磊晶结构412的最终形状可具有变化，且根据不同因素而有所改变，如材料组成、生长素率，以及区域410的几何形状。于一实施例中，磊晶结构412形成与柱状结构406直接相邻。
于一实施例中，磊晶结构412与基板404上的其他鳍式场效晶体管元件的源/漏极为相同材料。磊晶结构412可与其他鳍式场效晶体管元件的源/漏极的磊晶材料同时生长。
鳍402的上表面的磊晶结构412的排列将会影响电阻结构401的电阻值。电阻结构401包含所有电阻的主动区(如：鳍402及磊晶结构412)。磊晶结构412的数量可取决于蚀刻区域之间的多个空间。于一实施例中，磊晶结构412的数量与蚀刻区域间的空间的数量相同。
于图4F中，在鳍402以及磊晶结构412上方执行第二掺杂操作。掺杂可为N型或P型，且可进一步降低电阻结构401的整体电阻率。于一实施例中，此步骤所执行的掺杂与基板404上的其他晶体管的源/漏极的掺杂相同。
于图4G中，形成接触点416a及416b以电接触电阻结构401。接触点416a及416b可形成于绝缘层414所蚀刻的孔洞中。更清楚而言，绝缘层414是预先形成于基板404及鳍402上，且厚度至少要大于柱状结构406自基板404的表面往外延伸的高度。绝缘层414可为任何绝缘材料。于一实施例中，绝缘层414为氮化硅。
绝缘层414可通过如化学机械研磨制程(chemical mechanical polishing；CMP)平坦化以形成实质上平坦的表面。绝缘层414接着进行蚀刻以形成接触孔，接触孔向下连接至电阻结构401。于接触孔内填补导电材料以形成接触点416a及416b。于一实施例中，接触点416a及416b的导电材料为钨(tungsten)。
于一实施例中，接触点416a及416b与磊晶结构412的区域物理接触。此区可与电阻结构401的相对两侧的柱状结构406相邻。在填补导电材料形成接触点416a及416b之后，可再次对绝缘层414的上表面执行研磨制程，以产生实质平坦的表面。可接着图案化金属线418a及418b以分别电性连接接触点416a及416b。
图5为不同鳍式电阻结构所量测的电阻值。X轴列举了不同的鳍式电阻及其测量方法。例如，PP_PW_4P代表使用四点探针测量(four-point probe measurement)基板上的P井区(PW)的P型鳍(PP)。PP_PW_2P代表使用二点探针测量基板上的P井区的P型鳍。NP_NW_4P代表使用四点探针测量基板上的N井区(NW)的N型鳍(NP)。NP_NW_2P代表使用二点探针测量基板上的N井区的N型鳍。NP_PW_2P代表使用二点探针测量基板上的P井区的N型鳍。
如图所示，在P井上使用P型掺杂剂与在N井上使用N型掺杂剂的电阻的电阻值变异量非常小。此外，测量到的电阻值中，P型电阻约为100欧姆/单位面积，而N型电阻约为500欧姆/单位面积。当鳍与下方的基板使用不同掺杂剂时，如鳍为N型，基板为P型，则测量到的电阻值具有较高的电阻值且具有较大的变异量。
图6为本揭露的一实施例的方法600的流程图。方法600用于形成半导体元件，如鳍式电阻100。其余未提及的制造步骤可在方法600的各个操作之间进行，然而为了简化的目的，这些步骤在本文中省略。
方法600开始于操作602，蚀刻一基板以形成鳍。鳍与基板可为相同材料，且使用相同掺杂剂(N型或P型)。于另一实施例中，鳍与基板为不同材料层，因此具有不同掺杂型态。在又其他实施例中，基板为绝缘体上硅基板，其中鳍形成在绝缘层(如氧化硅)上的硅层内。
方法600继续进行至操作604，对鳍进行掺杂。操作604以虚线表示，意味着操作604可选择性进行，并非制造电阻的必要步骤。于一实施例中，此步骤执行的掺杂与基板上晶体管的制造轻掺杂漏极的掺杂相同。
方法600继续进行至操作606，其中对鳍的上表面形成遮罩层并进行图案化，以形成遮罩结构。遮罩层可经由图案化，使得鳍的上表面可包含两交替区，分别为遮罩结构所覆盖的区域，以及未被遮罩结构所覆盖的区域。遮罩结构可为任何已知的遮罩材料，如氮化硅。可对执行标准光微影技术以图案化遮罩层。
方法600继续进行至操作608，鳍的上表面的未被被遮罩结构所覆盖的区域进行蚀刻。蚀刻可为等向性蚀刻或非等向性蚀刻，蚀刻的深度会影响鳍式电阻的最终电阻值。
方法600继续进行至操作610，在鳍的上表面的曝露的蚀刻区磊晶生长材料。于一实施例中，磊晶生长材料可为硅锗，且鳍的上表面的磊晶生长材料的排列将会影响鳍式电阻的整体电阻值。在磊晶材料生长后，移除遮罩结构。在鳍上的磊晶生长材料的形成可与界定基板上的晶体管的源/漏极区的磊晶材料相同。
方法600继续进行至操作612，执行第二掺杂步骤以掺杂鳍与磊晶材料层。操作612用虚线表示，意味着操作604可选择性进行，并非制造电阻的必要步骤。于一实施例中，此步骤执行的掺杂与基板上晶体管的制造源/漏极的掺杂相同。
方法600继续进行至操作614，形成接触点以电性连接鳍式电阻。接触点包含导电材料，如钨，并延伸穿越沉积在鳍式电阻上方的绝缘层。于一实施例中，接触点与鳍的顶端的磊晶生长材料物理接触。
本揭露的一实施例为一种半导体元件，包含一鳍、多个磊晶生长区，以及至少二接触点。鳍自基板向外延伸，且包含半导体材料。磊晶生长区沿着鳍的上表面配置，其中在鳍的上表面，磊晶生长区与不具有磊晶材料的多个区域交替排列。接触点配置于与鳍电接触，其中接触点之间的电阻值至少部分取决于磊晶生长区的排列。
依据本揭露的部分实施例，半导体元件还包含两柱状结构，位于鳍的上表面，其中多个磊晶生长区排列在两柱状结构之间。
依据本揭露的部分实施例，其中两柱状结构包含多晶硅。
依据本揭露的部分实施例，其中鳍延伸出基板内的井区，且其中鳍包含N型掺杂剂而井区包含P型掺杂剂。
依据本揭露的部分实施例，其中鳍延伸出基板内的井区，且其中鳍包含P型掺杂剂而井区包含N型掺杂剂。
依据本揭露的部分实施例，其中鳍延伸出基板内的井区，且其中鳍与井区皆包含N型掺杂剂或P型掺杂剂。
依据本揭露的部分实施例，其中至少两接触点物理接触多个磊晶生长区内的磊晶生长材料。
依据本揭露的部分实施例，其中鳍包含硅，而多个磊晶生长区包含硅锗。
依据本揭露的部分实施例，半导体元件还包含多个虚设结构，配置于基板表面上以及相邻于鳍。
本揭露的另一实施例为一种制造半导体元件的方法，包含蚀刻基板以形成自基板突出的鳍。图案化位于鳍的上表面的遮罩层，使得鳍的上表面的曝露区与被遮罩层覆盖的区域交替排列。蚀刻鳍的上表面的曝露区。在鳍的上表面的曝露区内磊晶生长一材料。形成接触点，以电接触鳍，其中接触点之间的电阻至少部分取决于鳍的上表面的曝露区内的磊晶生长材料的排列。
依据本揭露的部分实施例，上述方法还包含在蚀刻曝露区域之后，移除遮罩层。
依据本揭露的部分实施例，上述方法还包含形成两柱状结构，柱状结构位于鳍的上表面，其中鳍的上表面的曝露区排列于两柱状结构之间。
依据本揭露的部分实施例，上述方法还包含在图案化遮罩层之前掺杂鳍。
依据本揭露的部分实施例，其中掺杂为用于基板上的一个或多个鳍式场效晶体管的轻掺杂漏极(lightly doped drain)制程。
依据本揭露的部分实施例，上述方法还包含掺杂鳍以及磊晶生长材料。
依据本揭露的部分实施例，其中掺杂亦掺杂了基板上的一个或多个鳍式场效晶体管的源极与漏极区。
依据本揭露的部分实施例，其中形成接触点包含形成接触点使得接触点与磊晶生长材料物理接触。
依据本揭露的部分实施例，上述方法还包含形成多个虚设结构，虚设结构排列在基板上以及相邻于鳍。
依据本揭露的部分实施例，其中鳍包含硅，而多个磊晶生长区包含硅锗。
本揭露的又一实施例为一种集成电路，包含位于基板上的多个场效晶体管，以及位于基板上的电阻。其中电阻包含鳍、多个磊晶区，以及至少两个接触点。鳍自基板突出且包含半导体材料。磊晶生长区沿着鳍的上表面配置，其中磊晶生长区与鳍的上表面的不具有磊晶材料的区域交替排列。接触点提供鳍电接触，其中两接触电之间的电阻至少部分取决于磊晶生长区的排列。
应了解实施方式的部分仅用于解释申请专利范围。而摘要部分仅描述一个或多个实施例，且并非发明人所思忖的全部实施例，因此并不用于限制本揭露以及申请专利范围。
上文概述了若干实施例的特征，以便本领域熟悉此项技艺者可更好地理解本揭示案的态样。本领域熟悉此项技艺者应当了解到他们可容易地使用本揭示案作为基础来设计或者修改其他制程及结构，以实行相同目的及/或实现相同优势的。本领域熟悉此项技艺者亦应当了解到，此类等效构造不脱离本揭示案的精神及范畴，以及在不脱离本揭示案的精神及范畴的情况下，其可对本文进行各种改变、取代及变更。

Claims (1)

1.一种半导体元件，其特征在于，包含：
一鳍，自一基板向外延伸，该鳍包含半导体材料；
多个磊晶生长区，配置于沿着该鳍的上表面，其中在该鳍的上表面，所述多个磊晶生长区与不具有磊晶材料的多个区域交替排列；以及
至少二接触点，配置于与该鳍电接触，其中所述接触点之间的一电阻值至少部分取决于所述多个磊晶生长区的排列。
CN201611007441.XA 2016-03-11 2016-11-16 半导体元件 Pending CN107180821A (zh)

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