CN107170817A - 一种横向igbt - Google Patents

一种横向igbt Download PDF

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CN107170817A
CN107170817A CN201710456204.XA CN201710456204A CN107170817A CN 107170817 A CN107170817 A CN 107170817A CN 201710456204 A CN201710456204 A CN 201710456204A CN 107170817 A CN107170817 A CN 107170817A
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CN107170817B (zh
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陈万军
陶宏
刘亚伟
刘承芳
刘杰
张波
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University of Electronic Science and Technology of China
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7394Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708Emitter or collector electrodes for bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明属于功率半导体器件技术领域,涉及一种横向IGBT。本发明提出一种新的横向IGBT结构,通过抑制P阱区对漂移区非平衡空穴的抽取作用,增大发射极的电子注入效率,增强P阱区与漂移区所形成PN结附近的电导调制效应,进而减小器件导通压降;通过抑制栅极与漂移区之间的电荷耦合作用可以降低密勒电容,进而提升器件的开关特性。

Description

一种横向IGBT
技术领域
本发明属于功率半导体器件技术领域,涉及一种横向IGBT。
背景技术
功率集成电路至上世纪70年代问世以来便以更低的功耗、体积及成本和更高的可靠性与稳定性在工业界被广泛使用。在其发展历程中,电路中所采用的集成功率器件从最初的驱动、保护较为复杂的流控型器件如晶体三极管、晶闸管,逐步发展为具有高输入阻抗、驱动、保护较为简单的压控型器件如横向双扩散MOSFET(LDMOS)和横向IGBT(LIGBT)。由于具有电导调制效应,在一定的电压范围内,LIGBT可以比LDMOS具有更低的导通损耗,因此可在中高压、低频应用条件下取代LDMOS,以降低系统功耗。
虽然LIGBT中的电导调制效应有利于减小器件电阻,但是由于器件在正向导通时,P阱区与漂移区形成的PN结是反偏的,导致该结附近的非平衡载流子浓度很低,电导调制效应较弱,从而使器件仍具有较大的导通压降,进而不利于系统功耗的降低。此外,由于栅极与漂移区之间的电荷耦合作用,导致器件具有一定的密勒电容,该电容的存在将增大器件的开关延迟时间和开关功耗。文献(罗小蓉,《一种横向IGBT》,电子科技大学)提出通过在P阱区和漂移区之间引入隔离槽来抑制P阱区对漂移区空穴的抽取作用,进而有利于提高空穴浓度,减小导通压降。但隔离槽内部设置了栅极结构G,栅极G与漂移区之间存在较大的电荷耦合面积,从而导致该结构具有很大的密勒电容,进而给器件的动态特性带来不利影响
发明内容
本发明针对上述问题,提出一种新的横向IGBT结构,通过抑制P阱区对漂移区非平衡空穴的抽取作用,增大发射极的电子注入效率,从而增强P阱区与漂移区所形成PN结附近的电导调制效应,进而减小器件导通压降;通过抑制栅极与漂移区之间的电荷耦合作用可以降低密勒电容,进而提升器件的开关特性。
本发明技术方案如下:
一种横向IGBT,其元胞包括自下而上依次层叠设置的衬底1、埋氧化层2和SOI层;所述SOI层包括发射极结构、栅极11、漂移区3以及集电极结构,其中集电极结构位于漂移区3一侧的上层,所述集电极结构包括N型缓冲区4、位于N型缓冲区4上层的P+集电区5和由P+集电区引出的集电极12;所述发射极结构位于漂移区3另一侧的上层,所述发射极结构包括发射极10、N型源区6、P+接触区7和P阱区8,所述P阱区8位于漂移区3的上层,所述N型源区6位于P阱区8上层远离集电极结构的一侧,所述P+接触区7的上表面与N型源区6的下表面接触,且P+接触区7的下表面与埋氧化层2的上表面接触;其特征在于,所述栅极11覆盖P阱区8的上表面,并沿P阱区8纵向方向两侧的侧面向下延伸直至覆盖P阱区8的侧壁,所述纵向方向为同时与器件平面方向和器件垂直方向均垂直的第三维方向;沿器件垂直方向的俯视图中,所述发射极10呈“C”字型,即发射极10将P阱区8和栅极11包围且在靠近漂移区3的一侧有开口,发射极10的内壁与N型源区6和P+接触区7接触。
进一步的,所述栅极11的底部延伸至与埋氧化层2相接触,栅极11与发射极10之间通过介质层9隔离,且沿器件纵向方向,栅极10向两侧延伸至覆盖发射极10的上方。
进一步的,所述发射极10的底部与埋氧化层2相接触,发射极10与漂移区3之间通过介质层9隔离。
本发明的有益效果为,相对于传统的结构,能有效降低器件导通功耗并提升器件的动态特性。
附图说明
图1为本发明所提出的横向IGBT整体结构示意图;
图2为本发明所提出的横向IGBT的剖面结构示意图;
图3为器件导通时P阱区周围电子电流分布示意图;
图4为本发明所提出的横向IGBT结构的俯视图和空穴电流分布示意图;
图5为开关过程中漂移区与发射极之间的电荷耦合示意图。
具体实施方式
下面结合附图对本发明进行详细的描述
如图1和图2所示,为本发明器件的元胞结构示意图,该结构的工作原理为:
如图3所述,图中带箭头的实线为器件导通时P阱区8周围的电子电流分布示意图,其中箭头的指向代表电子电流的流向。由于器件中引入的三维环绕栅极结构增大了MOS结构的有效沟道宽度,使器件的沟道电阻减小,进而有利于减小器件的导通压降。器件结构的俯视图如图4所示,图中带箭头的实线为器件导通时空穴电流分布示意图,其中箭头的指向代表空穴电流的流向,由于器件中引入的三维环绕栅极结构减小了P阱区8与漂移区3的有效接触面积,抑制了P阱区8对漂移区3中空穴的抽取作用,从而可以提高漂移区3靠近P阱区8周围的非平衡空穴浓度,进而有利于减小器件的导通压降。
如图5所示,图中箭头表示器件在开关过程中漂移区3与发射极10之间的电场线分布示意图,其中箭头的指向代表电场的方向。由于“C”字型发射极10处于栅极11和漂移区3之间,因此可以在一定程度上屏蔽栅极11与漂移区3之间的电荷耦合作用,从而能够降低器件的密勒电容,实现器件开关特性的提升。

Claims (3)

1.一种横向IGBT,其元胞包括自下而上依次层叠设置的衬底(1)、埋氧化层(2)和SOI层;所述SOI层包括发射极结构、栅极(11)、漂移区(3)以及集电极结构,其中集电极结构位于漂移区(3)一侧的上层,所述集电极结构包括N型缓冲区(4)、位于N型缓冲区(4)上层的P+集电区(5)和由P+集电区引出的集电极(12);所述发射极结构位于漂移区(3)另一侧的上层,所述发射极结构包括发射极(10)、N型源区(6)、P+接触区(7)和P阱区(8),所述P阱区(8)位于漂移区(3)的上层,所述N型源区(6)位于P阱区(8)上层远离集电极结构的一侧,所述P+接触区(7)的上表面与N型源区(6)的下表面接触,且P+接触区(7)的下表面与埋氧化层(2)的上表面接触;其特征在于,所述栅极(11)覆盖P阱区(8)的上表面,并沿P阱区(8)纵向方向两侧的侧面向下延伸直至覆盖P阱区(8)的侧壁,所述纵向方向为同时与器件平面方向和器件垂直方向均垂直的第三维方向;沿器件垂直方向的俯视图中,所述发射极(10)呈“C”字型,即发射极(10)将P阱区(8)和栅极(11)包围且在靠近漂移区(3)的一侧有开口,发射极(10)的内壁与N型源区(6)和P+接触区(7)接触。
2.根据权利要求1所述的一种横向IGBT,其特征在于,所述栅极(11)的底部延伸至与埋氧化层(2)相接触,栅极(11)与发射极(10)之间通过介质层(9)隔离,且沿器件纵向方向,栅极(10)向两侧延伸至覆盖发射极(10)的上方。
3.根据权利要求2所述的一种横向IGBT,其特征在于,所述发射极(10)的底部与埋氧化层(2)相接触,发射极(10)与漂移区(3)之间通过介质层(9)隔离。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021128435A1 (zh) * 2019-12-28 2021-07-01 汪克明 新半导体电子原理技术与器件

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JP2012124410A (ja) * 2010-12-10 2012-06-28 Toyota Motor Corp 半導体装置
CN103839802A (zh) * 2012-11-23 2014-06-04 中国科学院微电子研究所 一种沟槽型igbt结构的制作方法
CN106024873A (zh) * 2016-05-20 2016-10-12 电子科技大学 一种横向igbt
CN106206702A (zh) * 2016-07-19 2016-12-07 东南大学 分段双沟槽高压屏蔽的横向绝缘栅双极器件
CN106505101A (zh) * 2016-10-19 2017-03-15 东南大学 一种大电流绝缘体上硅横向绝缘栅双极型晶体管器件

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012124410A (ja) * 2010-12-10 2012-06-28 Toyota Motor Corp 半導体装置
CN103839802A (zh) * 2012-11-23 2014-06-04 中国科学院微电子研究所 一种沟槽型igbt结构的制作方法
CN106024873A (zh) * 2016-05-20 2016-10-12 电子科技大学 一种横向igbt
CN106206702A (zh) * 2016-07-19 2016-12-07 东南大学 分段双沟槽高压屏蔽的横向绝缘栅双极器件
CN106505101A (zh) * 2016-10-19 2017-03-15 东南大学 一种大电流绝缘体上硅横向绝缘栅双极型晶体管器件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021128435A1 (zh) * 2019-12-28 2021-07-01 汪克明 新半导体电子原理技术与器件

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