CN106024873A - 一种横向igbt - Google Patents

一种横向igbt Download PDF

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CN106024873A
CN106024873A CN201610344066.1A CN201610344066A CN106024873A CN 106024873 A CN106024873 A CN 106024873A CN 201610344066 A CN201610344066 A CN 201610344066A CN 106024873 A CN106024873 A CN 106024873A
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罗小蓉
邓高强
周坤
吴俊峰
张彦辉
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University of Electronic Science and Technology of China
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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Abstract

本发明属于功率半导体器件技术领域,涉及一种横向IGBT。本发明的横向IGBT器件,其技术方案是:SOI层上层两端分别具有P型阱区和N型阱区;N型阱区表面远离P型阱区的一端具有P型阳极区,P型阱区表面远离N型阱区的一端具有相互独立的P型体接触区和N型阴极区,N型阴极区位于靠近N型阱区的一侧;由P型体接触区和N型阴极区引出阴极电极;其特征在于,在靠近器件阴极一侧引入隔离槽,隔离槽沿器件纵向方向有开口,且隔离槽由位于槽内壁的介质层和由介质层包围的导电材料构成,其侧壁与P型阱区中的N型阴极区接触形成槽栅结构,所述P型体接触区和N型阴极区沿器件纵向方向均分为两段,两段之间有间距,并沿器件的横向中线呈对称结构。

Description

一种横向IGBT
技术领域
本发明属于功率半导体器件技术领域,涉及一种横向IGBT(绝缘栅双极型晶体管)。
背景技术
IGBT是20世纪80年代发展起来的一种新型功率器件,它运用一个MOSFET结构的栅驱动电流向一个双极结型晶体管提供基极电流,使其兼具BJT的大电流能力和MOS管的压控型驱动电路。IGBT极大的电流能力使其在中高压领域备受青睐,因此其自诞生以来就被广泛用于电机控制、智能电网以及交通运输等众多领域。
IGBT的大电流能力源于其漂移区的电导调制效应,通过提高漂移区中过剩载流子浓度可以有效降低IGBT的导通压降、增大导通电流。提高漂移区中过剩载流子浓度的常用方式有两种:一为增大阳极PN结的注入效率,即提高阳极区P型杂质的掺杂剂量或降低N型缓冲层的掺杂浓度,该方式可以使得IGBT正向导通时在漂移区远离阴极端的一侧有着极高的载流子浓度,然而这些载流子因远离P型体区和N型漂移区形成的耐压PN结,所以在IGBT关断时无法被耗尽区内建电场快速扫出漂移区,造成关断时间长、关断损耗大等不良影响。二为采用电子注入增强型IGBT(IEGT)。
本发明通过增强电子注入极大地降低了横向IGBT的导通压降,同时很好地改善了关断损耗与导通压降的折衷关系。
发明内容
本发明所要解决的,就是针对上述问题,提出一种极大降低了导通压降的横向IGBT。
本发明的技术方案是:一种横向IGBT,包括从下至上依次层叠设置的衬底1、介质层2和SOI层3;所述SOI层上层两端分别具有P型阱区6和N型阱区4;所述N型阱区4表面远离P型阱区6的一端具有P型阳极区5,由P型阳极区5引出阳极电极;所述P型阱区6表面具有相互独立的P型体接触区11和N型阴极区12,所述N型阴极区12位于靠近N型阱区4的一侧;由P型体接触区11和N型阴极区12引出阴极电极;其特征在于,所述SOI层3中具有隔离槽9,所述隔离槽9与N型阴极区12接触,隔离槽9深度大于P型阱区6的结深;隔离槽9沿器件纵向方向分为两段,两段隔离槽之间的间距为N。隔离槽9由位于槽内壁的介质层和由介质层包围的导电材料构成;由隔离槽9中的导电材料引出栅电极,形成槽栅结构。所述P型体接触区11和N型阴极区12均沿器件纵向方向分为两段,两段之间有间距,并沿器件的横向中线呈对称结构,两段P型体接触区11和N型阴极区12间距均为G,且满足G>N。
进一步的,沿器件纵向方向,所述P型阱区6分为两段,且两段P型阱区之间的间距为M;沿器件横向方向,两段P型阱区之间形成的开口与两段隔离槽之间形成的开口相对应,并且满足G>M>N。
进一步的,两段P型阱区除去P型体接触区11和N型阴极区12以外的表面形成平面栅结构并引出栅电极,平面栅与P型体接触区11和N型阴极区12均接触。
进一步的,所述N型阴极区12在器件的俯视图上呈“L”字形的镜像,P型体接触区11位于“L”字形的开口处。所述两段P型阱区除去P型体接触区11和N型阴极区12以外的表面形成平面栅结构并引出栅电极,平面栅与N型阴极区12接触,不与P型体接触区11接触
本发明的有益效果为,能极大的降低IGBT器件的导通压降。
附图说明
图1是实施例1的结构示意图;
图2是实施例2的结构示意图;
图3是实施例3的结构示意图;
图4是实施例4的结构示意图;
图5是实施例4的俯视结构示意图;
图6是实施例5的俯视结构示意图。
具体实施方式
下面结合附图和实施例,详细描述本发明的技术方案:
实施例1,如图1所示,本例包括从下至上依次层叠设置的衬底1、介质层2和SOI层3;所述SOI层上层两端分别具有P型阱区6和N型阱区4;所述N型阱区4表面远离P型阱区6的一端具有P型阳极区5,由P型阳极区5引出阳极电极;所述P型阱区6表面具有相互独立的P型体接触区11和N型阴极区12,所述N型阴极区12位于靠近N型阱区4的一侧;由P型体接触区11和N型阴极区12引出阴极电极;其特征在于,所述SOI层3中具有隔离槽9,所述隔离槽9与N型阴极区12接触,隔离槽9深度大于P型阱区6的结深;隔离槽9沿器件纵向方向分为两段,两段隔离槽之间的间距为N。隔离槽9由位于槽内壁的介质层和由介质层包围的导电材料构成;由隔离槽9中的导电材料引出栅电极,形成槽栅结构。所述P型体接触区11和N型阴极区12均沿器件纵向方向分为两段,两段之间有间距,并沿器件的横向中线呈对称结构,两段P型体接触区11和N型阴极区12间距均为G,且满足G>N。
本例的工作原理为:
在横向IGBT阴极端的P型阱区6与漂移区之间制造隔离槽用以在IGBT导通时阻挡漂移区中的空穴被阴极抽取。IGBT在导通时,阳极注入的空穴与沟道注入的电子在漂移区发生电导调制,大大降低了导通压降,本例中位于阴极一侧的隔离槽仅留有小尺寸开口,从阳极端注入的空穴因为该隔离槽的存在而大量贮存于靠近阴极端的漂移区,为维持漂移区的电中性,从沟道注入漂移区的电子也相应增多,所以IGBT漂移区的载流子浓度得以大幅提升,导通压降改善明显。
实施例2
如图2所示,本例在实施例1基础之上,将P型阱区6沿器件纵向方向分为两段,且两段P型阱区之间的间距为M;沿器件横向方向,两段P型阱区之间形成的开口与两段隔离槽之间形成的开口相对应,并且满足G>M>N。
实施例3
如图3所示,本例在实施例2基础之上,在两段P型阱区除去P型体接触区11和N型阴极区12以外的表面形成平面栅结构并引出栅电极,平面栅与P型体接触区11和N型阴极区12均接触。
本例的工作原理为:
隔离槽(槽栅)在本实施例中的作用仍在于阻挡空穴被阴极抽取,进而提高了器件导通状态漂移区载流子的浓度。与实施例1和实施例2相比,该实施例中新增的平面栅进一步增加了电子的注入,漂移区载流子浓度大幅升高,导通压降在实施例1和实施例2的基础上又有大幅度的降低。
实施例4
如图4所示,本例与实施例3相比,N型阴极区12在器件的俯视图上呈“L”字形的镜像,P型体接触区11位于“L”字形的开口处,平面栅与N型阴极区12接触,不与P型体接触区11接触。图5为本实施例的俯视图。
本例的工作原理为:
本实施例与实施例4相比通过改变N型阴极区12的几何形状拓宽了平面栅的沟道宽度,沟道电流增大,电子注入效率提高,因此该实施例的导通压降相比实施例3进一步降低。
实施例5
如图6所示,本例与实施例4相比,隔离槽(槽栅)底部与介质层2接触。

Claims (5)

1.一种横向IGBT,包括从下至上依次层叠设置的衬底(1)、介质层(2)和SOI层(3);所述SOI层上层两端分别具有P型阱区(6)和N型阱区(4);所述N型阱区(4)表面远离P型阱区(6)的一端具有P型阳极区(5),由P型阳极区(5)引出阳极电极;所述P型阱区(6)表面具有相互独立的P型体接触区(11)和N型阴极区(12),所述N型阴极区(12)位于靠近N型阱区(4)的一侧;由P型体接触区(11)和N型阴极区(12)引出阴极电极;其特征在于,所述SOI层(3)中具有隔离槽(9),所述隔离槽(9)与N型阴极区(12)接触,隔离槽(9)深度大于P型阱区(6)的结深;隔离槽(9)沿器件纵向方向分为两段,两段隔离槽之间的间距为N。隔离槽(9)由位于槽内壁的介质层和由介质层包围的导电材料构成;由隔离槽(9)中的导电材料引出栅电极,形成槽栅结构,所述P型体接触区(11)和N型阴极区(12)均沿器件纵向方向分为两段,两段之间有间距,并沿器件的横向中线呈对称结构,两段P型体接触区(11)和N型阴极区(12)间距均为G,且满足G>N。
2.根据权利要求1所述的一种横向IGBT,其特征在于,沿器件纵向方向,所述P型阱区(6)分为两段,且两段P型阱区之间的间距为M;沿器件横向方向,两段P型阱区之间形成的开口与两段隔离槽之间形成的开口相对应,并且满足G>M>N。
3.根据权利要求2所述的一种横向IGBT,其特征在于,所述两段P型阱区除去P型体接触区(11)和N型阴极区(12)以外的表面形成平面栅结构并引出栅电极,平面栅与P型体接触区(11)和N型阴极区(12)均接触。
4.根据权利要求2所述的一种横向IGBT,其特征在于,沿器件纵向方向,所述N型阴极区(12)在器件的俯视图上呈“L”字形的镜像,P型体接触区(11)位于“L”字形的开口处;所述两段P型阱区除去P型体接触区(11)和N型阴极区(12)以外的表面形成平面栅结构并引出栅电极,平面栅与N型阴极区(12)接触,不与P型体接触区(11)接触。
5.根据权利要求1-4任意一项所述的一种横向IGBT,其特征在于,隔离槽(9)的下表面与介质层(2)的上表面连接。
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CN107170817B (zh) * 2017-06-16 2019-08-02 电子科技大学 一种横向igbt
CN117374108A (zh) * 2023-11-17 2024-01-09 湖南杰楚微半导体科技有限公司 一种soi ligbt器件及其制备方法
CN117374108B (zh) * 2023-11-17 2024-06-11 湖南杰楚微半导体科技有限公司 一种soi ligbt器件及其制备方法

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