CN107170803A - 鳍型场效晶体管 - Google Patents

鳍型场效晶体管 Download PDF

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CN107170803A
CN107170803A CN201611215791.5A CN201611215791A CN107170803A CN 107170803 A CN107170803 A CN 107170803A CN 201611215791 A CN201611215791 A CN 201611215791A CN 107170803 A CN107170803 A CN 107170803A
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fin
recess
semiconductor fin
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ridge portion
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CN107170803B (zh
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张哲诚
林志翰
曾鸿辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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Abstract

一种鳍型场效晶体管，包括栅极堆叠结构、嵌于所述栅极堆叠结构中的半导体鳍、源极及漏极。所述半导体鳍沿所述栅极堆叠结构的宽度方向延伸且具有分别在所述栅极堆叠结构的侧壁处暴露出的第一凹部及第二凹部。所述源极及漏极配置于所述栅极堆叠结构的两个相对侧。所述源极包括嵌于所述第一凹部中的第一凸脊部分，且所述漏极包括嵌于所述第二凹部中的第二凸脊部分，其中所述第一凸脊部分及所述第二凸脊部分沿所述半导体鳍的高度方向延伸。

Description

鳍型场效晶体管
技术领域
本发明的实施例涉及一种鳍型场效晶体管。
背景技术
随着半导体装置的大小不断按比例缩减，已开发出三维多栅极结构(例如鳍型场效晶体管(fin-type field effect transistor，FinFET))以取代平面的互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)装置。鳍型场效晶体管的结构性特征为从衬底的表面直立延伸的硅系鳍，且包绕于由所述鳍形成的导电沟道周围的栅极进一步提供对所述沟道的更好的电性控制。
目前，用于鳍型场效晶体管的外延源极及漏极是在鳍凹陷工艺之后形成。外延应变源极及漏极需要嵌于栅极堆叠结构中，以增强鳍型场效晶体管的装置升压(deviceboost)。在形成针对成长外延源极及漏极而形成的鳍凹陷期间，所述鳍凹陷的横向尺寸及深度同时增加。然而，当所述鳍凹陷的深度增加时，可能出现子鳍泄漏路径(sub-finleakage path)。
发明内容
本发明的实施例提出一种鳍型场效晶体管，包括栅极堆叠结构、嵌于所述栅极堆叠结构中的半导体鳍、源极及漏极。所述半导体鳍沿所述栅极堆叠结构的宽度方向延伸且具有分别在所述栅极堆叠结构的侧壁处暴露出的第一凹部及第二凹部。所述源极及漏极配置于所述栅极堆叠结构的两个相对侧。所述源极包括嵌于所述第一凹部中的第一凸脊部分，且所述漏极包括嵌于所述第二凹部中的第二凸脊部分，其中所述第一凸脊部分及所述第二凸脊部分沿所述半导体鳍的高度方向延伸。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1A至图1H是根据某些实施例的半导体装置的p型鳍型场效晶体管的制作方法的立体图。
图2A至图2H是根据某些实施例的半导体装置的n型鳍型场效晶体管的制作方法的立体图。
图3A是图1H中的p型鳍型场效晶体管的剖视图。
图3B是图2H中的n型鳍型场效晶体管的剖视图。
[符号的说明]
100：衬底
100a：图案化衬底
102a：垫层
102a’：图案化垫层
102b：掩模层
102b’：图案化掩模层
104：图案化光刻胶层
106：沟槽
108a：第一半导体鳍
108a’：半导体鳍
108b：第二半导体鳍
108b’：半导体鳍
110：绝缘材料
110’：经抛光的绝缘材料
110a：绝缘体
112a：第一栅极介电层
112b：第二栅极介电层
116a：第一间隔壁
116b：第二间隔壁
120：第一栅极
120a：第一功函数金属
120b：第一主金属
122：第二栅极
122a：第二功函数金属
122b：第二主金属
124a：第一介电顶盖
124b：第二介电顶盖
C1：第一凹部
C2：第二凹部
C3：第三凹部
C4：第四凹部
D1：第一漏极
D2：第二漏极
DR1、DR2：长度方向
GS1：第一栅极堆叠结构
GS2：第二栅极堆叠结构
M1：第一主部分
M2：第二主部分
MS1、MS2：第一主表面
MS3、MS4：第二主表面
R1：第一凸脊部分
R2：第二凸脊部分
R3：第一圆弧突出部分
R4：第二圆弧突出部分/圆弧突出部分
RL1：第一凸脊线
RL2：第二凸脊线
S1：第一源极
S2：第二源极
SW1、SW2：侧壁
T1、T2、T3、T4：顶表面
TH1、TH2：最大厚度
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开内容。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第一特征形成于第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复参考编号及/或字母。这种重复是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对性描述语可同样相应地进行解释。
本发明的实施例阐述鳍型场效晶体管的示例性制作工艺。在本发明的某些实施例中可在块状硅(bulk silicon)衬底上形成鳍型场效晶体管。再者，作为替代形式，可在绝缘体上硅(silicon-on-insulator，SOI)衬底或绝缘体上锗(germanium-on-insulator，GOI)衬底上形成鳍型场效晶体管。此外，根据实施例，所述硅衬底可包括其他导电层或其他半导体元件(例如晶体管、二极管等)。所述实施例在本上下文中不受限制。
图1A至图1H是根据某些实施例的半导体装置的p型鳍型场效晶体管的制作方法的立体图，且图2A至图2H是根据某些实施例的半导体装置的n型鳍型场效晶体管的制作方法的立体图。
参照图1A及图2A，提供衬底100。在某些实施例中，衬底100包括晶体硅衬底(例如，晶片)。根据设计要求，衬底100可包括n型掺杂区及p型掺杂区。图1A中所示的衬底100的部分被掺杂以p型掺杂剂，而图2A中所示的衬底100的部分被掺杂以n型掺杂剂。举例来说，所述p型掺杂剂可为硼或BF2或者其组合，而所述n型掺杂剂可为磷、砷或其组合。在某些实施例中，包括n型掺杂区及p型掺杂区的衬底100可为n型衬底或p型衬底，所述n型衬底具有形成于其中的p型掺杂区(例如，p井)，所述p型衬底具有形成于其中的n型掺杂区(例如，n井)。在某些替代实施例中，包括n型掺杂区及p型掺杂区的衬底100可由下列制成：其他合适的元素半导体，例如金刚石或锗；合适的化合物半导体，例如砷化镓、碳化硅、砷化铟或磷化铟；或者合适的合金半导体，例如碳化硅锗、磷化镓砷或磷化镓铟。
在某些实施例中，在衬底100的p型掺杂区(在图1A中示出)及n型掺杂区(在图2A中示出)上依序形成垫层102a及掩模层102b。垫层102a可为例如由热氧化(thermaloxidation)工艺形成的氧化硅薄膜。垫层102a可作为衬底100与掩模层102b之间的粘着层。垫层102a也可作为刻蚀掩模层102b的刻蚀终止层。举例来说，掩模层102b是通过低压化学气相沉积(low-pressure chemical vapor deposition，LPCVD)或等离子体增强型化学气相沉积(plasma enhanced chemical vapor deposition，PECVD)而形成的氮化硅层。掩模层102b在后续光刻(photolithography)工艺期间被用作硬掩模。接着，在掩模层102b上形成具有预定图案的图案化光刻胶层104。
参照图1A至图1B以及图2A至图2B，依序刻蚀未被图案化光刻胶层104覆盖的掩模层102b及垫层102a，以形成图案化掩模层102b’及图案化垫层102a’，从而暴露出下面的衬底100。利用图案化掩模层102b’、图案化垫层102a’及图案化光刻胶层104作为掩模，将衬底100图案化以形成图案化衬底100a。刻蚀衬底100被图案化掩模层102b’、图案化垫层102a’及图案化光刻胶层104暴露出的部分，以形成沟槽106、形成于p型区(在图1B中示出)中的至少一个第一半导体鳍108a及形成于n型区(在图2B中示出)中的至少一个第二半导体鳍108b。第一半导体鳍108a是p型半导体鳍，且第二半导体鳍108b是n型半导体鳍。图1B中所示的第一半导体鳍108a的数目以及图2B中所示的第二半导体鳍108b的数目仅用于说明，在某些替代实施例中，根据实际设计要求，可形成两个或更多个第一半导体鳍108a及第二半导体鳍108b。在将衬底100图案化之后，第一半导体鳍108a及第二半导体鳍108b被图案化掩模层102b’、图案化垫层102a’及图案化光刻胶层104覆盖。形成于衬底100的p型区(在图1B中示出)中的两个邻近的沟槽106通过第一半导体鳍108a彼此间隔开，且形成于衬底100的n型区(在图2B中示出)中的两个邻近的沟槽106通过第二半导体鳍108b彼此间隔开。
第一半导体鳍108a的高度、第二半导体鳍108b的高度及沟槽106的深度介于约5nm至约500nm的范围内。在形成第一半导体鳍108a、第二半导体鳍108b及沟槽106之后，接着移除图案化光刻胶层104。在一个实施例中，可进行清洗(cleaning)工艺来移除图案化衬底100a的天然氧化物。可利用经稀释的氢氟(diluted hydrofluoric，DHF)酸或其他合适的清洗溶液来进行所述清洗工艺。
参照图1B至图1C及图2B至图2C，在图案化衬底100a之上形成绝缘材料110，以覆盖形成于p型区(在图1C中示出)中的第一半导体鳍108a及形成于n型区(在图2C中示出)中的第二半导体鳍108b。此外，绝缘材料110填充沟槽106。除第一半导体鳍108a及第二半导体鳍108b之外，绝缘材料110进一步覆盖图案化垫层102a’及图案化掩模层102b’。举例来说，绝缘材料110包括氧化硅、氮化硅、氮氧化硅、旋涂(spin-on)介电材料或低介电常数的介电材料。可通过高密度等离子体化学气相沉积(high-density-plasma chemical vapordeposition，HDP-CVD)、次大气压化学气相沉积(sub-atmospheric CVD，SACVD)或旋涂来形成绝缘材料110。
参照图1C至图1D及图2C至图2D，举例来说，进行化学机械抛光工艺来移除绝缘材料110的一部分、图案化掩模层102b’及图案化垫层102a’，直至暴露出第一半导体鳍108a的顶表面T1及第二半导体鳍108b的顶表面T2为止。如图1D及图2D中所示，在对绝缘材料110进行抛光之后，形成经抛光的绝缘材料110’，且经抛光的绝缘材料110’的顶表面T3与第一半导体鳍108a的顶表面T1及第二半导体鳍108b的顶表面T2实质上共平面。
参照图1D至图1E及图2D至图2E，通过刻蚀工艺局部地移除经抛光的绝缘材料110’，进而在图案化衬底100a上形成绝缘体110a，且每一绝缘体110a对应地位于其中一个沟槽106中。在某些实施例中，所述刻蚀工艺可为使用氢氟酸(hydrofluoric acid，HF)的湿刻蚀(wet etching)工艺或干刻蚀(dry etching)工艺。绝缘体110a的顶表面T4低于第一半导体鳍108a的顶表面T1及第二半导体鳍108b的顶表面T2。换句话说，第一半导体鳍108a及第二半导体鳍108b从绝缘体110a的顶表面T4突出，且因此暴露出第一半导体鳍108a的侧壁SW1及第二半导体鳍108b的侧壁SW2。
参照图1E至图1F及图2E至图2F，在形成绝缘体110a之后，形成第一栅极堆叠结构GS1及第二栅极堆叠结构GS2，以分别局部地覆盖第一半导体鳍108a及第二半导体鳍108b。换句话说，第一半导体鳍108a的部分及第二半导体鳍108b的部分以及绝缘体110a的部分会被暴露出。
在某些实施例中，第一栅极堆叠结构GS1包括第一栅极120、第一栅极介电层112a及一对第一间隔壁116a，而第二栅极堆叠结构GS2包括第二栅极122、第二栅极介电层112b及一对第二间隔壁116b。第一栅极120配置于第一栅极介电层112a之上。第一栅极介电层112a局部地覆盖第一半导体鳍108a且夹于第一半导体鳍108a与第一栅极120之间。所述第一间隔壁116a配置于第一栅极介电层112a之上且沿第一栅极120的侧壁延伸。第二栅极122配置于第二栅极介电层112b之上。第二栅极介电层112b局部地覆盖第二半导体鳍108b且夹于第二半导体鳍108b与第二栅极122之间。所述第二间隔壁116b配置于第二栅极介电层112b之上且沿第二栅极122的侧壁延伸。
在某些替代实施例中，第一栅极堆叠结构GS1可进一步包括形成于所述第一间隔壁116a之间的第一介电顶盖124a，且第二栅极堆叠结构GS2可进一步包括形成于所述第二间隔壁116b之间的第二介电顶盖124b。形成于所述第一间隔壁116a之间的第一介电顶盖124a覆盖第一栅极120，且形成于所述第二间隔壁116b之间的第二介电顶盖124b覆盖第二栅极122。如图1F及图2F中所示，第一介电顶盖124a的最大厚度TH1小于第二介电顶盖124b的最大厚度TH2。
在某些实施例中，举例来说，第一栅极介电层112a与第二栅极介电层112b是由相同的介电材料制成。第一栅极介电层112a及第二栅极介电层112b可包含氧化硅、氮化硅、氮氧化硅或高介电常数的介电质。高介电常数的介电质包括金属氧化物。用于高介电常数的介电质的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物及/或其混合物。在一个实施例中，栅极介电层112是厚度在约0.2nm至50nm范围内的高介电常数介电层。可通过例如原子层沉积(atomic layerdeposition，ALD)、化学气相沉积(chemical vapor deposition，CVD)、物理气相沉积(physical vapor deposition，PVD)、热氧化或紫外臭氧氧化(UV-ozone oxidation)等合适的工艺来形成第一栅极介电层112a及第二栅极介电层112b。
在某些实施例中，所述第一间隔壁116a及所述第二间隔壁116b是由例如氮化硅或SiCON等相同的介电材料形成。举例来说，所述第一间隔壁116a及所述第二间隔壁116b可包括单层结构或多层结构。
第一栅极120及第二栅极122的长度方向DR1不同于第一半导体鳍108a及第二半导体鳍108b的长度方向DR2。在某些实施例中，第一栅极120及第二栅极122的长度方向DR1垂直于第一半导体鳍108a及第二半导体鳍108b的长度方向DR2。图1F及图2F中所示的第一栅极120及第二栅极122的数目仅用于说明，在某些替代实施例中，可根据实际设计要求形成更多的栅极堆叠结构。
为了与第一半导体鳍108a的特性及第二半导体鳍108b的特性匹配，且为了降低p型鳍型场效晶体管及n型鳍型场效晶体管的阈值电压(threshold voltage)，第一栅极120的功函数大于第二栅极122的功函数。第一栅极120包含配置于栅极介电层112上的第一功函数金属120a及嵌于第一功函数金属120a中的第一主金属120b。第二栅极122包含配置于栅极介电层112上的第二功函数金属122a及嵌于第二功函数金属122a中的第二主金属122b。
在某些实施例中，可通过以下步骤形成第一栅极120：依序沉积第一功函数金属层及第一主金属层；局部地对所述第一功函数金属层及所述第一主金属层进行抛光；以及通过刻蚀工艺局部地移除所述第一功函数金属层及所述第一主金属层，以形成第一栅极120及位于所述第一间隔壁116a之间的第一栅极凹陷。第一介电顶盖124a填充所述第一栅极凹陷并覆盖第一栅极120。举例来说，通过Ar、O2、N2、He、SO2、Cl2、SiCl4、SF6、BCl3、NF3、HBr、CH4、CF4、CHF3、CH2F2、CH3F、C4F8、CxHyFz(x>0，y>0，z>0)或其组合对所述第一功函数金属层及所述第一主金属层进行回蚀(back-etch)。如图1F中所示，由于刻蚀选择性，与所述第一主金属层相比，对所述第一功函数金属层的刻蚀更为高效，所以第一主金属120b会从第一功函数金属120a的顶表面突出。
相似地，可通过以下步骤形成第二栅极122：依序沉积第二功函数金属层及第二主金属层；局部地对所述第二功函数金属层及所述第二主金属层进行抛光；以及通过另一刻蚀工艺局部地移除所述第二功函数金属层及所述第二主金属层，以形成第二栅极122及位于所述第二间隔壁116b之间的第二栅极凹陷。第二介电顶盖124b填充所述第二栅极凹陷并覆盖第二栅极122。举例来说，通过Ar、O2、N2、He、SO2、Cl2、SiCl4、SF6、BCl3、NF3、HBr、CH4、CF4、CHF3、CH2F2、CH3F、C4F8、CxHyFz(x>0，y>0，z>0)或其组合对所述第二功函数金属层及所述第二主金属层进行回蚀。如图2F中所示，由于刻蚀选择性，与所述第二主金属层相比，对所述第二功函数金属层的刻蚀更为高效，所以第二主金属122b会从第二功函数金属122a的顶表面突出。
在某些实施例中，第一栅极120的第一主金属120b及第二栅极122的第二主金属122b可由相同的材料制成且具有相同的功函数；并且第一功函数金属120a的功函数可大于第二功函数金属122a的功函数。举例来说，第一功函数金属120a的功函数可大于第一主金属120b的功函数，而第二功函数金属122a的功函数可小于第二主金属122b的功函数。在某些实施例中，具有较高的功函数(例如，5.5eV)的第一功函数金属120a可包括钽(Ta)、氮化钽(TaN)、氮化钛(TiN)或其组合，且具有较低的功函数(例如，4eV)的第二功函数金属122a可包括钽(Ta)、氮化钽(TaN)、氮化钛(TiN)或其组合；并且第一主金属120b及第二主金属122b包括钨(W)等。举例来说，第一主金属120b及第二主金属122b的功函数可为4.5eV。
参照图1F至图1G、图2F至图2G、图3A及图3B，在形成第一栅极堆叠结构GS1及第二栅极堆叠结构GS2之后，对第一半导体鳍108a进行第一鳍凹陷工艺(fin-recessingprocess)，以局部地移除第一半导体鳍108a的未被第一栅极堆叠结构GS1覆盖的部分。在进行所述第一鳍凹陷工艺之后，在某些实施例中，如图1G中所示，通过刻蚀工艺将第一半导体鳍108a进一步图案化以形成p型的半导体鳍108a’。第一鳍凹陷工艺的刻蚀配方(recipe)如下。刻蚀剂包括N2、O2、He、Ar、CH4、CF4、HBr、CH3F、CHF3、BCl3、Cl2、NF3、SO2、SF6、SiCl4或其组合；功率在100W至1500W的范围内；工艺温度在10摄氏度至80摄氏度的范围内；且压力在1mtorr至75mtorr的范围内。在某些实施例中，进行多个刻蚀步骤来控制p型的半导体鳍108a’的轮廓。
如图1G及图3A中所示，半导体鳍108a’沿第一栅极堆叠结构GS1的宽度方向(即，长度方向DR2)延伸且具有分别在第一栅极堆叠结构GS1的侧壁处暴露出的第一凹部C1及第二凹部C2。在某些实施例中，举例来说，第一凹部C1及第二凹部C2是V形凹部。换句话说，第一凹部C1及第二凹部C2是具有V形底表面的凹部。
在形成第一栅极堆叠结构GS1及第二栅极堆叠结构GS2之后，对第二半导体鳍108b进行第二鳍凹陷工艺，以局部地移除第二半导体鳍108b的未被第二栅极堆叠结构GS2覆盖的部分。在进行所述第二鳍凹陷工艺之后，在某些实施例中，如图2G中所示，通过刻蚀工艺将第二半导体鳍108b进一步图案化而形成n型的半导体鳍108b’。第二鳍凹陷工艺的刻蚀配方如下：刻蚀剂包括N2、O2、He、Ar、CH4、CF4、HBr、CH3F、CHF3、BCl3、Cl2、NF3、SO2、SF6、SiCl4或其组合；功率在100W至1500W的范围内；工艺温度在10摄氏度至80摄氏度的范围内；且压力在1mtorr至75mtorr的范围内。
如图2G及图3B中所示，半导体鳍108b’沿第二栅极堆叠结构GS2的宽度方向(即，长度方向DR2)延伸且具有分别在第二栅极堆叠结构GS2的侧壁处暴露出的第三凹部C3及第四凹部C4。在某些实施例中，举例来说，第三凹部C3及第四凹部C4是具有圆弧底表面的凹部。
应注意，上述第一鳍凹陷工艺及第二鳍凹陷工艺的顺序不受限制。在某些实施例中，可在第二鳍凹陷工艺之前进行第一鳍凹陷工艺。举例来说，第二半导体鳍108b在第一鳍凹陷工艺(即，半导体鳍108a’的形成)期间受到图案化光刻胶的保护，且所形成的半导体鳍108a’在第二鳍凹陷工艺(即，半导体鳍108b’的形成)期间受到另一图案化光刻胶的保护。在某些替代实施例中，可在第二鳍凹陷工艺之后进行第一鳍凹陷工艺。举例来说，第一半导体鳍108a在第二鳍凹陷工艺(即，半导体鳍108b’的形成)期间受到图案化光刻胶的保护，且所形成的半导体鳍108b’在第一鳍凹陷工艺(即，半导体鳍108a’的形成)期间受到另一图案化光刻胶的保护。
参照图1G至图1H、图2G至图2H、图3A及图3B，在进行第一鳍凹陷工艺及第二鳍凹陷工艺之后，在第一栅极堆叠结构GS1的两个相对侧形成第一源极S1及第一漏极D1，而在第二栅极堆叠结构GS2的两个相对侧形成第二源极S2及第二漏极D2。在某些实施例中，通过外延工艺形成第一源极S1、第一漏极D1、第二源极S2及第二漏极D2。举例来说，第一源极S1及第一漏极D1从半导体鳍108a’选择性地成长，而第二源极S2及第二漏极D2从半导体鳍108b’选择性地成长。
举例来说，第一源极S1及第一漏极D1的材料可为通过低压化学气相沉积工艺进行外延成长的硅锗(SiGe)，而第二源极S2及第二漏极D2的材料可为通过低压化学气相沉积工艺进行外延成长的碳化硅(SiC)。通过第一源极S1及第一漏极D1对被第一栅极堆叠结构GS1覆盖的半导体鳍108a’进行应变或对被第一栅极堆叠结构GS1覆盖的半导体鳍108a’施加应力，以增强p型鳍型场效晶体管的载流子迁移率及性能。通过第二源极S2及第二漏极D2对被第二栅极堆叠结构GS2覆盖的半导体鳍108b’进行应变或对被第二栅极堆叠结构GS2覆盖的半导体鳍108b’施加应力，以增强n型鳍型场效晶体管的载流子迁移率及性能。
如图1H及图3A中所示，第一源极S1包括第一主部分M1及从第一主部分M1突出的第一凸脊部分R1，其中第一凸脊部分R1嵌于第一凹部C1中且第一主部分M1分布于第一凹部C1的外部。第一漏极D1包括第二主部分M2及从第二主部分M2突出的第二凸脊部分R2，其中第二凸脊部分R2嵌于第二凹部C2中且第二主部分M2分布于第二凹部C2的外部。第一凸脊部分R1及第二凸脊部分R2沿半导体鳍108a’的高度方向延伸。在某些实施例中，半导体鳍108a’的第一凹部C1及栅极介电层112a具有用于容置并接触第一凸脊部分R1的V形槽，且半导体鳍108a’的第二凹部C2及栅极介电层112a具有用于容置并接触第二凸脊部分R2的另一V形槽。
第一源极S1的第一凸脊部分R1包括在第一凸脊部分R1的第一凸脊线RL1处互连的两个第一主表面MS1、MS2。第一漏极D1的第二凸脊部分R2包括在第二凸脊部分R2的第二凸脊线RL2处互连的两个第二主表面MS3、MS4。第一主表面MS1、MS2连接至或接触半导体鳍108a’的第一凹部C1且第二主表面MS3、MS4连接至半导体鳍108a’的第二凹部C2。此外，举例来说，第一主表面MS1、MS2之间的夹角及第二主表面MS3、MS4之间的夹角小于90度。
在某些实施例中，第一凸脊线RL1及第二凸脊线RL2沿半导体鳍108a’的高度方向延伸并指向半导体鳍108a’。此外，第一凸脊线RL1及第二凸脊线RL2接触半导体鳍108a’。
如图2H及图3B中所示，第二源极S2包括嵌于第三凹部C3中的第一圆弧突出部分R3且第二漏极D2包括嵌于第四凹部C4中的第二圆弧突出部分R4。第一圆弧突出部分R3及第二圆弧突出部分R4沿半导体鳍108b’的高度方向延伸。在某些实施例中，半导体鳍108b’的第三凹部C3及栅极介电层112b具有用于容置第一圆弧突出部分R3的圆弧槽，且半导体鳍108b’的第四凹部C4及栅极介电层112b具有用于容置圆弧突出部分R4的另一圆弧槽。
参照图3A及图3B，由于第一凹部C1及第二凹部C2是通过相同的刻蚀工艺而形成，因此第一凹部C1与第二凹部C2的深度相同。相似地，由于第三凹部C3及第四凹部C4是通过相同的刻蚀工艺而形成，因此第三凹部C3与第四凹部C4的深度相同。应注意，第一凹部C1的深度及第二凹部C2的深度大于第三凹部C3的深度及第四凹部C4的深度。换句话说，第一凸脊部分R1的轮廓及第二凸脊部分R2的轮廓比第一圆弧突出部分R3的轮廓及第二圆弧突出部分R4的轮廓尖锐。因此，包括半导体鳍108b’的鳍型场效晶体管的装置升压得到增强。
在包括至少一个n型鳍型场效晶体管及至少一个p型鳍型场效晶体管的上述半导体装置中，良率(yield rate)及可靠性可得到增强。
根据本发明的某些实施例，提供一种鳍型场效晶体管，所述鳍型场效晶体管包括栅极堆叠结构、嵌于所述栅极堆叠结构中的半导体鳍、源极及漏极。所述半导体鳍沿所述栅极堆叠结构的宽度方向延伸且具有分别在所述栅极堆叠结构的侧壁处暴露出的第一凹部及第二凹部。所述源极及漏极配置于所述栅极堆叠结构的两个相对侧。所述源极包括嵌于所述第一凹部中的第一凸脊部分且所述漏极包括嵌于所述第二凹部中的第二凸脊部分，其中所述第一凸脊部分及所述第二凸脊部分沿所述半导体鳍的高度方向延伸。
在所述的鳍型场效晶体管中，所述栅极堆叠结构包括：栅极；栅极介电层；以及一对间隔壁，配置于所述栅极的侧壁上，所述半导体鳍嵌于所述栅极及所述一对间隔壁中，所述栅极介电层位于所述半导体鳍与所述一对间隔壁之间以及所述半导体鳍与所述栅极之间。
在所述的鳍型场效晶体管中，所述半导体鳍的所述第一凹部及所述栅极介电层具有用于容置所述第一凸脊部分的第一V形槽，且所述半导体鳍的所述第二凹部及所述栅极介电层具有用于容置所述第二凸脊部分的第二V形槽。
在所述的鳍型场效晶体管中，所述第一凸脊部分包括在所述第一凸脊部分的第一凸脊线处互连的两个第一主表面，所述第二凸脊部分包括在所述第二凸脊部分的第二凸脊线处互连的两个第二主表面，所述第一主表面连接至所述半导体鳍的所述第一凹部，且所述第二主表面连接至所述半导体鳍的所述第二凹部。
在所述的鳍型场效晶体管中，所述第一凸脊线及所述第二凸脊线沿所述半导体鳍的高度方向延伸。
在所述的鳍型场效晶体管中，所述第一凸脊线及所述第二凸脊线接触所述半导体鳍。
在所述的鳍型场效晶体管中，所述第一主表面之间的夹角及所述第二主表面之间的夹角小于90度。
根据本发明的替代实施例，提供一种鳍型场效晶体管，所述鳍型场效晶体管包括栅极堆叠结构、嵌于所述栅极堆叠结构中的半导体鳍、源极及漏极。所述半导体鳍沿所述栅极堆叠结构的宽度方向延伸且具有分别在所述栅极堆叠结构的侧壁处暴露出的第一V形凹部及第二V形凹部。所述源极及漏极配置于所述栅极堆叠结构的两个相对侧。所述源极包括第一主部分及从所述第一主部分突出的第一凸脊部分，且所述漏极包括第二主部分及从所述第二主部分突出的第二凸脊部分。所述第一凸脊部分及所述第二凸脊部分分别嵌于所述第一V形凹部及所述第二V形凹部中，其中所述第一凸脊部分及所述第二凸脊部分沿所述半导体鳍的高度方向延伸。
在所述的鳍型场效晶体管中，所述第一主部分及所述第二主部分分布于所述第一V形凹部及所述第二V形凹部的外部。
在所述的鳍型场效晶体管中，所述第一凸脊部分包括在所述第一凸脊部分的第一凸脊线处互连的两个第一主表面，所述第二凸脊部分包括在所述第二凸脊部分的第二凸脊线处互连的两个第二主表面，所述第一主表面连接至所述半导体鳍的所述第一V形凹部，且所述第二主表面连接至所述半导体鳍的所述第二V形凹部。
在所述的鳍型场效晶体管中，所述第一凸脊线及所述第二凸脊线沿所述半导体鳍的高度方向延伸。
在所述的鳍型场效晶体管中，所述第一凸脊线及所述第二凸脊线接触所述半导体鳍。
在所述的鳍型场效晶体管中，所述第一主表面之间的夹角及所述第二主表面之间的夹角小于90度。
根据本发明的又一些替代实施例，提供一种半导体装置，所述半导体装置包括第一鳍型场效晶体管及第二鳍型场效晶体管。所述第一鳍型场效晶体管包括第一栅极堆叠结构、嵌于所述第一栅极堆叠结构中的第一半导体鳍、第一源极及第一漏极。所述第一半导体鳍沿所述第一栅极堆叠结构的宽度方向延伸且具有分别在所述第一栅极堆叠结构的侧壁处暴露出的第一凹部及第二凹部。所述第一源极及所述第一漏极配置于所述第一栅极堆叠结构的两个相对侧。所述第一源极包括嵌于所述第一凹部中的第一凸脊部分且所述第一漏极包括嵌于所述第二凹部中的第二凸脊部分。所述第一凸脊部分及所述第二凸脊部分沿所述第一半导体鳍的高度方向延伸。所述第二鳍型场效晶体管包括第二栅极堆叠结构、嵌于所述第二栅极堆叠结构中的第二半导体鳍、第二源极及第二漏极。所述第二半导体鳍沿所述第二栅极堆叠结构的宽度方向延伸且具有分别在所述第二栅极堆叠结构的侧壁处暴露出的第三凹部及第四凹部。所述第二源极及所述第二漏极配置于所述第二栅极堆叠结构的两个相对侧。所述第二源极包括嵌于所述第三凹部中的第一圆弧突出部分且所述第二漏极包括嵌于所述第四凹部中的第二圆弧突出部分。所述第一圆弧突出部分及所述第二圆弧突出部分沿所述第二半导体鳍的高度方向延伸。
在所述的半导体装置中，所述第一凸脊部分包括在所述第一凸脊部分的第一凸脊线处互连的两个第一主表面，所述第二凸脊部分包括在所述第二凸脊部分的第二凸脊线处互连的两个第二主表面，所述第一主表面连接至所述半导体鳍的所述第一凹部，且所述第二主表面连接至所述半导体鳍的所述第二凹部。
在所述的半导体装置中，所述第一凸脊线及所述第二凸脊线沿所述半导体鳍的高度方向延伸。
在所述的半导体装置中，所述第一凸脊线及所述第二凸脊线接触所述半导体鳍。
在所述的半导体装置中，所述第一主表面之间的夹角及所述第二主表面之间的夹角小于90度。
在所述的半导体装置中，所述第一凹部的深度及所述第二凹部的深度大于所述第三凹部的深度及所述第四凹部的深度。
在所述的半导体装置中，所述第一凸脊部分的轮廓及所述第二凸脊部分的轮廓比所述第一圆弧突出部分的轮廓及所述第二圆弧突出部分的轮廓尖锐。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知，他们可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (1)

1.一种鳍型场效晶体管，其特征在于，包括：
栅极堆叠结构；
半导体鳍，嵌于所述栅极堆叠结构中，所述半导体鳍沿所述栅极堆叠结构的宽度方向延伸且具有分别在所述栅极堆叠结构的侧壁处暴露出的第一凹部及第二凹部；以及
源极及漏极，配置于所述栅极堆叠结构的两个相对侧，所述源极包括嵌于所述第一凹部中的第一凸脊部分，且所述漏极包括嵌于所述第二凹部中的第二凸脊部分，其中所述第一凸脊部分及所述第二凸脊部分沿所述半导体鳍的高度方向延伸。
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