CN107121889B

CN107121889B - Optical proximity correction verification method, method of designing layout of stacked memory device, and stacked memory device manufacturing method

Info

Publication number: CN107121889B
Application number: CN201710075831.9A
Authority: CN
Inventors: 金昶汎; 金成勋; 金祐呈; 粱香子
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2016-02-25
Filing date: 2017-02-13
Publication date: 2021-12-28
Anticipated expiration: 2037-02-13
Also published as: KR20170100354A; KR102417183B1; CN107121889A; US10170495B2; US20170250195A1

Abstract

An Optical Proximity Correction (OPC) inspection method includes: checking a first position of a first pattern in a layout of a stacked memory device; calculating an offset value of the first pattern according to the first position; obtaining a difference between the first position and a second position of a second pattern formed by OPC for the first pattern; and determining whether the OPC is to be performed again based on the offset value and the difference value.

Description

Optical proximity correction verification method, method of designing layout of stacked memory device, and stacked memory device manufacturing method

Technical Field

The present disclosure relates to memory devices. More particularly, the present disclosure relates to stacked memory devices, Optical Proximity Correction (OPC) verification methods, methods of designing layouts of memory devices, and methods of manufacturing stacked memory devices.

Background

Memory devices are used to store data and are classified into volatile memory devices and nonvolatile memory devices. As an example of the nonvolatile memory device, a flash memory device may be used in a mobile phone, a digital camera, a Portable Digital Assistant (PDA), a portable computer device, a stationary computer device, and other devices. Due to the need for small, high-capacity nonvolatile memory devices, stacked memory devices have been developed. The stacked memory device refers to a memory device including a plurality of memory cells or a memory cell array vertically stacked on a substrate. The peripheral circuit region of the stacked memory device may be affected by a process of forming the memory cell array. As a result, the semiconductor chip implementing the stacked memory device may fail.

Disclosure of Invention

According to an aspect of the present disclosure, an Optical Proximity Correction (OPC) inspection method includes checking a first position of a first pattern in a layout of a stacked memory device. The OPC inspection method further includes calculating an offset value of the first pattern according to the first position. The OPC inspection method further includes obtaining a difference between the first position and a second position of a second pattern formed by OPC with respect to the first pattern. The OPC verifying method further includes determining whether OPC is to be performed again based on the offset value and the difference value.

According to another aspect of the present disclosure, a method of designing a layout of a stacked memory device includes checking a first position of a first pattern in an initial layout of the stacked memory device. The OPC inspection method further includes calculating an offset value of the first pattern according to the first position. The method also includes obtaining a difference between the first position and a second position of a second pattern formed with respect to the first pattern by a first Optical Proximity Correction (OPC). The method further includes determining whether to perform the second OPC based on the offset value and the difference value. A final layout of the stacked memory device is generated based on the second pattern or a third pattern formed by the second OPC.

According to another aspect of the present disclosure, a method of fabricating a stacked memory device includes designing a layout of the stacked memory device. The method also includes calculating an offset value for the first pattern based on a first position of the first pattern in the layout. The method also includes obtaining a difference between the first location and a second location of a second pattern formed by the first OPC with respect to the first pattern. The method further includes determining whether a second OPC is to be performed based on the offset value and the difference value. A mask is formed based on the second pattern or a third pattern formed by the second OPC. The stacked memory device is formed by a photolithography process using the mask.

According to another aspect of the present disclosure, a stacked memory device includes a memory cell array including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate. The stacked memory device further includes a peripheral circuit arranged adjacent to the memory cell array in the first direction. The peripheral circuitry includes a plurality of transistors electrically connected to the memory cell array. The positions of the contacts respectively connected to the first transistors among the transistors in the first direction are substantially the same. The first transistor is spaced apart from the memory cell array by the same distance.

According to another aspect of the present disclosure, a stacked memory device includes a memory cell array including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate. The stacked memory device further includes a peripheral circuit arranged adjacent to the memory cell array in the first direction. The peripheral circuit includes a transistor electrically connected to the first region of the memory cell array and a transistor electrically connected to the second region of the memory cell array. First positions in the first direction of first contacts respectively connected to first transistors among the transistors electrically connected to the first region are substantially the same. The first transistor is spaced apart from the memory cell array by the same distance. Second positions in the first direction of second contacts respectively connected to second transistors among the transistors electrically connected to the second region are substantially the same. The second transistors are spaced apart from the memory cell array by the same distance. The distance from the memory cell array to the first transistor is the same as the distance from the memory cell array to the second transistor. The first position and the second position are different.

According to another aspect of the present disclosure, a stacked memory device includes a memory cell array including a plurality of memory cells respectively connected to a plurality of word lines vertically stacked on a substrate. The stacked memory device further includes a peripheral circuit arranged adjacent to the memory cell array in the first direction. The peripheral circuitry includes a plurality of transistors electrically connected to the memory cell array. The positions of the contacts respectively connected to the first transistors among the plurality of transistors along the second direction are substantially the same. The first transistors are located at the same position along the second direction. The second direction is substantially perpendicular to the first direction.

Drawings

Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a flow chart of a method of manufacturing a stacked memory device according to an embodiment;

FIG. 2 is a layout of a stacked memory device according to an embodiment;

FIG. 3 illustrates an array of memory cells according to an embodiment;

fig. 4 is a circuit diagram of an equivalent circuit of a first memory block, which is one of the memory blocks included in the memory cell array of fig. 3;

FIG. 5 is a perspective view of the first memory block of FIG. 4;

fig. 6A to 6F are sectional views illustrating an example of a method of manufacturing a stacked memory device according to an embodiment;

fig. 7 is a graph showing offset values according to areas in the peripheral circuit area included in the stacked memory device of fig. 2;

fig. 8 is a graph showing an offset value according to a position in the X direction in the first region of the peripheral circuit region PA included in the stacked memory device of fig. 2;

FIG. 9 is a flow chart of an Optical Proximity Correction (OPC) verification method for stacked memory devices according to an embodiment;

fig. 10 is a view illustrating an operation of checking a position of a pattern in a layout of a stacked memory device according to an embodiment;

FIG. 11 is a sectional view taken along line XI-XI' of FIG. 10;

FIG. 12 is an initial layout for the peripheral circuit region of FIG. 11;

FIG. 13 illustrates a pattern offset value calculation operation for a first corrected pattern of the first pattern of FIG. 12, in accordance with an embodiment;

14A through 14D illustrate various embodiments of the first pattern of FIG. 12 and a second pattern formed by OPC with respect to the first pattern;

fig. 15A to 17B illustrate a pattern offset value calculation method for a peripheral circuit region according to some embodiments;

fig. 18 is a sectional view showing a stacked memory device according to an embodiment;

FIG. 19 is a flow diagram of a method of designing a layout of a stacked memory device according to an embodiment;

FIG. 20 is a flow chart of a method of fabricating a stacked memory device according to an embodiment; and

fig. 21 is a block diagram of a stacked memory device according to some embodiments.

Detailed Description

Fig. 1 is a flow chart of a method of manufacturing a stacked memory device according to an embodiment.

Referring to fig. 1, in operation S110, a layout of a stacked memory device is designed. Here, the layout is a physical representation through which a circuit designed for a stacked memory device can be transferred onto a wafer, and the layout may include a plurality of patterns. In this specification, a layout may be referred to as an "initial layout" or an "original layout". Here, the pattern may correspond to a circuit, an interconnection, or the like directly related to the operation of the stacked memory device. Here, in this specification, the pattern included in the initial layout will refer to the first pattern. In an embodiment, the first pattern may include a contact pattern disposed in a peripheral circuit region of the stacked memory device. However, the layout of the stacked memory device is not limited thereto, and the first pattern may include a conductive layer pattern or an insulating layer pattern.

Here, the stacked memory device refers to a memory device including a plurality of memory cells or a memory cell array vertically stacked on a substrate. In an embodiment, the stacked memory device may be a vertical channel type memory device including memory cells respectively connected to word lines vertically stacked on a substrate. In an embodiment, the stacked memory device may be a cross-point memory device in which word lines and bit lines are alternately stacked on a substrate and include memory cells arranged in regions where the word lines and the bit lines cross each other. However, the stacked memory device is not limited thereto.

The memory cell arrays, memory cells, and memories described herein are tangible storage media that can store data and executable instructions, and are non-transitory during the time instructions are stored therein. As used herein, the term "non-transitory" should be understood as not being a permanent feature of a state, but rather as a feature of a state that will last for a period of time. The term "non-transitory" specifically negates temporal features such as specific carrier waves or signals or other forms of features that are only temporarily present at any location at any time. The memory cell arrays, memory cells, or memories described herein are articles of manufacture and/or machine components. The memory cell arrays, memory cells, and memories described herein are computer-readable media from which data and executable instructions may be read by a computer.

In operation S130, Optical Proximity Correction (OPC) is performed on the patterns included in the layout. Optical Proximity Correction (OPC) is a technique for correcting image errors caused by diffraction in photolithography, for example. OPC can be performed by an OPC tool, which can receive layout data in a Graphic Database System (GDS) format, for example. The OPC tool may convert the layout data into data corresponding to OPC. For example, the OPC tool may be a software module comprising a plurality of instructions executable on a processor and may be stored in a non-transitory computer-readable storage medium.

Specifically, the second pattern may be formed by performing OPC on the first pattern included in the layout. Here, the second pattern may refer to a pattern formed by performing OPC. Here, the OPC refers to an operation of changing patterns included in a layout by reflecting an error caused by an Optical Proximity Effect (OPE). As the pattern becomes finer, OPE caused by influence between adjacent patterns may occur during the exposure process. Therefore, OPE can be suppressed by performing OPC that corrects the pattern layout on the mask onto which the pattern is transferred.

In operation S150, the OPC is checked. OPC can be verified by an OPC verification tool. An OPC verification tool may receive the layout data and OPC data and may verify the OPC. For example, the OPC inspection tool may be a software module comprising a plurality of instructions executable on a processor and may be stored in a non-transitory computer readable storage medium.

In the present embodiment, the offset value for the first pattern included in the layout may be calculated from the position of the first pattern. Whether the OPC is to be repeated (performed again) may be determined based on the offset value and a difference between the position of the first pattern and the position of the second pattern. The offset value may then be a predicted offset value calculated based on experience, such as from previous calculations and determinations. In an embodiment, a calculation formula for calculating an offset value for the first pattern may be different according to the position of the first pattern. Accordingly, misalignment of contacts formed along the second pattern may be prevented, and thus potential malfunction of a semiconductor chip in which the stacked memory device is implemented may be prevented.

In operation S170, a mask is formed. In an embodiment, a mask may be used to form contacts in a peripheral circuit region of a stacked memory device. Specifically, the mask may be formed by performing an exposure process on the substrate for the mask using the second pattern or using a third pattern formed by the re-performing of OPC. Here, the third pattern may refer to a pattern formed by performing the second OPC.

In operation S190, a stacked memory device is formed by using a mask. The stacked memory device is formed by performing various semiconductor processes on a semiconductor substrate such as a wafer using the mask. For example, the process using the mask may refer to a patterning process performed by a photolithography process. A desired pattern may be formed on the semiconductor substrate or the material layer through a patterning process. In an embodiment, the desired pattern may be contacts in a peripheral circuit region of the stacked memory device.

Fig. 2 is a layout 100 of a stacked memory device according to an embodiment.

Referring to fig. 2, the layout 100 may include a plurality of adjacent semiconductor chips CH1 through CH 4. A stacked memory device may be implemented in each of the semiconductor chips CH1 through CH 4. The first semiconductor chip CH1 and the second semiconductor chip CH2 are adjacent to each other in the X direction, and the third semiconductor chip CH3 and the fourth semiconductor chip CH4 are adjacent to each other in the X direction. The first semiconductor chip CH1 and the third semiconductor chip CH3 are adjacent to each other in the Y direction, and the second semiconductor chip CH2 and the fourth semiconductor chip CH4 are adjacent to each other in the Y direction.

The first semiconductor chip CH1 may include memory

cell array regions

110a and 110a' and a peripheral circuit region PA. The peripheral circuit region PA may be adjacent to the memory

cell array regions

110a and 110a' in the first direction. In an embodiment, the first direction may be a Y direction. However, the first semiconductor chip CH1 is not limited thereto, and the peripheral circuit region PA may be adjacent to the memory cell array region 110 in the X direction.

The peripheral circuit area PA may be divided into a plurality of areas according to its position. In an embodiment, the peripheral circuit region PA may be divided into first to third regions REG _ A, REG _ B and REG _ C along the Y direction. The peripheral circuit region PA may have a row decoder, a page buffer, a latch circuit, a cache circuit, a column decoder, a sense amplifier, or a data input/output circuit. The second to fourth semiconductor chips CH2 to CH4 are realized in the same manner as the first semiconductor chip CH 1. The first semiconductor chip CH1 will be mainly described below.

The memory cell array region 110 may be defined as an active region in which a memory cell array is disposed. Although it is illustrated that the first semiconductor chip CH1 includes two memory

cell array regions

110a and 110a', the first semiconductor chip CH1 is not limited thereto. The number of memory cell array regions included in the first semiconductor chip CH1 may vary.

Fig. 3 illustrates a memory cell array 111 according to an embodiment.

Referring to fig. 3, the memory cell array 111 includes a plurality of memory blocks BLK1 through BLKn and each of the memory blocks BLK1 through BLKn may have a 3-dimensional (3D) structure (or a vertical structure). Therefore, the memory cell array MCA may be referred to as a 3D memory cell array. For example, the memory cell array 111 may be arranged in each of the memory

cell array regions

110a and 110a' of fig. 2.

In an embodiment, a 3D memory cell array is integrally formed at least one physical level of a memory cell array having an active region and a circuit. The active region is disposed on the silicon substrate. The circuit is formed on or in the substrate as a circuit related to the operation of the memory cell. The term "integrally" means that the layers constituting the hierarchy of the array are stacked immediately above the layers of the hierarchy located below the array.

In an embodiment, a 3D memory cell array includes NAND strings arranged vertically such that at least one memory cell is located on another memory cell. The at least one memory cell may include a charge trapping layer. U.S. patent No. 7,679,133, U.S. patent No. 8,553,466, U.S. patent No. 8,654,587, U.S. patent No. 8,559,235, and U.S. patent application publication No. 2011/0233648, the disclosures of which are incorporated herein by reference, disclose suitable configurations of 3D memory arrays that include multiple levels and in which word lines and/or bit lines are shared by the levels.

Fig. 4 is a circuit diagram of an equivalent circuit of a first memory block BLK1, which is one of the memory blocks included in the memory cell array 111 of fig. 3.

Referring to fig. 4, the first memory block BLK1 may include a plurality of NAND strings NS11 to NS33, a plurality of word lines WL1 to WL8, a plurality of bit lines BL1 to BL3, a plurality of ground select lines GSL1 to GSL3, a plurality of string select lines SSL1 to SSL3, and a common source line CSL. Here, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground select lines, and the number of string select lines may vary according to embodiments.

Fig. 5 is a perspective view of the first memory block BLK1 of fig. 4.

Referring to fig. 5, the first memory block BLK1 is formed in a direction perpendicular to the substrate SUB. Although fig. 5 shows that the first memory block BLK1 includes two select lines GSL and SSL, eight word lines WL1 to WL8, and three bit lines BL1 to BL3, the number thereof may be more or less.

Referring back to fig. 2, when the memory blocks BLK1 through BLKn shown in fig. 3 through 5 are formed in the memory cell array region MCA of each of the semiconductor chips CH1 through CH4, the silicon substrate corresponding to the peripheral circuit region PA may be shifted to the memory cell array region MCA. Therefore, devices (for example, transistors) formed in advance in the silicon substrate can be shifted toward the memory cell array region MCA as compared with the pattern included in the initial layout. Misalignment can occur between the device and the contacts to be formed on the device. This will be described in detail below with reference to fig. 6A to 6F.

Fig. 6A to 6F are sectional views illustrating an example of a method of manufacturing a stacked memory device according to an embodiment. Fig. 6A to 6F may correspond to an example of operation S190 of fig. 1, and may correspond to a sectional view taken along line VI-VI' of fig. 2.

Referring to fig. 6A, an active region is defined by forming a device separation film 120 on a substrate 110. Here, the substrate 110 may be a semiconductor substrate. The substrate 110 may be divided into a memory cell array region 110a and a peripheral circuit region 110 b. For example, the memory cell array region 110a may correspond to the memory cell array region 110a of fig. 2. The peripheral circuit region 110b may correspond to the peripheral circuit region PA of fig. 2.

Subsequently, the transistor 130 is formed on the peripheral circuit region 110b of the substrate 110. Transistor 130 includes a gate structure including a gate insulator 131, a gate electrode 133, and a spacer 135. Transistor 130 also includes a source region 137 and a drain region 139 disposed on opposite sides of the gate structure. Here, the process of forming the transistor 130 on the peripheral circuit region 110b may be referred to as a "front end layer forming process".

Referring to fig. 6B, the interlayer insulating films 150 and the sacrificial films 160 are repeatedly alternately laminated to form a mold structure. The sacrificial film 160 has an etching selectivity with respect to the interlayer insulating film 150, and may be formed of a material that is easily removed by a wet etching process. The sacrificial film 160 may be removed by a subsequent process to provide a space in which a ground selection line, a word line, and a string selection line are formed.

Referring to fig. 6C, a step-type mold structure is formed by partially etching the interlayer insulating film 150 and the sacrificial film 160. Accordingly, the interlayer insulating film 150 and the sacrificial film 160 can be removed from the peripheral circuit region 110 b. The process shown in fig. 6A to 6C may be performed at, for example, about 650 ℃ for 30 minutes.

The substrate 110 may be stressed by a process of forming the stepped mold structure of fig. 6B and 6C (hereinafter, referred to as "mold stress"). Accordingly, the peripheral circuit region 110b of the substrate 110 may be offset toward the memory cell array region 110 a. Therefore, through the process of forming the front end layer of fig. 6A, the transistor 130 previously formed in the peripheral circuit region 110b can be shifted toward the memory cell array region 110 a.

Referring to fig. 6D, a plurality of via holes 170 may be formed through the interlayer insulating film 150 and the sacrificial film 160. In addition, a charge storage film structure is formed on the sidewall of the via hole 170. In addition, the sacrificial film 160 may be removed, and a plurality of gate electrodes 180 may be formed. Here, a process of forming the 3D memory cell array on the memory cell array region 110a may be referred to as a "cell array forming process". The cell array formation process may be performed at a temperature of, for example, about 850 deg.c for about 30 minutes.

The substrate 110 may be stressed by a process of forming the cell array of fig. 6D (hereinafter, referred to as "via hole stress"). Accordingly, the peripheral circuit region 110b of the substrate 110 may be offset toward the memory cell array region 110 a. Therefore, through the process of forming the front end layer of fig. 6A, the transistor 130 previously formed in the peripheral circuit region 110b can be shifted toward the memory cell array region 110 a.

Referring to fig. 6E, a gate contact 190 is formed on the transistor 130 in the peripheral circuit region 110b of the substrate 110. This process may be referred to as a "contact formation process". Then, the gate contact 190 may be formed using a mask formed along the first pattern included in the layout and the second pattern formed by the OPC. When the gate contact 190 is formed by using the formed mask without considering the offset of the transistor 130 caused by the above-described mold stress or via stress, the gate contact 190 may not be aligned with the gate electrode 133 at times.

Referring to fig. 6F, a metal layer 195 is formed on the gate contact 190. This process may be referred to as a "back end layer formation process". Due to the misalignment between the gate contact 190 and the gate electrode 133 in fig. 6E, the gate electrode 133 and the metal layer 195 may not be properly connected to each other. Therefore, the semiconductor chip (e.g., CH1 of fig. 2) in which the stacked memory device is formed may suffer from malfunction.

As already described with reference to fig. 6A to 6F, the stacked memory device may be formed by the following process: a front end layer forming process is performed first, then a cell array forming process is performed, then a process of forming a contact in the peripheral circuit region 110b is performed, and then a back end layer forming process is performed. Then, the transistor 130 of the peripheral circuit region 110b formed in the front end layer forming process may be shifted to the memory cell array region 110a by a mold stress or a via hole stress during the cell array forming process. Therefore, misalignment may be caused by the contacts 190 electrically connecting the front end layer and the back end layer, which may cause malfunction of the semiconductor chip in which the stacked memory device is formed.

Meanwhile, fig. 6A to 6F exemplarily show that the peripheral circuit region 110b adjacent to the memory cell array region 110a in the Y direction is shifted to the memory cell array region 110a by a mold stress or a via hole stress during a cell array formation process, that is, in the Y direction. However, the arrangement of the peripheral circuit region 110b and the memory cell array region 110a is not limited thereto. A peripheral circuit region adjacent to the memory cell array region 110a in the X direction may also be stressed by a die stress or a via hole stress during a cell array formation process, and thus may be shifted in the Y direction. Even in the peripheral circuit region adjacent to the memory cell array 110a in the X direction, misalignment may be caused by contacts electrically connecting the front end layer and the rear end layer, which may cause malfunction of the semiconductor chip in which the stacked memory device is formed.

Fig. 7 is a graph showing offset values according to areas in the peripheral circuit area PA included in the stacked memory device of fig. 2.

Referring to fig. 7, the horizontal axis indicates an area in the peripheral circuit area PA. The vertical axis represents an offset value of the silicon substrate corresponding to the region. In the present embodiment, the peripheral circuit region PA may be divided into first to third regions REG _ a to REG _ C along the Y direction.

The first region REG _ a is closest to the memory

cell array regions

110a and 110a' of the first semiconductor chip CH 1. Accordingly, the first region REG _ a may be shifted toward the memory

cell array regions

110a and 110a' of the first semiconductor chip CH1 due to stress from the memory cell array region 110 of the first semiconductor chip CH1 in the cell array formation process. Accordingly, the offset value corresponding to the first region REG _ a may correspond to + k, and the transistor TRa arranged in the first region REG _ a may be offset by k toward the memory cell array region 110 of the first semiconductor chip CH 1.

The third region REG _ C is farthest from the memory cell array region 110 of the first semiconductor chip CH1 but is closest to the memory

cell array regions

111a and 111a' of the third semiconductor chip CH 3. Accordingly, the third region REG _ C may be shifted toward the memory

cell array regions

111a and 111a 'of the third semiconductor chip CH3 due to stress from the memory

cell array regions

111a and 111a' of the third semiconductor chip CH3 in the cell array formation process. Accordingly, the offset value corresponding to the third region REG _ C may correspond to-k, and the transistor TRc disposed in the third region REG _ C may be offset by k toward the memory

cell array regions

111a and 111a' of the third semiconductor chip CH 3.

As for the second region REG _ B, a distance between the memory

cell array regions

110a and 110a 'of the first semiconductor chip CH1 and the second region REG _ B may be substantially the same as a distance between the memory

cell array regions

111a and 111a' of the third semiconductor chip CH3 and the second region REG _ B. Substantially the same stress may be applied from the memory

cell array regions

110a and 110a 'of the first semiconductor chip CH1 and the memory

cell array regions

111a and 111a' of the third semiconductor chip CH3 to the second region REG _ B. Accordingly, the offset value corresponding to the second region REG _ B may correspond to 0, and the transistor TRb disposed in the second region REG _ B may not be offset.

According to an embodiment, a calculation formula for calculating an offset value of a pattern on a peripheral circuit region may be established based on the graph of fig. 7. Specifically, a calculation formula for calculating the offset value of the pattern may be established based on the distance between the pattern and the memory cell array region of the corresponding semiconductor chip and the distance between the memory cell array regions of the adjacent semiconductor chips.

In the graph of fig. 7, the peripheral circuit region PA is divided into three regions, but the peripheral circuit region PA is not limited thereto. In an embodiment, the peripheral circuit region PA may be divided into a greater number of regions along the Y direction. Then, the offset value of the pattern can be calculated by using different calculation formulas for different areas. In an embodiment, the peripheral circuit region PA may be divided into two regions with respect to the reference line in the Y direction. For example, the shift direction of the pattern arranged on the reference line of the peripheral circuit region PA may be determined as the positive direction. The offset direction of the pattern disposed below the reference line may be determined as a negative direction.

Meanwhile, in some embodiments, the peripheral circuit region PA is not necessarily divided into a plurality of regions. In an embodiment, all the shift directions of the patterns included in the peripheral circuit region PA may be determined as positive directions. In an embodiment, all offset values of the patterns included in the peripheral circuit area PA may be determined to have a specific value in a positive direction. In an embodiment, all the shift directions of the patterns included in the peripheral circuit region PA may be determined as negative directions. In an embodiment, all offset values of the patterns included in the peripheral circuit area PA may be determined to have a specific value in a negative direction.

Meanwhile, although the offset value of the area in the peripheral circuit area PA of the first semiconductor chip CH1 according to fig. 2 has been described, the offset value is not limited thereto. The offset value may be different from that in fig. 7 even in the peripheral circuit region adjacent to the first semiconductor chip CH1 in the X direction according to the region.

Fig. 8 is a graph showing an offset value according to a position in the X direction in the first region REG _ a of the peripheral circuit region PA included in the stacked memory device of fig. 2.

Referring to fig. 8, the horizontal axis indicates a position in the X direction in the first region REG _ a. The vertical axis represents an offset value of the silicon substrate corresponding to the position. In the present embodiment, the position of the first region REG _ a in the X direction may be represented by 1 to N.

The position 1 in the X direction may correspond to an edge area of the first memory cell array region 110 a. Position 3 in the X direction may correspond to a central region of the first memory cell array region 110 a. In this way, the offset value of the silicon substrate with respect to the position in the X direction can be increased from the edge area of the first memory cell array area 110a toward the center. Therefore, the transistor corresponding to the position 3 in the X direction may be shifted closer to the first memory cell array region 110a than the transistor corresponding to the position 1 in the X direction.

Meanwhile, the position N-2 in the X direction may correspond to a central region of the second memory cell array region 110 a'. The position N in the X direction may correspond to an edge region of the second memory cell array region 110 a'. In this way, the offset value of the silicon substrate with respect to the position in the X direction can be reduced from the center region toward the edge region of the second memory cell array region 110 a'. Accordingly, the transistor corresponding to the position N-2 in the X direction may be shifted closer to the second memory cell array region 110a' than the transistor corresponding to the position N in the X direction.

According to an embodiment, a calculation formula for calculating an offset value of a pattern on a peripheral circuit region may be established based on the graph of fig. 8. Specifically, a calculation formula for calculating the offset value of the pattern may be established based on the distance between the pattern and the memory cell array region of the corresponding semiconductor chip and the distance between the memory cell array regions of the adjacent semiconductor chips and based on the position of the pattern in the X direction.

In an embodiment, the peripheral circuit region PA may be divided into a plurality of regions along the X direction. Then, the offset value of the pattern can be calculated by using different calculation formulas for different areas. In an embodiment, the peripheral circuit region PA may be divided into two regions with respect to the reference line in the X direction. For example, the shift direction of the pattern arranged on the left side of the reference line of the peripheral circuit region PA may be determined as the positive direction. The offset direction of the pattern disposed on the right side of the reference line may be determined as a negative direction.

FIG. 9 is a flow chart of an OPC inspection method for a stacked memory device according to an embodiment.

Referring to fig. 9, the OPC verifying method according to the present embodiment may correspond to an embodiment of operation S130 of fig. 1, for example. Therefore, the contents described with reference to fig. 1 to 8 can be applied to the present embodiment, and a repetitive description thereof will be omitted.

In operation S210, a first position of a first pattern in a layout of a stacked memory device is checked. Here, the stacked memory device may include a memory cell array region and a peripheral circuit region adjacent to the memory cell array region in the first direction. In an embodiment, the first pattern may include a contact pattern disposed in the peripheral circuit region. For example, the first pattern may include a gate contact pattern, a source contact pattern, or a drain contact pattern for a transistor disposed in the peripheral circuit region.

In an embodiment, the first position may be a Y-coordinate along the first direction in the layout. In an embodiment, the first position may be an X-coordinate along the second direction in the layout. In an embodiment, the first position may be a Y-coordinate along the first direction and an X-coordinate along the second direction in the layout. Hereinafter, a case where the first position is the Y coordinate will be mainly described. Operation S210 will be described in more detail with reference to fig. 10.

In operation S230, an offset value of the first pattern is calculated according to the first position. Specifically, the offset value of the first pattern may be calculated such that at least one of the offset direction of the first pattern and the magnitude of the offset value (i.e., the offset amount) changes according to the first position. That is, the offset value of the first pattern may be represented by a vector. In an embodiment, the offset value of the first pattern may be calculated such that the offset direction and the offset amount of the first pattern are changed according to the Y coordinate of the first pattern.

Here, the offset value of the first pattern may be an expected offset value for the first pattern. In the present embodiment, the expected offset value for the first pattern may be calculated by using a calculation formula established based on experience such as from previous calculations and determinations. For example, a calculation formula may be established based on the graphs of fig. 7 and 8.

In an embodiment, the calculation formula may be a linear function (i.e., f (x) ═ ax + b). In an embodiment, the calculation formula may be a quadratic function (i.e., f (x) ═ ax²+ bx + c). In an embodiment, the calculation formula may be a cubic function (i.e., f (x) ═ ax)³+bx²+ cx + d). Then, the value of x input into the calculation formula may be the first position of the first pattern checked in operation S210, and may be, for example, the Y coordinate of the first pattern. Meanwhile, in an embodiment, the calculation formula may simply be a constant value, in which case the offset value of the first pattern may be constant regardless of the first position.

In some embodiments, the offset value of the first pattern may be calculated by applying the same calculation formula regardless of the first position. In an embodiment, the first position of the first pattern checked in operation S210 may be a Y coordinate, and the offset value of the first pattern may be calculated regardless of the Y coordinate by applying the same calculation formula in operation S230. In an embodiment, the first position of the first pattern checked in operation S210 may be an X coordinate, and the offset value of the first pattern may be calculated regardless of the X coordinate by applying the same calculation formula in operation S230.

In some embodiments, the offset value of the first pattern may be calculated by applying a different calculation formula according to the first position. In an embodiment, the first position of the first pattern checked in operation S210 may be a Y coordinate, and the offset value of the first pattern may be calculated in operation S230 by applying a different calculation formula according to the Y coordinate. For example, the offset value of the first pattern may be calculated by applying a linear function to some Y coordinates, and the offset value of the first pattern may be calculated by applying a cubic function to other Y coordinates. In an embodiment, the first position of the first pattern checked in operation S210 may be an X coordinate, and the offset value of the first pattern may be calculated in operation S230 by applying a different calculation formula according to the X coordinate. For example, the offset value of the first pattern may be calculated by applying a linear function to some X-coordinates, and the offset value of the first pattern may be calculated by applying a cubic function to other X-coordinates. Operation S230 will be described in more detail with reference to fig. 11 to 13.

In operation S250, a difference between a second position of the second pattern (which is formed by OPC with respect to the first pattern) and a first position of the first pattern is obtained. In an embodiment, a difference between a first Y coordinate corresponding to the first location and a second Y coordinate corresponding to the second location may be obtained. Operation S250 will be described in more detail with reference to fig. 14A to 14D.

In operation S270, the offset value and the difference value are compared. In operation S290, it is determined whether the comparison value is within the tolerance. Whether the second pattern is within the tolerance may be determined based on the offset value and the direction and magnitude of the difference value. If the second pattern is within the tolerance after the determining, it is determined that the misalignment of the contact corresponding to the first pattern is accurately corrected and that the OPC verification result is successful. If the second pattern deviates from the tolerance, it is determined that the misalignment of the contact corresponding to the first pattern is not accurately corrected and that the OPC verification result reflects a failure. In an embodiment, it may be determined that the second OPC is to be performed for the second pattern. In an embodiment, it may be determined that the layout is formed again.

Fig. 10 is a view illustrating an operation of checking a position of a pattern in a layout of a stacked memory device according to an embodiment.

Referring to fig. 10, the stacked memory device may be implemented in a semiconductor chip CH. The semiconductor chip CH may include memory cell array regions 210a and 210b, row decoder regions 220a to 220c, and a peripheral circuit region 230. The row decoder regions 220a to 220c may be adjacent to the memory cell array regions 210a and 210b in the X direction. The row decoders may be arranged in the row decoder regions 220a to 220 c. The peripheral circuit region 230 may be adjacent to the memory cell array regions 210a and 210b and the row decoder regions 220a to 220c in the Y direction. A page buffer, a data input/output circuit, and the like may be disposed in the peripheral circuit region 230.

In an embodiment, the Y coordinate of the pattern disposed in the peripheral circuit region 230 may be checked. In an embodiment, the X-coordinate of the pattern disposed in the peripheral circuit region 230 may be checked. In an embodiment, the X-coordinate and the Y-coordinate of the pattern disposed in the peripheral circuit region 230 may be checked.

Further, in an embodiment, the Y-coordinate of the patterns arranged in the row decoder regions 220a to 220c may be checked. Further, in an embodiment, X coordinates of patterns arranged in the row decoder regions 220a to 220c may be checked. Further, in an embodiment, X and Y coordinates of patterns arranged in the row decoder regions 220a to 220c may be checked.

Fig. 11 is a sectional view taken along line XI-XI' of fig. 10.

Referring to fig. 11, a substrate 200 may be divided into a memory cell array region 210a and a peripheral circuit region 230. A memory cell array including a stacked structure of the via hole 213 and the interlayer insulating film 211 and the gate electrode 212 may be formed in the memory cell array region 210 a. A transistor TR including a gate electrode 231, a source region 232, and a drain region 233 may be formed in the peripheral circuit region 230. A gate contact 231a, a source contact 232a, and a drain contact 233a may be formed on the gate electrode 231, the source region 232, and the drain region 233, respectively. Metal layers MTa, MTb, and MTc may be formed on the gate contact 231a, the source contact 232a, and the drain contact 233a, respectively. As described above, the transistor TR may be shifted toward the memory cell array region 210a due to stress during the cell array formation process.

Fig. 12 is an initial layout 300 for the peripheral circuit region 230 of fig. 11.

Referring to fig. 12, the initial layout 300 for the peripheral circuit region 230 may be a layout designed in operation S110 of fig. 1, for example. The initial layout 300 includes an active region pattern 310, a gate electrode pattern 320, a gate contact pattern 331, a source contact pattern 332, a drain contact pattern 333, and metal layer patterns 341 to 343.

The active region pattern 310 may correspond to an active region of the peripheral circuit region 230 of fig. 11. The gate electrode pattern 320 may correspond to the gate electrode 231 of fig. 11. In addition, the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333 may correspond to the gate contact 231a, the source contact 232a, and the drain contact 233a of fig. 11, respectively. In addition, the metal layer patterns 341 to 343 may correspond to the metal layers MTa to MTc of fig. 11, respectively.

The initial layout 300 may not properly reflect the offset of the silicon substrate corresponding to the peripheral circuit region 230 due to stress during the cell array formation process. Therefore, according to the present embodiment, in operation S210 of fig. 9, the positions of the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333 in the initial layout 300 may be checked. In an embodiment, Y coordinates of the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333 may be checked. Hereinafter, the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333 may be referred to as a first pattern PT 1.

Fig. 13 illustrates a first corrected pattern PT1' for the first pattern PT1 of fig. 12 according to a pattern offset value calculation operation of an embodiment.

Referring to fig. 13, offset values SV1, SV2, and SV3 may be calculated from the positions of the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333 corresponding to the first pattern PT 1. In comparison with the layout 300 of fig. 12, the layout 300 'of fig. 13 further includes a corrected gate contact pattern 331', a corrected source contact pattern 332', and a corrected drain contact pattern 333'. The corrected gate contact pattern 331', the corrected source contact pattern 332', and the corrected drain contact pattern 333' may be formed based on offset values SV1, SV2, and SV3 calculated for the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333, respectively. Hereinafter, the corrected gate contact pattern 331', the corrected source contact pattern 332', and the corrected drain contact pattern 333 'may be referred to as a first corrected pattern PT 1'.

In an embodiment, the positions of the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333 may be classified by their Y-coordinates. For example, the source contact pattern 332 is closest to the memory cell array region 210a, and the drain contact pattern 333 may be farthest from the memory cell array region 210 a. Accordingly, offset values SV1, SV2, and SV3 of the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333 may be different from each other.

In an embodiment, the offset value according to the Y coordinate may be calculated by applying the same calculation formula to the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333. For example, the calculation formula may be implemented by a cubic function, and the Y-coordinates of the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333 are different from each other. As a result, offset values SV1, SV2, and SV3 for the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333 may be calculated differently. The cubic function may be pre-established based on prior calculations and experience with the function.

In an embodiment, the offset value according to the Y coordinate may be calculated by applying different calculation formulas to the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333. For example, a calculation formula implemented by a linear function may be applied to the gate contact pattern 331 and the source contact pattern 332. The calculation implemented by the cubic function may be applied to the drain contact pattern 333. The linear function and the cubic function may be established in advance based on prior calculations and experience with the functions.

Fig. 14A to 14D illustrate various embodiments of the first pattern PT1 of fig. 11 and the second pattern PT2 formed by OPC with respect to the first pattern PT 1. In fig. 14A to 14D, the first pattern PT1 may be one of the gate contact pattern 331, the source contact pattern 332, and the drain contact pattern 333 of fig. 11. Hereinafter, a case in which the first pattern PT1 corresponds to the gate contact pattern 331 of fig. 11 will be mainly described.

Referring to fig. 14A, the second pattern PT2a may be a pattern formed by performing OPC on the first pattern PT 1. The position of the second pattern PT2a along the Y direction may be shifted by the first difference DV1 in the positive direction, compared to the position of the first pattern PT1 in the Y direction.

According to the present embodiment, the first difference DV1 may be obtained by a difference between the first position of the first pattern PT1 and the second position of the second pattern PT 2. Subsequently, it is determined whether the first difference DV1 is within the OPC tolerance by comparing the first difference DV1 with the offset value SV 1. In fig. 14A, the direction of the first difference value DV1 and the direction of the offset value SV1 may be the same. The difference between the first difference value DV1 and the offset value SV1 may be within the reference value. Then, assuming that OPC was successful, contacts may be formed by manufacturing a mask according to the second pattern PT2 a. Misalignment of the contacts can be prevented.

Referring to fig. 14B, the second pattern PT2B may be a pattern formed by performing OPC on the first pattern PT 1. The position of the second pattern PT2b along the Y direction may be shifted by the second difference DV2 in the positive direction, compared to the position of the first pattern PT1 in the Y direction. Then, the second difference DV2 may be greater than the first difference DV1 of fig. 14A.

According to the present embodiment, the second difference DV2 may be obtained by the difference between the first position of the first pattern PT1 and the second position of the second pattern PT 2. Subsequently, it is determined whether the second difference DV2 is within the OPC tolerance by comparing the second difference DV2 with the offset value SV 1. In fig. 14B, the direction of the second difference value DV2 and the direction of the offset value SV1 may be the same, but the difference between the second difference value DV2 and the offset value SV1 may be greater than the reference value. Then, assuming that the OPC fails, it may be determined that the second OPC is to be performed.

Referring to fig. 14C, the second pattern PT2C may be a pattern formed by performing OPC on the first pattern PT 1. The position of the second pattern PT2c along the Y direction may be shifted by the third difference DV3 in the negative direction compared to the position of the first pattern PT1 in the Y direction.

According to the present embodiment, the third difference DV3 may be obtained by the difference between the first position of the first pattern PT1 and the second position of the second pattern PT2 c. Subsequently, it is determined whether the third difference DV3 is within the OPC tolerance by comparing the third difference DV3 with the offset value SV 1. In fig. 14C, the difference between the third difference value DV3 and the offset value SV1 is smaller than the reference value, but the direction of the third difference value DV3 and the direction of the offset value SV1 may be different. Then, assuming that the OPC fails, it may be determined that the second OPC is to be performed.

Referring to fig. 14D, the second pattern PT2D may be a pattern formed by performing OPC on the first pattern PT 1. The position of the second pattern PT2d along the Y direction may be shifted by the fourth difference DV4 in the negative direction compared to the position of the first pattern PT1 in the Y direction.

According to the present embodiment, the fourth difference DV4 may be obtained by the difference between the first position of the first pattern PT1 and the second position of the second pattern PT2 d. Subsequently, it is determined whether the fourth difference DV4 is within the OPC tolerance by comparing the fourth difference DV4 with the offset value SV 1. In fig. 14D, the difference between the fourth difference value DV4 and the offset value SV1 is larger than the reference value, but the direction of the fourth difference value DV4 and the direction of the offset value SV1 may be different. Then, assuming that the OPC fails, it may be determined that the second OPC is to be performed.

Fig. 15A to 17B illustrate a pattern offset value calculation method for a peripheral circuit region according to some embodiments.

Referring to fig. 15A, the stacked memory device may be implemented in the semiconductor chip CHa. The semiconductor chip CHa may include memory

cell array regions

410a and 410b, row decoder regions 420a to 420c, first

peripheral circuit regions

430a and 430b, and second peripheral circuit regions 440a to 440 c. The row decoder regions 420a to 420c may be adjacent to the memory

cell array regions

410a and 410b in the X direction. The row decoders may be arranged in row decoder regions 420a to 420 c.

The first

peripheral circuit regions

430a and 430b may be adjacent to the memory

cell array regions

410a and 410b in the Y direction. For example, page buffers, data input/output circuits, and the like may be disposed in the first

peripheral circuit regions

430a and 430 b. The second peripheral circuit regions 440a to 440c may be adjacent to the first

peripheral circuit regions

430a and 430b in the X direction, and may be adjacent to the row decoder regions 420a to 420c in the Y direction. For example, a discharge circuit or the like connected to the common source line CSL may be disposed in the second peripheral circuit regions 440a to 440 c.

In the present embodiment, offset values for the first patterns arranged in the first

peripheral circuit regions

430a and 430b and the second peripheral circuit regions 440a to 440c may be calculated. The offset value for such a first pattern may be calculated by applying the same calculation formula to the first

peripheral circuit regions

430a and 430b and the second peripheral circuit regions 440a to 440 c. That is, a calculation formula for calculating the offset value can be determined regardless of the X coordinate.

For example, when a reference line corresponding to a Y coordinate of 0 is taken as a center, an offset value for the first pattern disposed above the reference line in the first

peripheral circuit regions

430a and 430b and the second peripheral circuit regions 440a to 440c may be determined by + a 1. The offset value for the first pattern disposed below the reference line in the first

peripheral circuit regions

430a and 430b and the second peripheral circuit regions 440a to 440c may be determined by-a 1.

For example, when a reference line corresponding to a Y coordinate of 0 is taken as a center, an offset value for a first pattern disposed above the reference line in the first

peripheral circuit regions

430a and 430b and the second peripheral circuit regions 440a to 440c may be determined by applying a first calculation formula. The offset value for the first pattern disposed below the reference line in the first

peripheral circuit regions

430a and 430b and the second peripheral circuit regions 440a to 440c may be determined by applying a second calculation formula.

Referring to fig. 15B, the stacked memory device may be implemented in the semiconductor chip CHa'. The semiconductor chip CHb' according to the present embodiment is a modified embodiment of the semiconductor chip CHa of fig. 15a, and only the differences therebetween will be mainly described below.

In the present embodiment, the offset values for the first patterns arranged in the row decoder areas 420a to 420c may be calculated by applying a first calculation formula to the row decoder areas 420a to 420 c. That is, the calculation formula for calculating the offset value may be determined based on the Y coordinate regardless of the X coordinate. For example, when a first reference line according to a Y coordinate is taken as a center, an offset value for a first pattern arranged above the first reference line in the row decoder areas 420a to 420c may be determined by + a 2. The offset value for the first pattern arranged below the first reference line in the row decoder areas 420a to 420c may be determined by-a 2. For example, the first calculation formula may be implemented by a linear function.

peripheral circuit regions

430a and 430b and the second peripheral circuit regions 440a to 440c may be calculated. The offset value for such a first pattern may be calculated by applying a second calculation formula different from the first calculation formula applied to the row decoder regions 420a to 420c to the first

peripheral circuit regions

430a and 430b and the second peripheral circuit regions 440a to 440 c. That is, the calculation formula for calculating the offset value may be determined based on the Y coordinate regardless of the X coordinate.

peripheral circuit regions

430a and 430b and the second peripheral circuit regions 440a to 440c may be calculated. Offset values for such a first pattern may be calculated by applying a first calculation formula applied to the row decoder regions 420a to 420c to the first

peripheral circuit regions

430a and 430b and the second peripheral circuit regions 440a to 440 c. Further, in the embodiment, the offset value for the first pattern arranged in the row decoder areas 420a to 420c may be calculated by applying a first calculation formula to the row decoder areas 420a to 420 c. The offset values do not have to be calculated separately for the first patterns disposed in the first

peripheral circuit regions

430a and 430b and the second peripheral circuit regions 440a to 440 c.

Referring to fig. 16A, the stacked memory device may be implemented in the semiconductor chip CHb. The semiconductor chip CHb according to the present embodiment is a modified embodiment of the semiconductor chip CHa of fig. 15a, and only the differences therebetween will be mainly described below. In an embodiment, the second peripheral circuit regions 440a to 440c may be divided into a plurality of regions according to their X-coordinates, respectively.

In the present embodiment, offset values for the first patterns disposed in the first

peripheral circuit regions

430a and 430b and the second peripheral circuit regions 440a to 440c may be calculated by applying different calculation formulas to the first

peripheral circuit regions

430a and 430b and the second peripheral circuit regions 440a to 440 c. That is, the calculation formula for calculating the offset value may be determined based on the Y coordinate, based on the X coordinate and the Y coordinate.

For example, when a reference line corresponding to a Y coordinate of 0 is taken as a center, an offset value for the first pattern arranged above the reference line in the first

peripheral circuit regions

430a and 430b may be determined by + a 1. The offset value for the first pattern arranged below the reference line in the first peripheral circuit regions 430a to 430b may be determined by-a 1. Further, an offset value for the first pattern disposed above the reference line in the second peripheral circuit regions 440a to 440c may be determined by + b 1. The offset value for the first pattern disposed below the reference line in the second peripheral circuit regions 440a to 440c may be determined by-b 1.

peripheral circuit regions

430a and 430b may be determined by applying a first calculation formula. The offset value for the first pattern disposed below the reference line in the first peripheral circuit regions 430a to 430b may be determined by applying a second calculation formula. Further, the offset value for the first pattern disposed above the reference line in the second peripheral circuit regions 440a to 440c may be determined by applying a third calculation formula. The offset value for the first pattern disposed below the reference line in the second peripheral circuit regions 440a to 440c may be determined by applying a fourth calculation formula.

Referring to fig. 16B, the stacked memory device may be implemented in the semiconductor chip CHb'. The semiconductor chip CHb' according to the present embodiment is a modified embodiment of the semiconductor chip CHb of fig. 16A, and only the differences therebetween will be mainly described below.

Referring to fig. 17A, the stacked memory device may be implemented in the semiconductor chip CHc. The semiconductor chip CHc according to the present embodiment is a modified embodiment of the semiconductor chip CHa of fig. 15a, and only the differences therebetween will be mainly described below.

In an embodiment, the first and second center

peripheral circuit regions

431a and 431b may be divided into a plurality of regions according to their X-coordinates, respectively. In an embodiment, the first and second edge peripheral circuit regions 432a to 432d may be divided into a plurality of regions according to their X-coordinates, respectively. In an embodiment, the second peripheral circuit regions 440a to 440c may be divided into a plurality of regions according to their X-coordinates, respectively.

Meanwhile, although the peripheral circuit region adjacent to the first memory cell array region 410a in the Y direction is divided into the first center peripheral circuit region 431a and the first edge peripheral circuit regions 432a and 432b in fig. 17A, the peripheral circuit region is not limited thereto. In another embodiment, the peripheral circuit region adjacent to the first memory cell array region 410a in the Y direction may be divided into a plurality of regions according to their X coordinates. For example, a peripheral circuit region adjacent to the first memory cell array region 410a in the Y direction may be divided into a left peripheral circuit region and a right peripheral circuit region. Similarly, a peripheral circuit region adjacent to the second memory cell array region 410b in the Y direction may be divided into a left peripheral circuit region and a right peripheral circuit region.

The first central peripheral circuit region 431a may be adjacent to a central region of the memory cell array region 410a in the Y direction. Devices connected to the central region of the memory cell array region 410a through a plurality of central bit lines may be arranged in the first central peripheral circuit region 431 a. The second central peripheral circuit region 431b may be adjacent to a central region of the memory cell array region 410b in the Y direction. Devices connected to the central region of the memory cell array region 410b through a plurality of central bit lines may be arranged in the second central peripheral circuit region 431 b. The transistors disposed in the first and second central

peripheral circuit regions

431a and 431b will be referred to as central transistors.

The first edge peripheral circuit regions 432a and 432b may be adjacent to an edge region of the memory cell array region 410a in the Y direction. Devices connected to the edge region of the memory cell array region 410a through a plurality of edge bit lines may be arranged in the first edge peripheral circuit regions 432a and 432 b. The second edge

peripheral circuit regions

432c and 432d may be adjacent to an edge region of the memory cell array region 410b in the Y direction. Devices connected to the edge region of the memory cell array region 410b through a plurality of edge bit lines may be arranged in the second edge

peripheral circuit regions

432c and 432 d. The transistors arranged in the first and second edge peripheral circuit regions 432a to 432d will be referred to as edge transistors.

In the present embodiment, offset values may be calculated for the first patterns arranged in the first and second center

peripheral circuit regions

431a and 431b, the first and second edge peripheral circuit regions 432a to 432d, and the second peripheral circuit regions 440a to 440 c. The offset values may be calculated by applying different calculation formulas to the first and second center

peripheral circuit regions

431a and 431b, the first and second edge peripheral circuit regions 432a to 432d, and the second peripheral circuit regions 440a to 440 c. That is, the calculation formula for calculating the offset value may be based on the X coordinate and the Y coordinate.

For example, when a reference line corresponding to a Y coordinate of 0 is taken as a center, an offset value for the first pattern arranged above the reference line in the first and second central

peripheral circuit regions

431a and 431b may be determined by + a 1. The offset value for the first pattern arranged below the reference line in the first and second central

peripheral circuit regions

431a and 431b may be determined by-a 1. Further, an offset value for the first pattern arranged above the reference line in the first and second edge peripheral circuit regions 432a to 432d may be determined by + c 1. The offset value for the first pattern arranged below the reference line in the first and second edge peripheral circuit regions 432a to 432d may be determined by-c 1. Further, an offset value for the first pattern disposed above the reference line in the second peripheral circuit regions 440a to 440c may be determined by + b 1. The offset value for the first pattern disposed below the reference line in the second peripheral circuit regions 440a to 440c may be determined by-b 1.

peripheral circuit regions

431a and 431b may be determined by applying a first function. The offset value for the first pattern arranged below the reference line in the first and second central peripheral circuit regions 431a to 431b may be determined by applying a second function. Further, the offset value for the first pattern arranged above the reference line in the first and second edge peripheral circuit regions 432a to 432d may be determined by applying a third function. The offset value for the first pattern arranged below the reference line in the first and second edge peripheral circuit regions 432a to 432d may be determined by applying a fourth function. Further, an offset value for the first pattern arranged above the reference line in the second peripheral circuit regions 440a to 440c may be determined by applying a fifth function. The offset value for the first pattern disposed below the reference line in the second peripheral circuit regions 440a to 440c may be determined by applying a sixth function. In an embodiment, the first to sixth functions may all be different from each other. In an embodiment, at least two of the first to sixth functions may be the same. In an embodiment, all of the first to sixth functions may be the same.

Referring to fig. 17B, the stacked memory device may be implemented in the semiconductor chip CHc'. The semiconductor chip CHc' according to the present embodiment is a modified embodiment of the semiconductor chip CHc of fig. 17a, and only the differences therebetween will be mainly described below.

Fig. 18 is a sectional view illustrating a stacked memory device according to an embodiment.

Referring to fig. 18, a stacked memory device 500 corresponds to an ideal case of being manufactured according to an initial layout. The gate contact 530 may be aligned with the gate electrode 520 of the transistor TR, assuming that the peripheral circuit region 510b is not shifted due to a mold stress or a channel hole stress caused by a cell array formation process.

The stacked memory device 500a corresponds to a practical case of being manufactured according to an initial layout without performing OPC verification (e.g., the method of fig. 9) according to an embodiment. In contrast to the stacked memory device 500, the transistors TR disposed in the peripheral circuit region 510b may be shifted toward the memory cell array region 510a by d1 due to die stress or via hole stress caused by the cell array formation process. Accordingly, the gate contact 530 may be misaligned with the gate electrode 520a of the transistor TR.

The stacked memory device 500b corresponds to a case of being manufactured by performing an OPC inspection (e.g., the method of fig. 9) according to an embodiment. According to the present embodiment, determining whether the OPC is to be performed again may be performed by calculating an offset value of the contact pattern corresponding to the gate contact 530b in advance, and comparing the difference value of the contact pattern of the initial layout and the contact pattern on which the OPC has been performed with the offset value. Accordingly, the corrected contact pattern may be shifted toward the memory cell array region 510a by d1 as compared to the contact pattern of the initial layout. When the gate contact 530b is formed by using a mask manufactured according to the corrected contact pattern, the gate contact 530b may be aligned with the gate electrode 520b even though it is formed after the cell array formation process.

Fig. 19 is a flow chart of a method of designing a layout of a stacked memory device according to an embodiment.

Referring to fig. 19, in operation S310, a first position of a first pattern in an initial layout of a stacked memory device is checked. In operation S330, an offset value of the first pattern is calculated according to the first position. In operation S350, a difference between a second position and a first position of the second pattern obtained through the first OPC is obtained. The operation of performing the first OPC on the first pattern may further be included between operations S330 and S350.

In operation S370, it is determined whether the second OPC is to be performed based on the offset value and the difference value. In operation S390, a final layout is formed based on the second pattern or the third pattern formed by the second OPC. The operation of performing the second OPC on the second pattern may further be included between operations S370 and S390.

Fig. 20 is a flow chart of a method of fabricating a stacked memory device according to an embodiment.

Referring to fig. 20, in operation S410, a layout of a stacked memory device is designed. In operation S420, an offset value of a first pattern is calculated according to a first position of the first pattern in a layout of a stacked memory device. In operation S430, a difference between a second position and a first position of a second pattern formed by the first OPC is obtained. The operation of performing the first OPC on the first pattern may further be included between operations S420 and S430.

In operation S440, it is determined whether the second OPC is to be performed based on the offset value and the difference value. In operation S450, a mask is formed based on the second pattern or a third pattern formed by the second OPC. The operation of performing the second OPC on the second pattern may further be included between operations S440 and S450. In operation S460, a stacked memory device is formed through a photolithography process using a mask.

Fig. 21 is a block diagram of a stacked memory device 1000 according to some embodiments.

Referring to fig. 21, the stacked memory device 1000 may include a memory cell array 1100, a row decoder 1200, a page buffer 1300, an input/output buffer 1400, a control logic circuit 1500, and a voltage generator 1600. Peripheral circuits such as a row decoder, a page buffer 1300, an input/output buffer 1400, a control logic circuit 1500, and a voltage generator 1600 may be arranged adjacent to the memory cell array 1100 in the first direction.

In an embodiment, the first direction may correspond to the Y direction of fig. 2. The peripheral circuit may include a plurality of transistors electrically connected to the memory cell array 1100. When the stacked memory device 1000 is manufactured by the method of fig. 1, 9, 19, or 20, the positions of the contacts connected to the first transistor among the plurality of transistors in the first direction may be substantially the same. The first transistor may be the same distance from the memory cell array 1100. For example, the contacts may be gate contacts respectively connected to gate electrodes of the transistors. According to this embodiment, the gate electrodes may be aligned with the respective gate contacts.

In an embodiment, the first direction may correspond to the Y direction of fig. 2. The peripheral circuit may include a transistor electrically connected to a first region of the memory cell array 1100 and a transistor electrically connected to a second region of the memory cell array 1100. Here, although the memory cell array 1100 is divided into two regions, the memory cell array 1100 is not limited thereto, and the memory cell array 1100 may be divided into three or more regions. Therefore, the peripheral circuit may also be divided into three or more regions. When the stacked memory device 1000 is manufactured by the method of fig. 1, 9, 19, or 20, first positions in the first direction of the first contacts connected to the first transistors among the transistors electrically connected to the first region may be substantially the same. The first transistor may be the same distance from the memory cell array 1100. Further, the second positions of the second contacts connected to the second transistors among the transistors electrically connected to the second region may be substantially the same. The second transistors may be spaced the same distance from the memory cell array 1100.

For example, the first direction may correspond to the Y direction of fig. 2, the first region of the memory cell array 1100 may be a central region, and the second region of the memory cell array 1100 may be an edge region. Then, the peripheral circuit may include a center transistor electrically connected to a center region of the memory cell array 1100 and an edge transistor electrically connected to an edge region of the memory cell array 1100. When the stacked memory device 1000 is manufactured by the method of fig. 1, 9, 19, or 20, the first positions of the first contacts connected to the first transistors in the center transistors in the first direction may be substantially the same. The first transistor may be the same distance from the memory cell array 1100. Further, the second locations of the second contacts connected to the second ones of the edge transistors may be substantially the same. The second transistors may be spaced the same distance from the memory cell array 1100.

When the distance from the memory cell array 1100 to the first transistor and the distance from the memory cell array 1100 to the second transistor are the same, the first position and the second position may be different. For example, the first contacts may be first gate contacts respectively connected to the first gate electrodes of the first transistors. The second contacts may be second contacts respectively connected to the second gate electrodes of the second transistors. According to this embodiment, the first gate electrodes may be aligned with the corresponding first gate contacts, respectively, and the second gate electrodes may be aligned with the corresponding second gate contacts, respectively.

In an embodiment, the first direction may correspond to the X direction of fig. 2. The peripheral circuit may include a plurality of transistors electrically connected to the memory cell array 1100. When the stacked memory device 1000 is manufactured by the method of fig. 1, 9, 19, or 20, the first position of the first contact connected to the first transistor of the plurality of transistors may be substantially the same. The first position of the first contact along the Y direction may be the same. For example, the contacts may be gate contacts respectively connected to gate electrodes of the transistors. According to this embodiment, the gate electrodes may be aligned with the respective gate contacts.

The memory cell array 1100 may be arranged in a memory cell array region (e.g., 110a and 110a' of fig. 2, 210a and 210B of fig. 10, 410a and 410B of fig. 15A to 17B, or 510a of fig. 18). The row decoder 1200, the page buffer 1300, the input/output buffer 1400, the control logic circuit 1500, or the voltage generator 1600 may be arranged in a peripheral circuit region (e.g., PA of fig. 2, 230 of fig. 10, 430a, 430B, 440a to 440c, 431a, 431B, and 432a to 432d of fig. 15A to 17B, or 510B of fig. 18).

Although the embodiments have been described above with reference to the accompanying drawings, it should be understood that these embodiments are given by way of illustration only, and that various changes, alterations, and modifications may be made without departing from the spirit and scope of the disclosure. Therefore, the true technical scope of the present disclosure will be determined by the technical spirit of the claims.

This application claims priority to korean patent application No. 10-2016-0022824, filed in korean patent office at 25/2/2016, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A method of fabricating a stacked memory device, comprising:

designing a layout of the stacked memory device, the layout including a first pattern;

calculating an offset value of the first pattern from a first position of the first pattern in the layout, the offset value representing an offset of the first pattern due to stress during a formation process of a memory cell array region of the stacked memory device;

obtaining a difference between the first position of the first pattern and a second position of a second pattern formed by a first optical proximity correction to the first pattern;

determining, by a processor executing software instructions, whether a second optical proximity correction is to be performed based on the offset value and the difference value;

forming a third pattern by the second optical proximity correction when the processor determines that the second optical proximity correction is to be performed;

forming a mask based on the second pattern or the third pattern formed by the second optical proximity correction; and

the stacked memory device is formed by a photolithography process using the mask.

2. The method of claim 1, wherein the stacked memory device includes the memory cell array region and a peripheral circuit region adjacent to the memory cell array region in a first direction, the first pattern including a contact pattern arranged in the peripheral circuit region.

3. The method of claim 2, wherein the first location comprises a Y-coordinate of the first pattern along the first direction.

4. The method of claim 3, wherein calculating the offset value comprises calculating the offset value such that at least one of an offset direction and an offset amount of the first pattern changes according to the Y coordinate.

5. The method of claim 4, wherein calculating the offset value comprises:

selecting one of a plurality of calculation formulas according to the Y coordinate; and

calculating the offset value using the selected calculation formula.

6. The method of claim 3, wherein obtaining the difference comprises obtaining a difference between a first Y coordinate corresponding to the first location and a second Y coordinate corresponding to the second location.

7. The method of claim 2, wherein the first location comprises a Y-coordinate of the first pattern along the first direction and an X-coordinate of the first pattern along a second direction, and the second direction is substantially perpendicular to the first direction.

8. The method of claim 7, wherein calculating the offset value comprises:

selecting one of a plurality of calculation formulas according to the X coordinate; and

calculating the offset value using the selected calculation formula.

9. The method of claim 7, wherein calculating the offset value comprises:

selecting one of a plurality of calculation formulas according to the X coordinate and the Y coordinate; and

calculating the offset value using the selected calculation formula.

10. The method of claim 7, wherein the stacked memory device further comprises a row decoder region adjacent to the memory cell array region in the second direction,

wherein the peripheral circuit region includes a first peripheral circuit region adjacent to the memory cell array region and a second peripheral circuit region adjacent to the row decoder region, and

wherein calculating the offset value comprises:

calculating the offset value from the Y coordinate by using a first calculation formula when the X coordinate is in the first peripheral circuit region; and is

Calculating the offset value from the Y coordinate by using a second calculation formula when the X coordinate is in the second peripheral circuit region.

11. The method of claim 10, wherein calculating the offset value further comprises calculating the offset value according to the Y coordinate by using a third calculation formula when the Y coordinate is in the row decoder area.

12. The method of claim 7, wherein the stacked memory device further comprises a row decoder region adjacent to the memory cell array region in the second direction,

wherein the peripheral circuit region includes a first central peripheral circuit region adjacent to a central region of the memory cell array region, a first edge peripheral circuit region adjacent to an edge region of the memory cell array region, and a second peripheral circuit region adjacent to the row decoder region, and

wherein calculating the offset value comprises:

calculating the offset value from the Y coordinate by using a first calculation formula when the X coordinate is in the first central peripheral circuit region;

calculating the offset value from the Y coordinate by using a second calculation formula when the X coordinate is in the first edge peripheral circuit region; and

calculating the offset value from the Y coordinate by using a third calculation formula when the X coordinate is in the second peripheral circuit region.

13. The method of claim 12, wherein calculating the offset value further comprises calculating the offset value according to the Y coordinate by using a fourth calculation formula when the Y coordinate is in the row decoder area.

14. The method of claim 7, wherein obtaining the difference comprises obtaining a difference between a first Y coordinate corresponding to the first location and a second Y coordinate corresponding to the second location.

15. The method of claim 2, further comprising performing the optical proximity correction on the first pattern before obtaining the difference, and

wherein performing the optical proximity correction includes forming the second pattern by shifting the first pattern according to the first position so that the first pattern becomes closer to or farther from the memory cell array region.

16. The method of claim 1, wherein determining whether the second optical proximity correction is to be performed comprises:

determining whether the second pattern is within a tolerance based on the offset value and a direction and a magnitude of the difference value;

determining not to perform the second optical proximity correction if the second pattern is within the tolerance; and

determining that the second optical proximity correction is to be performed if the second pattern deviates from the tolerance.

17. A method of designing a layout of a stacked memory device, the method comprising:

checking a first position of a first pattern in an initial layout of a stacked memory device;

calculating an offset value of the first pattern according to the first position, the offset value representing an offset of the first pattern due to stress during a formation process of a memory cell array region of the stacked memory device;

obtaining a difference between the first position and a second position of a second pattern formed by a first Optical Proximity Correction (OPC) for the first pattern;

determining whether a second optical proximity correction is to be performed based on the offset value and the difference value; and

generating a final layout of the stacked memory device based on the second pattern or a third pattern formed by the second optical proximity correction.

18. The method of claim 17, wherein the stacked memory device includes the memory cell array region and a peripheral circuit region adjacent to the memory cell array region in a first direction, the first pattern including a contact pattern arranged in the peripheral circuit region.

19. The method of claim 18, wherein the first location comprises a Y-coordinate of the first pattern along the first direction.

20. The method as recited in claim 18, further comprising:

performing the first optical proximity correction on the first pattern before obtaining the difference; and

performing the second optical proximity correction on the second pattern prior to generating the final layout,

wherein performing the first optical proximity correction includes forming the second pattern by shifting the first pattern according to the first position so that the first pattern becomes closer to or farther from the memory cell array region, and performing the second optical proximity correction includes forming the third pattern by shifting the second pattern according to the first position so that the second pattern becomes closer to or farther from the memory cell array region.

21. A method of fabricating a stacked memory device, the method comprising:

designing a layout of the stacked memory device;

calculating an offset value of a first pattern from a first position of the first pattern in the layout, the offset value representing an offset of the first pattern due to stress during a formation process of a memory cell array region of the stacked memory device;

obtaining a difference between the first location and a second location of a second pattern formed by a first optical proximity correction to the first pattern;

determining whether a second optical proximity correction is to be performed based on the offset value and the difference value;

forming a mask based on the second pattern or a third pattern formed by the second optical proximity correction; and

22. The method of claim 21, wherein the stacked memory device includes the memory cell array region and a peripheral circuit region adjacent to the memory cell array region in a first direction, the first pattern including a contact pattern arranged in the peripheral circuit region.

23. The method of claim 22, wherein forming the mask comprises forming a mask for forming contacts according to the contact pattern.

24. The method of claim 23, wherein forming the stacked memory device comprises:

forming a transistor in the peripheral circuit region;

forming a plurality of memory cells in the memory cell array region; and

the contact connected to the transistor is formed by a photolithography process using the mask.

25. The method of claim 22, wherein the first location comprises a Y-coordinate of the first pattern along the first direction.