KR101508836B1 - 3d stacked semiconductor device and method for operating thereof - Google Patents

Abstract

A semiconductor device includes a semiconductor substrate and a plurality of layers vertically stacked on the semiconductor substrate. The semiconductor device divides and stores the data having the continuous address space in the first layer and the second layer adjacent to each other among the plurality of layers and divides the data into a first position of the stored first layer and a second position of the stored second layer Are not vertically adjacent. By making the positions of the plurality of layers of the semiconductor device in which data is stored not to be vertically adjacent to each other, the heat generated in the semiconductor device can be dispersed by repeated access to the data. It is possible to prevent hot spots from being generated in the semiconductor device and to prevent the occurrence of a physical failure in the semiconductor device.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device having a three-dimensional stacked structure and a method of operating the same.

The following description relates to a semiconductor device having a three-dimensional laminated structure, and more particularly to a semiconductor device having a three-dimensional laminated structure for dispersing heat generated by data access.

A three-dimensional chip stacking technique using a silicon via electrode (TSV) is a technique of vertically connecting a plurality of chip layers without using wire bonding or the like. By stacking a plurality of chip layers through the silicon penetrating electrode, an optimized signal transmission path can be provided between the stacked chips. In addition, since the wire bonding area between the chips to be stacked is not required, the three-dimensional chip stacking technique can have advantages in light weight shortening of the semiconductor device package.

The three-dimensional chip stacking technique can also be applied to the structure of a memory semiconductor device. That is to say, the memory chip layers can be stacked on top of the processor.

The power density of a three-dimensional stacked semiconductor device becomes higher as the number of stacked layers increases. Therefore, the heat generation problem of the semiconductor device of the three-dimensional laminated structure is more serious than the heat generation problem of the two-dimensional structure semiconductor device. The heat generation of the semiconductor device of the three-dimensional stacked structure can increase the leakage power and the capacitor leakage current. In a DRAM having a three-dimensional structure, the periodic refresh rate may increase with an increase in leakage current. By increasing the period refresh rate, the power consumption of the three-dimensional structure of the DRAM apparatus can be increased. In addition, the heat generation of the semiconductor device may cause a data error, and may cause a physical failure in the semiconductor device.

When data having a continuous address space is striped in a three-dimensionally stacked semiconductor device, the data is stored in the same columns of the plurality of layers of the semiconductor device. Here, the same column can mean the same number of columns. When data having a continuous address space in columns having the same number of layers is divided and stored and the semiconductor device repeatedly accesses data having a continuous address space, The heating points are concentrated in the vertical direction. When the heat generating points are concentrated in the vertical direction, the heat is intensively diffused in the vertical direction, so that hot spots can be generated in the semiconductor device and a physical failure can occur in the semiconductor device.

Korean Patent No. 1144159 (Published on May 14, 2012) discloses a 3-dimensional multicore processor to which a temperature management floor plan is applied. The prior art has proposed a temperature management floor plan that can prevent the generation of hot-spots by arranging the units of the processor cores to be stacked such that the units having a relatively large heating value are not located on the same vertical line Dimensional multi-core processor.

The information described above is for illustrative purposes only and may include content that does not form part of the prior art and may not include what the prior art has to offer to the ordinary artisan.

One embodiment of the present invention can provide a three-dimensional stacked structure semiconductor device in which data having a continuous address space is divided and stored, and an operation method thereof.

One embodiment can provide a three-dimensional stacked structure semiconductor device in which data including a plurality of chunks are divided and stored, and an operation method thereof.

There is provided a semiconductor device of a three-dimensional stacked structure, comprising: a semiconductor substrate; and a plurality of layers vertically stacked on the semiconductor substrate, the semiconductor device comprising: Wherein the first location of the first layer and the second location of the second layer are not vertically adjacent, wherein the first location of the first layer and the second location of the second layer are not vertically adjacent. Is provided.

The first location may be the first of the plurality of columns of the first layer.

The second location may be a second one of the plurality of columns of the second layer.

The number of the first column and the number of the second column may be different from each other.

The first location may be the first of the plurality of rows of the first layer.

The second location may be a second row of the plurality of rows of the second layer.

The number of the first column and the number of the second column may be different from each other.

Wherein the semiconductor device of the three-dimensionally stacked structure divides and stores the data at the first position and the second position that are not vertically adjacent to each other, thereby storing heat generated by consecutive approach to the data into the three- To the spaced apart locations in the semiconductor device.

The data may be ECC words.

The semiconductor device of the three-dimensionally stacked structure may strip the data so that regions of the plurality of layers in which the data is stored are not vertically adjacent to each other.

The regions may be shifted in the order in which the plurality of layers are stacked.

The regions may be columns of the plurality of layers.

The regions may be rows of the plurality of layers.

The semiconductor device of the three-dimensional laminated structure may further include a memory controller.

The plurality of layers may be n.

n may be an integer of 2 or more.

The memory controller may write the data including n chunks of the first to n-th chunks at a time.

The n chunks may be stored in the n layers, respectively.

The areas in which one of the n chunks in the n layers are stored may not be vertically adjacent to each other.

The data may further include an (n + 1) th chunk.

The first chunk and the (n + 1) th chunk may be stored in non-adjacent regions of the first layer among the n layers.

The semiconductor device of the three-dimensional laminated structure may further include an offset disperser that does not vertically adjoin the regions by applying different offsets to each of the n chunks.

The application of the offset may be performed for each chunk of the n chunks.

The application of the offset may be such that each chunk changes the number of columns to be stored in the layer.

In another aspect, a semiconductor device having a three-dimensional stacked structure including a semiconductor substrate and a plurality of layers stacked vertically on the semiconductor substrate is provided, wherein data having a continuous address space is provided between adjacent ones of the plurality of layers Dividing the first layer and the second layer into a first layer and a second layer, and accessing the divided stored data, wherein the data is divided into a first position of the first layer and a second position of the second layer, There is provided a method of operating a semiconductor device having a three-dimensional stacked structure, which is not vertically adjacent.

The storing step may include writing the data including n chunks of the first to n-th chunks.

The plurality of layers may be n.

n may be an integer of 2 or more.

The n chunks may be stored in the n layers, respectively.

The areas in which one of the n chunks in the n layers are stored may not be vertically adjacent to each other.

The storing may further comprise applying different offsets to each of the n chunks.

By applying the offset, the n chunks can be stored in regions that are not vertically adjacent to each other in the n layers.

There is provided a semiconductor device having a three-dimensional stacked structure and an operation method thereof, in which data having a continuous address space is divided and stored in a semiconductor device of a three-dimensional stacked structure so that heat generated by accessing data can be dispersed.

A three-dimensionally stacked structure capable of dispersing heat generating points generated by repeated access of data and preventing generation of hot-spots by dividing and storing data including a plurality of chunks in a three-dimensional stacked semiconductor device A semiconductor device and a method of operating the same are provided.

1 shows a semiconductor device of a three-dimensional stack structure in which data having a continuous address space is stored.
Fig. 2 shows the generation of heat in the semiconductor device of the three-dimensional laminated structure.
3 shows a semiconductor device of a three-dimensional laminated structure according to an embodiment.
4 illustrates layers in which data is stored among a plurality of layers according to an embodiment.
Fig. 5 shows dispersion of heat generation of a semiconductor device of a three-dimensional laminated structure according to an example.
6 shows data stored in a semiconductor device of a three-dimensional laminated structure according to an example.
7 shows a three-dimensional stacked semiconductor device including an offset disperser according to an example.
8 shows an example of offset application according to an example.
9 is a flowchart showing a method of operating a semiconductor device of a three-dimensional laminated structure according to an embodiment.
FIG. 10 is a flowchart illustrating a method of dividing and storing data having a continuous address space according to an exemplary embodiment into a first layer and a second layer adjacent to each other among a plurality of layers.

In the following, embodiments will be described in detail with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

Various modifications may be made to the embodiments and may have various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the description. It is to be understood, however, that the intention is not to limit the embodiments to the embodiments, but to include all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms used in the examples are used only to illustrate specific embodiments and are not intended to limit the embodiments. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this embodiment belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

In the following description of the present invention with reference to the accompanying drawings, the same components are denoted by the same reference numerals regardless of the reference numerals, and redundant explanations thereof will be omitted. In the following description of the embodiments, a detailed description of related arts will be omitted if it is determined that the gist of the embodiments may be unnecessarily blurred.

1 shows a semiconductor device of a three-dimensional stack structure in which data having a continuous address space is stored.

The semiconductor device 100 of FIG. 1 includes a plurality of layers stacked on a semiconductor substrate 110 and a semiconductor substrate 110. The plurality of layers may be vertically stacked layers on the semiconductor substrate 110. For example, four layers may be vertically stacked on the semiconductor substrate 110 as shown in FIG.

Data may be stored in each of the plurality of layers.

For example, data having a continuous address space may be stored in each of the plurality of layers.

Data having a contiguous address space stored in each of the plurality of layers may comprise a plurality of chunks. For example, data having a contiguous address space stored in each of a plurality of layers may be divided into four chunks as in FIG. That is to say, the chunks can be seen as being divided according to the layer in which the data with continuous address space is stored. A plurality of chunks may be stored in a plurality of layers, respectively.

In the semiconductor device 100, each of the four chunks may be stored at a location within the same layer of each of the four layers. That is to say, the four chunks can be stored in positions of a plurality of layers that are on the same vertical line. Alternatively, the location where each of the four chunks is stored may be vertically adjacent to the location of the adjacent layer in which the other of the four chunks is stored.

The term "vertical line" as used throughout this specification may be a line in the direction in which a plurality of layers are stacked. That is, the vertical line may be a line vertically penetrating a plurality of vertically stacked layers or a line parallel to the vertically penetrating line.

The devices constituting the semiconductor device, the structure of the semiconductor device, and the data stored in the semiconductor device will be described in more detail in the detailed description to follow.

Fig. 2 shows the generation of heat in the semiconductor device of the three-dimensional laminated structure.

Fig. 2 may represent the generation of heat in the semiconductor device 100 of Fig.

1, each of the plurality of chunks may be stored in the same location in each layer of the plurality of layers of the semiconductor device 100. [

The plurality of chunks may be part or all of the data having a contiguous address space. Thus, data having a continuous address space can be accessed by the semiconductor device 100 at the same time or almost simultaneously, or can be accessed by the semiconductor device 100 in succession. That is, a plurality of chunks stored in the plurality of layers of the semiconductor device 100 can be accessed by the semiconductor device 100 at the same time or at substantially the same time in succession.

The access of the semiconductor device 100 to the data may generate heat at the location where the data is stored. That is to say, the approach of the semiconductor device 100 to a plurality of chunks can generate heat at locations where a plurality of chunks are stored.

Also, for a plurality of chunks, if there is a repeated access of the semiconductor device 100, the heat generation at the location where the plurality of chunks are stored can be intensified.

Since the positions in the plurality of layers of the semiconductor device 100 in which the plurality of chunks are stored are present on the same vertical line, the above heat can be concentrated in the vertical direction.

As shown in FIG. 2, when heat is concentrated in the vertical direction, generated heat is intensively diffused in the vertical direction, so that hot spots can be generated in the semiconductor device 100, Physical failure may occur.

The devices constituting the semiconductor device, the structure of the semiconductor device, and the data stored in the semiconductor device will be described in more detail in the detailed description to follow.

3 shows a semiconductor device of a three-dimensional laminated structure according to an embodiment.

The semiconductor device 300 of the three-dimensional stacked structure may include a semiconductor substrate 110, a plurality of layers 310, and a memory controller 320.

The semiconductor device 300 may be a memory semiconductor device. For example, the semiconductor device 300 may be a DRAM semiconductor device.

The semiconductor substrate 110 may be composed of elements such as silicon (Si), germanium (Ge), gallium phosphorus (GaP), and gallium arsenide (GaAs).

A plurality of semiconductor elements may be integrated in one semiconductor substrate 110. The plurality of semiconductor elements may be stacked on the semiconductor substrate 110 in a three-dimensional structure. The plurality of semiconductor elements to be stacked may be a plurality of semiconductor chips.

The plurality of layers 310 may be layers deposited on the semiconductor substrate 110. For example, the plurality of layers 310 may be a plurality of layers 310 stacked vertically on a semiconductor substrate 110. The number of the plurality of layers 310 to be stacked on the semiconductor substrate 110 may be n. n may be an integer of 2 or more. The plurality of layers 310 may be sequentially stacked on the semiconductor substrate 110 during the fabrication of the semiconductor device 300.

The plurality of layers 310 may be stacked vertically on the semiconductor substrate 110 through the silicon penetrating electrode.

Each shape of the plurality of layers 310 may be a two-dimensional plane.

Each of the plurality of layers 310 may be a semiconductor device for storing data. In addition, each of the plurality of layers 310 may comprise a semiconductor device and may include circuitry for accessing data stored in the semiconductor device.

Each of the plurality of layers 310 may be a memory chip. For example, each of the plurality of layers 310 may be a DRAM chip vertically stacked on the semiconductor substrate 110. In addition, each of the plurality of layers 310 may include a memory chip and may include input / output lines to the memory chip.

Each of the plurality of layers 310 may comprise a plurality of memory cells. The semiconductor device or memory chip, which each of the plurality of layers 310 includes, may include a plurality of memory cells. Alternatively, the semiconductor element or the memory chip may be composed of a plurality of memory cells.

The memory cell may be an electronic circuit or a semiconductor device used to store a single bit. That is to say, each of the plurality of layers 310 may store data bit by bit.

Each of the plurality of layers 310 may include an independent address space. That is to say, the plurality of layers 310 may correspond to different address spaces, respectively.

The data stored in the plurality of layers 310 may be data having a contiguous address space. That is to say, the data can correspond to a continuous address space. Data may be stored in an area corresponding to a continuous address space of the plurality of layers 310. [

 If the address space of the data is continuous, the locations where the data are stored may be physically continuous. Alternatively, if the address space of the data is continuous, the locations where the data is stored may be logically contiguous.

Data having a contiguous address space may be divided and stored in some of the plurality of layers 310. The layers of the plurality of layers 310 in which data having a contiguous address space is stored may be adjacent layers.

For example, the semiconductor device 100 may divide and store data having a continuous address space in the first layer and the second layer, which are adjacent to each other, of the plurality of layers 310.

The first and second layers adjacent to each other may be any two adjacent layers selected from the plurality of layers 310 according to the address space of the data.

The data having the continuous address space may be divided and stored in the first position of the first layer and the second position of the second layer. The first position and the second position may be positions existing in the first layer and the second layer, respectively. The positions in the layers of the first position and the second position may be different from each other. That is to say, the first position and the second position may be positions that are in different layers from each other and that are not on the same vertical line. That is, the first location of the first layer and the second location of the second layer may not be vertically contiguous.

When the first position and the second position are vertically adjacent, the separation distance between the first position and the second position may be minimum. In other words, when the distance between the first position and the second position is minimized, the first position and the second position may be vertically adjacent.

The data can be divided and stored at the first position and the second position at which the distance between the first position and the second position becomes the maximum. For example, the semiconductor device 300 may divide and store data having a continuous address space in a first position of the first layer and a second position of the second layer that maximizes the separation distance from the first position.

The first and second locations may be physical locations within the first and second layers. Alternatively, the first location and the second location may be logical locations within the first and second layers.

Logical locations may be locations formed by logical addresses. That is to say, the first location and the second location may be logical locations within the address space corresponding to the first and second layers. Alternatively, the first location and the second location may be physical locations of the portion where data is actually stored in the layer. The logical location and the physical location may correspond to each other. That is to say, the larger the value representing the logical position, the larger the value representing the physical position. Here, the value indicating the logical location may be an address in the address space. The value representing the physical location may be a value indicating a specific part of the semiconductor device, the memory chip or the storage space of the memory cell, such as the number of the column, the number of the row and the number of the way.

The separation distance between the first position and the second position may be a physical distance between the first position and the second position. Alternatively, the distance between the first position and the second position may be a logical distance between the first position and the second position.

As shown in FIG. 3, the first layer and the second layer may be the kth layer and the (k + 1) th layer of the plurality of layers 310, respectively. k may be an integer of n-1 or less and 1 or more. That is to say, the k-th layer and the (k + 1) th layer may be selected from any two adjacent layers among the n-number of the layers 310.

The first position and the second position may be respectively present in the k-th layer and the (k + 1) th layer.

A memory controller 320 may control each of the plurality of layers 310. The memory controller 320 may access data stored in the plurality of layers 310. [ For example, the memory controller 320 may access data having a contiguous address space of the entire data stored in the plurality of layers 310. [ The memory controller 320 is described in further detail in the detailed description that follows.

4 illustrates layers in which data is stored among a plurality of layers according to an embodiment.

The first layer 410 and the second layer 420 may correspond to the first and second layers, respectively, described above with reference to FIG. The first layer 410 and the second layer 420 may be any two adjacent layers of the plurality of layers 310. For example, the first layer 410 and the second layer 420 may be layers in which data having a continuous address space among the plurality of layers 310 is divided and stored.

The first layer 410 and the first layer 420 may each include a plurality of columns. The first layer 410 and the second layer 420 may each comprise m columns. m may be an integer of 2 or more.

Each column of the plurality of columns may comprise a plurality of memory cells.

Data may be stored in each column of the plurality of columns.

For example, data having a continuous address space may be divided and stored in each column of the first layer 410 and the second layer 420. In other words, data having a continuous address space may be divided and stored in the first column 430 of the first layer 410 and the second column 440 of the second layer 420. The first column 430 and the second column 440 may correspond to the first and second positions described above with reference to FIG.

The first column 430 and the second column 440 may be one of a plurality of columns of the first layer 410 and the second layer 420, respectively. Each column of a plurality of columns may have a unique column number. The number of the column may be a value indicating the order of the corresponding column. That is to say, the number of the column can correspond to the position of the column.

The number of the first column 430 and the number of the second column 440 may be different from each other. When the number of the first column 430 and the number of the second column 440 are different from each other, the first column 430 and the second column 440 may not be vertically adjacent.

The location at which data is stored may be represented as columns and rows, and the columns and rows may correspond to physical locations within the layers. For example, the number of the columns may correspond to the coordinates of the x-axis of the physical location, and the number of the rows may correspond to the coordinates of the y-axis of the physical location.

3, the first location described above with reference to FIG. 3 may represent the first column 430 of the plurality of columns of the first layer 410. In addition, the second location may represent the second column 440 of the plurality of columns of the second layer 420.

Because the first and second locations may not be vertically adjacent, the number of the first column 430 and the number of the second column 440 may be different from each other. In addition, maximizing the separation distance between the first position and the second position may be to maximize the difference in the number of the columns between the first column 430 and the second column 440.

For example, data having a contiguous address space may be stored in two columns that have a maximum difference in number between columns. That is to say, the semiconductor device 300 can divide and store data having a continuous address space into two columns having a maximum difference in number between the columns.

According to the embodiment, the above-mentioned "column" can be replaced by "row ". Alternatively, the above-described "row" may be replaced by a "column ". For example, the terms "column" and the term "row" used throughout this specification may be used interchangeably.

For example, the above description may be based on the assumption that one chunk is stored in one column. That is to say, continuous data is stored in one column once and large data that can not be stored in one column can be stored in a plurality of columns of the plurality of layers 310, separated into a plurality of chunks.

On the other hand, when one chunk is stored in one row, "column" and "row" in the above description can be replaced with each other. That is to say, continuous data is once stored in one row, and large data that can not be stored in one row can be stored in a plurality of rows of a plurality of layers 310, separated into a plurality of chunks. That is to say, the first location may be the first of the plurality of rows of the first layer. Also, the second location may be the second row of the plurality of rows of the second layer. Since the first position and the second position may not be vertically adjacent, the numbers of the first row and the numbers of the second row may be different from each other.

The technical contents described with reference to Figs. 1 to 3 can be applied as it is, and a detailed description will be omitted below.

Fig. 5 shows dispersion of heat generation of a semiconductor device of a three-dimensional laminated structure according to an example.

As described above with reference to FIGS. 1 and 2, when positions in a plurality of layers in which data having a continuous address space is stored are present on the same vertical line, access to the data of the semiconductor device 100 of FIG. The heat generated by repeating can be concentrated in the vertical direction of the locations where the data is stored. The heat concentrated in the vertical direction can cause hot spots in the semiconductor device 100 or cause a physical failure in the semiconductor device 100. [

By causing the locations in the plurality of layers in which data having a contiguous address space to be stored are not vertically adjacent as described above with reference to FIGS. 3 and 4, the heat generated by the access of the data by the semiconductor device 300 Points can be dispersed. By dispersing the heat generating points, concentration of heat in the vertical direction can be prevented from being concentrated. It is possible to prevent hot spots from being generated in the semiconductor device 300 and to prevent a physical failure from occurring in the semiconductor device 300 by preventing concentration of heat diffusion in the vertical direction.

5 illustrates a plurality of layers 310 of semiconductor device 300 in which data is stored when the value of n described above with reference to FIG. 3 is 4 and is generated by accessing data of semiconductor device 300 Lt; / RTI >

Any two adjacent layers of the four plurality of layers 310 may correspond to the first and second layers described above with reference to FIG.

Alternatively, any two adjacent layers of the four multiple layers 310 may correspond to the k-th layer and the (k + 1) th layer described above with reference to FIG.

For example, within any two adjacent layers of four of the plurality of layers 310, the locations where the data having the contiguous address space is divided and stored may not be vertically adjacent.

That is to say, in the four multiple layers 310, data having a contiguous address space may not be partitioned and vertically adjacent among the stored locations. That is, the positions where the data having the continuous address space are stored in the four plural layers 310 may not be vertically adjacent to each other.

Therefore, by dividing and storing the data having the continuous address space at the first position and the second position which are not vertically adjacent, the heat generated by the continuous approach to the data can be stored in the semiconductor device 300 at a distance from each other.

By dividing and storing the data having the continuous address space at the first position and the second position at which the distance between the first position and the second position is the maximum, the semiconductor device 300 is generated by accessing the above- The heating points can be dispersed as much as possible.

For example, by dividing and storing data having a continuous address space in a first position that is not vertically adjacent and a second position that maximizes a separation distance from the first position, the heat generated by successive approach to the data Can be dispersed at mutually spaced positions in the semiconductor device 300 of the three-dimensional stacked structure.

As described above with reference to FIG. 4, the numbers of the columns corresponding to the positions where the data of the four plural layers 310 of FIG. 5 are stored may be different from each other.

For example, in all the two adjacent layers of the four multiple layers 310, the columns of data having a contiguous address space may not be vertically contiguous. That is to say, the number of columns in which the data having a continuous address space in the four multiple layers 310 is divided and stored may be different from each other.

That is, by dividing and storing the data having the continuous address space into the first column and the second column that are not vertically adjacent to each other, the heat generated by the successive approach to the data is stored in the three- 300 at a distance from each other.

Alternatively, the data having the continuous address space is divided and stored in the first column and the second column in which the numbers of the columns are different from each other, so that the heat generated by the successive approach to the data is stored in the three- And can be dispersed into spaced locations.

The heating points generated by the access to the data of the semiconductor device 300 can be dispersed to the maximum by storing the data at the first position and the second position at which the distance between the first column and the second column becomes the maximum . That is to say, for dispersion of the heating points, the difference between the numbers of the columns between the first column and the second column can be maximum.

For example, the semiconductor device 300 may divide and store data having a continuous address space into a first column and a second column that have a maximum difference in the number of columns between the first column and the second column, The heat generated by the approach can be dispersed to the mutually spaced positions in the semiconductor device of the three-dimensional laminated structure.

By using the semiconductor device 300 of this embodiment, heat generated in the semiconductor device 300 can be dispersed by repeated access to data. Also, by preventing the concentration of thermal diffusion in the vertical direction, it is possible to prevent hot spots from being generated in the semiconductor device and to prevent the occurrence of a physical failure in the semiconductor device.

Further, deterioration in the performance of the semiconductor device 300, such as an increase in leakage power and occurrence of a data error, which may be caused by a heat generation problem, can be prevented.

The technical contents described above with reference to Figs. 3 to 4 can be applied as they are, so a more detailed description will be omitted below.

6 shows data stored in a semiconductor device of a three-dimensional laminated structure according to an example.

The data 610 may be data having a contiguous address space that is divided and stored in the plurality of layers 310 of FIG.

Data 610 may comprise a plurality of bits.

The data 610 may be error correction code (ECC) words.

The ECC word can be used for correction of a 1-bit data error and detection of 2-bit data error (SEC / DED). That is to say, a 2-bit data error can be detected by the ECC word, and a 1-bit data error can be corrected by using the ECC word.

The data 610 may be stripped to regions of the plurality of layers 310. [ For example, the data 610 may be striped into regions of each layer of the plurality of layers 310 by being divided into uniform sizes.

Data 610 may be striped into regions of adjacent ones of the plurality of layers 310. [

For example, data 610 may be striped into a first region of the first layer and a second region of the second layer of FIG. The first area of the first layer and the second area of the second layer where the data 610 is striped may correspond to the first and second positions described above with reference to Fig.

As described above in Fig. 3, the first position and the second position may be positions that are not vertically adjacent. That is, the first area and the second area may be areas that are not vertically adjacent.

That is, the semiconductor device 300 of the three-dimensional stacked structure may strip the data 610 so that the regions of the plurality of layers 310 where the data 610 is stored are not vertically adjacent to each other.

In addition, the first region of the first layer and the second region of the second layer, to which the data 610 is striped, may correspond to the first and second columns described above with reference to Fig. In other words, the areas in which the data 610 are striped may be the columns of the plurality of layers 310.

Data 610 may comprise a plurality of chunks.

The number of chunks may be n. That is to say, the number of chunks included in the data 610 may be equal to the number of layers included in the plurality of layers 310.

The size of the chunks can be uniform.

For example, the chunks may be evenly partitioned according to the address value of the data 610 having a contiguous address space.

The n chunks included in the data 610 may have a predetermined order of 1 to n. For example, the order may be an order determined according to an address value of data 610 having a contiguous address space.

The chunk may be part or all of data 610. Each of the plurality of chunks may comprise a plurality of bits.

Each of the plurality of chunks may be data of an ECC word.

The data stored in each layer of the plurality of layers 310 in FIG. 3 may be a chunk corresponding to each layer of the plurality of chunks.

For example, n chunks may be stored in n layers, respectively.

the areas where one of the n chunks in the n layers are stored may not be vertically adjacent to each other. That is to say, the areas of the plurality of layers 310 where one of the n chunks is stored may be on different vertical lines from each other.

The semiconductor device 300 may store a chunk stored in any one of the plurality of layers 310 in a region where the separation distance from the chunk stored in the region of the layer adjacent to the arbitrary layer becomes maximum.

Alternatively, the semiconductor device 300 may have a structure in which the number of the column corresponding to the area where the chunks of any layer among the plurality of layers 310 are stored and the number of the column corresponding to the area where the chunk of the layer adjacent to the arbitrary layer is stored The difference between the numbers can be maximized.

The memory controller 320 of FIG. 3 may access the data stored in the plurality of layers 310 in a divided manner. For example, the memory controller 320 may access the data stored in the plurality of layers 310 at the same time or sequentially.

That is, the memory controller 320 can write or read data including n chunks of the first to n-th chunks at a time.

The data 610 may further include an (n + 1) th chunk 620.

The (n + 1) th chunk 620 may be stored in any area of one of the plurality of layers 310. [ For example, the (n + 1) th chunk 620 may be stored in the first layer among the plurality of layers 310. [ When the (n + 1) -th chunk 620 is stored in the first layer, the area in the first layer where the (n + 1) -th chunk is stored may not be adjacent to the area in which the first chunk is stored.

When the (n + 1) -th chunk 620 is stored in the first layer, the area in the first layer where the (n + 1) -th chunk 620 is stored is the area in which the chunk of the layer adjacent to the first layer is stored And may not be vertically adjacent to the region.

That is, the first chunk and the (n + 1) th chunk 620 may be stored in non-adjacent regions of the first layer among the n layers.

If the data 610 has n + x chunks, each of the (n + 2) th through (n + x) th chunks may be stored in a region of one of the plurality of layers 310 . For example, each of the (n + 2) th to (n + x) th chunks may be sequentially stored according to the stacked order of the second layer to the nth layer.

When the (n + x) th chunk is stored in the area of the xth layer, the area where the (n + x) th chunk is stored may not be adjacent to the area where the xth chunk is stored. When the (n + x) th chunk is stored in the region of the xth layer, the region where the (n + x) th chunk 620 is stored is adjacent to the region where the chunk of the layer adjacent to the .

That is to say, the xth chunk and the (n + x) th chunk may be stored in non-adjacent regions of the xth layer of the n layers.

If x is an integer greater than n, each of the (2 + n + 1) th to (n + x) th chunks may be sequentially stored again from the first layer.

For example, areas of each layer of the plurality of layers 310 in which the chunks are stored may not be adjacent to each other.

Also, each of the areas of each layer of the plurality of layers 310 in which the chunks are stored may not be vertically adjacent to the areas in which the chunks of the adjacent layer (s) are stored.

The technical contents described above with reference to Figs. 3 to 4 can be applied as they are, so a more detailed description will be omitted below.

7 shows a three-dimensional stacked semiconductor device including an offset disperser according to an example.

As described above with reference to FIGS. 3, 4 and 6, the plurality of layers 310 of FIG. 3 may include four layers. That is to say, the value of n may be four.

Since the value of n is 4, the data 610 may include four chunks.

In addition, each layer of the plurality of layers 310 may comprise ten columns. That is to say, the value of m may be 10.

The semiconductor device 300 of FIG. 3 may include an offset disperser 710.

The offset may be a relative address value for representing the relative position of the data in the memory device.

Offset spreader 710 may apply an offset to each of a plurality of chunks of data 610 having a contiguous address space to be stored in each layer of the plurality of layers 310. [

The memory controller 320 may write data having a contiguous address space that includes chunks in the plurality of layers 310 according to the offset value applied to each chunk.

Applying an offset to each of the plurality of chunks may be to assign each of the plurality of chunks an address relative to the area of each layer of the plurality of layers 310 in which each of the plurality of chunks is to be stored.

Offset spreader 710 may apply different offsets to each of the plurality of chunks. If different offsets are applied to each of the plurality of chunks stored in each of the plurality of layers 310 by the offset spreader 710, then the area of each layer where each chunk is stored is stored in the chunks of adjacent layers And may not be vertically adjacent to the region.

For example, the offset spreader 710 may apply different offsets to each of the n chunks that the data 610 includes so that the areas where each of the n chunks is stored are not vertically adjacent to each other.

Applying an offset to each of the plurality of chunks may be to assign a number of columns corresponding to regions of each layer of the plurality of layers 310 in which each of the plurality of chunks is to be stored.

For example, the application of the offset may be for each chunk of the n chunks, each chunk changing the number of columns to be stored in the layer.

The offset spreader 710 may assign a different number of columns to each of the plurality of chunks. If a different number of columns is assigned for each of the plurality of chunks stored in each of the plurality of layers 310 by the offset spreader 710, the area of each layer where each chunk is stored is stored And may not be vertically adjacent to the region to be formed.

The technical contents described above with reference to FIGS. 3 to 6 may be applied as they are, so a more detailed description will be omitted below.

8 shows an example of offset application according to an example.

As described above with reference to FIG. 7, the plurality of layers 310 may comprise four layers.

And the first to fourth layers may represent the first to fourth layers, respectively. Alternatively, the first to fourth layers may respectively represent the fourth layer to the first layer.

Data 610 having a contiguous address space may include four chunks.

Each layer of the plurality of layers 310 may comprise ten columns.

The offset spreader 710 of FIG. 7 may apply different offsets to each of the plurality of chunks.

By applying different offsets to each of the plurality of chunks, regions of the plurality of layers 310 in which a plurality of chunks are stored can be shifted according to the offsets applied to each of the plurality of chunks.

As shown in FIG. 8, the areas in which each of the chunks is stored for each layer of the plurality of layers 310 may be differentially shifted.

The regions in which each of the chunks is stored may be shifted 810 according to the order in which the plurality of layers 310 are stacked. Here, the areas where each of the chunks is stored may be shifted in a predetermined direction, and may be shifted at regular intervals. On the other hand, the regions in which each of the chunks is stored may be shifted at different intervals based on the temperature distribution or policy of managing the data.

Here, the shift may be that each chunk changes the number of columns to be stored in the layer.

For example, the number of the column in the area in which the chunk to be stored in the tth layer is to be stored may be increased by 2 * t. t may be an integer of 1 or more and n or less. If the shifted 2 * t is greater than the last number m of the column, the number of the column of the area in which the chunk is to be stored may be increased again from the first column corresponding to the difference between 2 * t and m.

The chunk of data 610 stored in layer t may be the t-th chunk.

Considering the case where n is 4 and m is 10 in FIG. 8, the first chunk may be stored in the third column of the first layer. And the second chunk may be stored in the fifth column of the second layer. And the third chunk may be stored in the seventh column of the third layer. The fourth chunk may be stored in the ninth column of the fourth layer.

Also, the data 610 may include a fifth chunk 620.

The fifth chunk 620 may be stored in a column of one of the first through fourth layers.

For example, the fifth chunk 620 may be stored in the first layer. When the fifth chunk 620 is stored in the first layer, the column in which the fifth chunk is stored may not be adjacent to the area in which the first chunk is stored.

When the fifth chunk 620 is stored in the first layer, the column storing the fifth chunk 620 is perpendicular to the area where the second chunk of the second layer adjacent to the first layer is stored It may not be adjacent.

The technical contents described above with reference to FIGS. 3 to 7 can be applied as they are, so a more detailed description will be omitted below.

9 is a flowchart showing a method of operating a semiconductor device of a three-dimensional laminated structure according to an embodiment.

In step 910, a three-dimensional stacked semiconductor device 300 including a semiconductor substrate 110 and a plurality of layers 310 stacked vertically on a semiconductor substrate is patterned to include data 610 having a contiguous address space, May be divided and stored in the first layer and the second layer adjacent to each other among the plurality of layers 310. [

In step 910, the first and second layers may correspond to the first and second layers, respectively, described above with reference to Fig.

Alternatively, the first and second layers may correspond to the layers 410 and 420 described above with reference to FIG. 4, respectively.

In step 910, the first location of the first layer and the second location of the second layer, where the data 610 is stored in a segmented manner, may not be vertically contiguous.

In other words, the semiconductor device 300 can transfer data 610 having a contiguous address space to the first and second adjacent layers of the plurality of layers 310, Position and the second position of the second layer, respectively

Further, the data 610 may be divided and stored at a first position and a second position at which the distance between the first position and the second position is the maximum. For example, the semiconductor device 300 may divide and store data having a continuous address space in a first position of the first layer and a second position of the second layer that maximizes the separation distance from the first position.

In step 920, the semiconductor device 300 may access the data stored in a divided manner.

Step 920 may also be performed by the memory controller 320 of FIG.

That is, the memory controller 320 can access the data stored in the device 300 in a divided manner.

In steps 910 and 920, the data stored in the plurality of layers 310 may be a plurality of chunks that the data 610 includes.

The technical contents described above with reference to Figs. 3 to 6 can be applied as they are, so that a more detailed description will be omitted below.

FIG. 10 is a flowchart illustrating a method of dividing and storing data having a continuous address space according to an exemplary embodiment into a first layer and a second layer adjacent to each other among a plurality of layers.

Step 910 described above with reference to FIG. 9 may include steps 1010 and 1020 described below.

As described above in FIG. 3, the number of the plurality of layers 310 may be n. Also, n may be an integer of 2 or more.

6, data 610 having a contiguous address space may include n chunks. Also, the n chunks included in the data 610 may have a predetermined order of 1 through n.

7, the semiconductor device 300 of FIG. 3 may include an offset spreader 710. The offset spreader 710 may be implemented using any suitable technique.

At step 1010, the offset distributor 710 may apply different offsets to each of the n chunks.

The memory controller 320 may write data including a plurality of chunks to the plurality of layers 310 according to the offset value applied to each chunk.

By applying different offsets to each of the n chunks, the n chunks may be stored in regions that are not vertically adjacent to each other in the n layers.

In step 1020, the semiconductor device 300 may write data including n chunks of the first through n-th chunks.

Step 1020 may also be performed by the memory controller 320 of FIG.

That is, the memory controller 320 may write the data including n chunks of the first to n-th chunks.

In step 1020, n chunks may be stored in each of the n layers.

For example, the first to n-th chunks may be stored in the first to n-th layers, respectively.

Also, the areas in which one of the n chunks in the n layers are stored may not be vertically adjacent to each other.

By applying different offsets to each of the n chunks by the offset spreader 710, each of the n chunks may be stored in areas that are not vertically adjacent to each other in each layer of the plurality of layers 310 have.

The technical contents described above with reference to FIGS. 3 to 9 may be applied as they are, so that a more detailed description will be omitted below.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

300: semiconductor device
310: a plurality of layers
320: memory controller
610: Data
710: Offset disperser

Claims (16)

In a semiconductor device having a three-dimensional stacked structure,
A semiconductor substrate;
A memory controller; And
A plurality of vertically stacked layers on the semiconductor substrate
/ RTI >
Wherein the semiconductor device divides and stores data having a continuous address space in first and second layers adjacent to each other among the plurality of layers,
Wherein the first location of the first layer and the second location of the second layer are not vertically adjacent,
Wherein the plurality of layers are n,
n is an integer of 2 or more,
Wherein the memory controller writes the data including n chunks of the first to n < th > chunks at a time,
The n chunks are stored in each of the n layers,
Areas in which one of the n chunks in the n layers are stored are not vertically adjacent to each other,
Wherein the data further includes an (n + 1) < th >
Wherein the first chunk and the (n + 1) th chunk are stored in non-adjacent regions of the first layer among the n layers. The method according to claim 1,
The first location being the first of the plurality of columns of the first layer,
The second location being a second one of the plurality of columns of the second layer,
Wherein the number of the first column and the number of the second column are different from each other. The method according to claim 1,
Wherein the first location is a first row of the plurality of rows of the first layer,
The second location being a second row of the plurality of rows of the second layer,
Wherein the number of the first column and the number of the second column are different from each other. The method according to claim 1,
Wherein the semiconductor device of the three-dimensionally stacked structure divides and stores the data at the first position and the second position that are not vertically adjacent to each other, thereby storing heat generated by consecutive approach to the data into the three- Dimensional semiconductor device having a three-dimensional stacked structure in which the semiconductor devices are dispersed at mutually spaced positions in a semiconductor device of a three- The method according to claim 1,
The data is ECC words, and the semiconductor device The method according to claim 1,
Wherein the semiconductor device of the three-dimensional laminated structure strips the data so that regions of the plurality of layers in which the data is stored are not vertically adjacent to each other. The method according to claim 6,
Wherein the regions are shifted in the order in which the plurality of layers are stacked. The method according to claim 6,
Said regions being columns of said plurality of layers. The method according to claim 6,
Said regions being rows of said plurality of layers. delete delete The method according to claim 1,
And applying offset different from each other for each of the n chunks so that the regions are not vertically adjacent to each other.
Wherein the semiconductor device further comprises: 13. The method of claim 12,
Wherein application of the offset changes the number of columns to be stored in each layer for each chunk of the n chunks. A semiconductor device having a three-dimensional stacked structure including a semiconductor substrate and a plurality of layers vertically stacked on the semiconductor substrate,
Dividing and storing data having a continuous address space in first and second layers adjacent to each other among the plurality of layers; And
Accessing the divided stored data
Lt; / RTI >
Wherein the first location of the first layer and the second location of the second layer are not vertically adjacent,
Wherein the storing step comprises:
applying different offsets to each of the n chunks
Further comprising:
Wherein the application of the offset causes the n chunks to be stored in regions that are not vertically adjacent to each other within the n layers. 15. The method of claim 14,
Wherein the storing step comprises:
Writing the data including n chunks of the first through n-th chunks
Lt; / RTI >
Wherein the plurality of layers are n,
n is an integer of 2 or more,
The n chunks are stored in each of the n layers,
Wherein regions in which one of the n chunks in the n layers are stored are not vertically adjacent to each other. delete

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