CN112859508A - Method for manufacturing integrated circuit - Google Patents
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- CN112859508A CN112859508A CN201911182217.8A CN201911182217A CN112859508A CN 112859508 A CN112859508 A CN 112859508A CN 201911182217 A CN201911182217 A CN 201911182217A CN 112859508 A CN112859508 A CN 112859508A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
Abstract
Embodiments of the invention relate to integrated circuit fabrication methods. A method of manufacturing an integrated circuit, comprising: receiving an initial integrated circuit design layout, wherein the initial integrated circuit design layout comprises m x n integrated circuit regions which are arranged into an array of m columns and n rows, and the same initial integrated circuit pattern is contained in each integrated circuit region; respectively carrying out first Optical Proximity Correction (OPC) on the initial integrated circuit patterns in each integrated circuit region, wherein the first POC comprises m x n x (l-1) repeated operations; defining a plurality of integrated circuit regions arranged in the same column in the array as a same group; and performing a second OPC in groups to obtain a corrected integrated circuit design layout.
Description
Technical Field
The present invention relates to integrated circuit manufacturing methods, and more particularly, to an integrated circuit manufacturing method using Optical Proximity Correction (OPC).
Background
Technological advances in the design and processing of semiconductor Integrated Circuits (ICs) have gone through several generations of ICs, each with smaller dimensions and more complex circuits than previous generations. As IC development progresses, as functional density (e.g., interconnected devices per chip area) increases, the geometries shrink as well.
This process of scaling down is accompanied by the benefits of increased manufacturing efficiency, reduced production costs, etc., but the scaling down also increases the complexity of the process. For example, as line widths (line widths) become smaller, the pattern of features transferred from the mask to the wafer may be distorted as the photolithography process proceeds. To avoid these optical effects, the semiconductor industry compensates the mask pattern by modifying it, for example, using OPC to modify the mask pattern so that the circuit pattern created after photolithography is the same as the desired circuit pattern, while allowing semiconductor fabrication techniques to fabricate more advanced devices. OPC has been a necessary procedure in all integrated circuit processes for semiconductor processing into deep sub-micron to today's nano-processes.
Distortions and offsets to be corrected by known OPCs may include pinching (necking), necking (necking), bridging (bridging), dishing (deforming), line corner rounding (line corner rounding), line density and line depth focus variations, and the like. The ultimate goal of OPC is to achieve the ability to produce smaller component patterns in IC designs through improved mask pattern transfer techniques using inherent equipment. OPC techniques systematically vary the mask pattern dimensions to modify the shape of the design pattern or to insert assist features to compensate for distortions caused by optical diffraction and scattering in the lithography process.
However, although the OPC technology has been greatly improved and evolved from the conventional rule-based OPC technology to the model-based OPC technology which can provide higher accuracy, the technology still has certain limitations, such as failing to meet the requirement of the exposure process into Extreme Ultraviolet (EUV), and obviously consuming more time to process each of the multiple physical circuit layers and each of the multiple chip units.
Disclosure of Invention
According to some embodiments of the invention, there is provided a method of manufacturing an integrated circuit. The method comprises the following steps: receiving an initial integrated circuit design layout, wherein the initial integrated circuit design layout comprises m x n integrated circuit regions which are arranged into an array of m columns and n rows, and the same initial integrated circuit pattern is contained in each integrated circuit region; performing a first Optical Proximity Correction (OPC) on the initial integrated circuit patterns in each integrated circuit region, wherein the first OPC comprises m × n (l-1) repeated operations (iterations); defining a plurality of integrated circuit regions arranged in the same column in the array as a same group; and performing a second OPC in groups to obtain a corrected integrated circuit design layout.
According to some embodiments of the present invention, there is also provided a method of manufacturing an integrated circuit. The method comprises the following steps: receiving an initial integrated circuit design layout, wherein the initial integrated circuit design layout comprises m x n integrated circuit regions which are arranged into an array of m columns and n rows, and the same initial integrated circuit pattern is contained in each integrated circuit region; defining a plurality of integrated circuit regions arranged in the same column in the array as a same group; grouping and carrying out first OPC; and respectively carrying out second OPC on each integrated circuit region to obtain the corrected integrated circuit design layout. The second OPC comprises m × n (l-1) repeated operations.
There is further provided, in accordance with some embodiments of the present invention, a method for manufacturing an integrated circuit. The method comprises the following steps: receiving an initial integrated circuit design layout, wherein the initial integrated circuit design layout comprises m x n integrated circuit regions which are arranged into an array of m columns and n rows, and the same initial integrated circuit pattern is contained in each integrated circuit region; performing first OPC on the initial integrated circuit patterns in each integrated circuit region respectively, wherein the first OPC comprises m × n × l-1 repeated operations in total; defining a plurality of integrated circuit regions arranged in the same column in the array as a same group to obtain m integrated circuit region groups; grouping a second OPC which corrects the slit effect to obtain a plurality of corrected integrated circuit patterns, wherein the corrected integrated circuit patterns form a corrected integrated circuit design layout, and the second OPC comprises m times of repeated operations; and outputting the corrected integrated circuit design layout to a mask.
Drawings
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various components are not drawn to scale in accordance with conventional practice in the industry. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 is a simplified block diagram of an integrated circuit manufacturing system and an IC production flow associated with the integrated circuit manufacturing system.
FIG. 2 is a schematic diagram of an initial design layout of an integrated circuit.
Fig. 3 is a schematic diagram of image deformation caused by the slit effect.
Fig. 4 is a flow chart illustrating a method for manufacturing an integrated circuit according to the present disclosure.
Fig. 5 is a flow chart illustrating a method for manufacturing an integrated circuit according to the present disclosure.
Fig. 6-10 are schematic diagrams of stages in a method of fabricating an integrated circuit according to some embodiments of the present disclosure.
Fig. 11-14 are schematic diagrams of stages in a method of fabricating an integrated circuit according to some embodiments of the present disclosure.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, such are merely examples and are not intended to be limiting. For example, in the following description, "forming a first member over or on a second member" may include embodiments in which the first member and the second member are formed in direct contact, and may also include embodiments in which additional members may be formed between the first member and the second member such that the first member and the second member may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms (e.g., "below," "lower," "above," "upper," and the like) may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s), as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, terms such as "first," "second," and "third" describe various elements, components, regions, layers, and/or sections, and such elements, components, regions, layers, and/or sections should not be limited by such terms. Such terms may be used only to define elements, components, regions, layers, or sections to one another. Terms such as "first," "second," and "third," as used herein, do not imply a sequence or order unless clearly indicated by the context.
Referring to FIG. 1, FIG. 1 is a simplified block diagram of an Integrated Circuit (IC) manufacturing system 10 and an IC production flow associated with the IC manufacturing system. The integrated circuit manufacturing system 10 includes a number of physical entities (entities), such as a design house 110, a mask room 120, and an integrated circuit fab 130. The aforementioned physical mechanisms interact with each other during design, development, and manufacturing cycles and/or during the manufacture of services (services) associated with the integrated circuit device 140. The entity mechanisms can be connected by a communication network (e.g., a single network) or various networks, such as an intranet (internet) or the internet, and can include wired or wireless communication channels. Each entity may interact with and be serviced or received by other entity organizations. One or more design companies 110, mask chambers 120, and/or integrated circuit fabs 130 may be owned by a single large company, and may even exist in a common facility and use common resources.
The design company 110 generates an integrated circuit design layout (IC design layout)112, also referred to as an IC design pattern 112. The integrated circuit design layout 112 includes various circuit patterns designed for an integrated circuit product (IC product) according to specifications of the integrated circuit product being manufactured. The circuit patterns correspond to geometric patterns formed in various material layers (e.g., conductive, insulating, or semiconductor layers) that, in combination, form integrated circuit elements of an integrated circuit product (e.g., integrated circuit device 140). For example, portions of the integrated circuit design layout 112 may include various integrated circuit elements formed on a substrate (e.g., a silicon wafer) and/or disposed on various material layers of the substrate. These various components may include active regions, gate components (e.g., gate dielectric layers and/or gate electrodes), source/drain components, interconnect components, bonding pad components, other integrated circuit components, combinations thereof, and the like.
The mask chamber 120 manufactures one or more masks (photomasks) used to fabricate the various layers of the integrated circuit device 140 according to the integrated circuit design layout 112 using the integrated circuit design layout 112. A mask refers to a patterned substrate used in a photolithographic process to pattern a wafer, such as a semiconductor wafer. The mask chamber 120 may have a data preparation (data preparation) module 122 and a mask machining (mask firing) module 124. The data preparation module 122 and the mask processing module 124 may perform Logic Operations (LOP) 126-1 and OPC 126-2 to compile the integrated circuit design layout 112 into a form that can be written to by the mask writer 126-3 to generate a mask. For example, the integrated circuit design layout 122 is compiled into machine readable instructions for a mask writer 126-3, such as an electron-beam (E-beam) writer, and the writer 126-3 is utilized to generate a mask pattern.
The integrated circuit fab 130 uses the mask (or masks) produced by the mask chamber 120 to fabricate integrated circuit devices 140 on the wafer 132. For example, the integrated circuit fab 130 may perform a photolithography process to transfer a pattern on a mask (e.g., the mask manufactured by the mask chamber 120) onto a wafer material layer to form a patterned photoresist layer, and to transfer a pattern defined in the patterned photoresist layer to the wafer material layer. The wafer material layer may be a dielectric layer, a semiconductor layer, a conductive layer, a portion of a substrate, and/or other suitable wafer material layer.
Referring to FIG. 2, FIG. 2 is a diagram of an initial IC design layout 20. In the initial integrated circuit design layout 20, a plurality of integrated circuit regions 210, labeled 1, 2, 3 … … through n, respectively, may be included. The initial integrated circuit pattern 220 is included in each integrated circuit region 210, and the initial integrated circuit patterns 220 in the integrated circuit regions 210 are identical. The initial integrated circuit pattern 220 includes one or more features corresponding to dielectric, semiconductor, conductive, or other suitable wafer material layers that will form the various components of the integrated circuit device, such as active regions, gates, source/drains, contact plugs, lines or vias for inter-level metal interconnects, etc. In some embodiments, each integrated circuit region 210 defines an integrated circuit die that includes the integrated circuit pattern 220 described above.
In addition, in semiconductor processing, the exposure wavelength of the optical lithography radiation source can be reduced to achieve the goals of improving image resolution and reducing the minimum feature size. Therefore, EUV lithography with exposure wavelength between 10nm and 130nm is a lithography solution that is an emerging technology node (e.g. 22nm, 14nm, 10nm, etc.). However, the EUV lithography process is not only a high energy consuming and difficult to control process by itself, but in the EUV lithography process, deformation due to various optical effects or material influences, such as a shadow effect (shadow slit effect), a slit effect (slit effect), a flare effect (flare effect), an edge effect (border effect), an etch heating effect (resist heating effect), a baking effect, a development loading effect (developing loading effect), an etch loading effect (etching loading effect), or a combination thereof, may be found.
For example, when the lithographic process uses an EUV beam, the EUV beam is tilted towards the optical axis of the lithographic system, for example at a tilt angle of about 6 degrees. Oblique illumination causes shadowing effects (shadow effect) and results in image distortions that depend on the position of the pattern feature to be imaged. In addition to the shadowing effect, the slit effect (slit effect) also causes the original identical initial integrated circuit pattern 220 to encounter different imaging effects due to differences in position on the initial integrated circuit design layout 20. Referring to fig. 3, since the EUV illumination slit is an arc-shaped slit, when light passes through the arc-shaped slit, azimuthally angles (azimuthally angles) are generated due to the relative positions of the light and the transmitted light at different positions has different intensities (intensity) and phases (phase). So that the initial integrated circuit pattern 220 corresponding to the position is deformed to different degrees when the exposure process is performed. Generally, the deformation caused by the slit effect will be exhibited in the X-direction (as shown in fig. 2). That is, the initial integrated circuit patterns 220 in the same column of integrated circuit regions 210 in the initial integrated circuit design layout 20 are distorted to the same degree, while the integrated circuit patterns 220 in different columns of integrated circuit regions 210 are distorted to different degrees.
To avoid these pattern distortions, the mask chamber 120 may be configured to perform the OPC 126-2, and use the OPC 126-2 to correct distortions and deformations (e.g., line end shortening, line end connection, line width variation, line corner rounding, line density and line depth focalization) that may occur in each of the initial integrated circuit patterns 220. When the exposure process is performed using EUV, it is more necessary to treat the distortion due to EUV using OPC 126-2. Therefore, the OPC 126-2 performs a plurality of iterations (iterations) on the initial integrated circuit pattern 220 in each integrated circuit region 210 to correct the image distortion problem. For example, for the initial ic design layout 20 shown in fig. 2, 30 initial ic patterns 220 in 6 rows and 5 columns must be repeatedly processed by one iteration, i.e., 6 × 5 × l — 30l iterations. Since the OPC 126-2 must be operated for all possible variations of the initial integrated circuit pattern 220 in each integrated circuit region 210, the number of repetitive operations is too large, the execution time of the repetitive operations is too long, and the Turn Around Time (TAT) cannot meet the target of the ic foundry 130 on the cycle of the production cycle.
Accordingly, the present disclosure provides a method for fabricating an integrated circuit, which uses grouping and level (hierarchy) operations to reduce the number of times of OPC iterations and the execution time while ensuring the mask pattern is authentic, so as to achieve the TAT goal.
Referring to fig. 4, fig. 4 is a flow chart illustrating a method 30a of manufacturing an integrated circuit according to some embodiments of the present disclosure. As shown in fig. 4, the integrated circuit fabrication method 30a includes operations 301 through 305. In operation 301, an initial integrated circuit design layout is received. In some embodiments, the initial integrated design layout includes m x n integrated circuit regions, the integrated circuit regions are arranged in an array of m columns and n rows, and the same initial integrated circuit pattern is included in each of the integrated circuit regions. In operation 302, a first OPC is performed on the initial integrated circuit patterns within each of the integrated circuit regions, respectively. In some embodiments, the first OPC comprises a total of m × n × l-1 iterations. In operation 303, a plurality of the integrated circuit regions arranged in a same column in the array are defined as a same group. In some embodiments, a total of m groups of integrated circuit regions are obtained. In operation 304, a second OPC is performed in groups to obtain a corrected integrated circuit design layout. In operation 305, the corrected integrated circuit design layout is output to a mask. The method 30a for fabricating an integrated circuit may include the following embodiments, but is not limited thereto. It is noted that the method 30a of fabricating an integrated circuit provided by the present disclosure may rearrange or otherwise modify its operation or perform operations within the scope of the various aspects. For example, the execution order of operations 302 and 303 may be operation 302 before operation 303 and after operation 303 in some embodiments, and may be operation 303 before operation 302 and after operation 303 in some embodiments. In addition, the method 30a of fabricating an integrated circuit provided by the present disclosure may include other operations before, during, and after, and only some of the other operations are briefly described herein, but are not limited thereto.
Referring to fig. 5, fig. 5 is a flow chart illustrating a method 30b of fabricating an integrated circuit according to some embodiments of the present disclosure. As shown in fig. 5, the method 30b for manufacturing an integrated circuit includes operations 311 through 315. In operation 311, an initial integrated circuit design layout is received. In some embodiments, the initial integrated design layout includes m x n integrated circuit regions arranged in an array of m columns and n rows, and each of the integrated circuit regions includes the same initial integrated circuit pattern therein. In operation 312, a plurality of the integrated circuit regions disposed in a same column in the array are defined as a same group. In some embodiments, a total of m groups of integrated circuit regions are obtained. In operation 313, the grouping performs the second OPC. In operation 314, a second OPC is performed on each of the integrated circuit regions to obtain a corrected integrated circuit design layout. In some embodiments, the second OPC comprises a total of m × n × l-1 iterations. In operation 315, the corrected integrated circuit design layout is output to a mask. The method 30b for manufacturing an integrated circuit may include the following embodiments, but is not limited thereto. It is noted that the method 30b of fabricating an integrated circuit provided by the present disclosure may rearrange or otherwise modify its operation or perform operations within the scope of the various aspects. In addition, the method 30b of fabricating an integrated circuit provided by the present disclosure may include other operations before, during, and after, and only some of the other operations are briefly described herein, but is not limited thereto.
Referring to fig. 6, fig. 6 is a schematic diagram of an initial integrated circuit design layout 40 provided by the present disclosure. Pursuant to operation 301, an initial integrated circuit design layout 40 is accepted. In the initial ic design layout 40, a plurality of ic regions 410, such as m × n ic regions 410, may be included, which may be respectively labeled as 1, 2, 3 … … through n, but the labeling is not limited thereto. These integrated circuit regions 410 are arranged in an array of m columns and n rows. For example, in the present embodiment, the initial design layout 40 of the integrated circuit includes 30 integrated circuit regions 410 arranged in an array of 5 columns and 6 rows, but the disclosure is not limited thereto. An initial integrated circuit pattern 420 is included in each integrated circuit region 410, and the initial integrated circuit patterns 420 in the integrated circuit regions 410 are identical. The initial integrated circuit pattern 420 includes one or more features corresponding to dielectric, semiconductor, conductive, or other suitable wafer material layers that will form the various components of the integrated circuit device, such as active regions, gates, source/drains, contact plugs, lines or vias for inter-level metal interconnects, etc. In some embodiments, each integrated circuit region 410 defines an integrated circuit die that includes the integrated circuit pattern 420 described above.
In operation 302, a first OPC 430 is performed on each initial integrated circuit pattern 420 within each integrated circuit region 410, respectively. It is noted that the first OPC 430 is performed for each integrated circuit region 410 for a plurality of iterations. Various imaging effects may occur as a result of transferring the initial integrated circuit design layout 420 to a mask or wafer used to fabricate the final integrated circuit elements. These imaging effects may cause the integrated circuit patterns fabricated in the various integrated circuit regions 410 to differ in the final integrated circuit elements even though the initial integrated circuit patterns 420 are the same. These effects include proximity effect (proximity effect) and location effect (location effect). Proximity effects are changes in the image due to close features caused by diffraction (diffraction) or interference (interference). For example, pattern features in a dense pattern environment and identical features in an isolated environment may produce images with different critical dimensions. In the present embodiment, the first OPC 430 performs a plurality of repeated operations on the initial integrated circuit patterns 410 in the integrated circuit regions 410, and adjusts the initial integrated circuit patterns 420 in the integrated circuit regions 410 by resizing, reshaping, adding assist features (assist features), adding scattering bars (scattering bars), or a combination thereof, so as to improve the image of the photolithography process.
The position effect is an imaging variation due to or related to the position of the corresponding pattern feature in the initial integrated circuit design layout 40. As previously mentioned, when the lithography process uses an extreme ultraviolet light (EUV) beam, positional effects that may occur include in the EUV lithography process, deformations due to various optical effects or material influences may be found, such as shadow effects, slit effects, flare effects, edge effects, or combinations thereof. The first OPC also performs a plurality of iterations of resizing, reshaping, adding assist features, adding scattering bars, or a combination thereof, on the initial integrated circuit patterns 410 in each integrated circuit region 410 to adjust the initial integrated circuit patterns 420 in each integrated circuit region 410 to improve the image of the photolithography process.
It is noted that in the comparative embodiment (comparative embodiment), the initial integrated circuit pattern 410 of the OPC in each integrated circuit region 410 is corrected for all the imaging variations described above, that is, the initial integrated circuit pattern 420 in each integrated circuit region 410 may undergo l iterations to improve the image of the photolithography process. An initial ic layout pattern having m x n ic regions undergoes m x n x l iterations, where l is the total number of predetermined operations in any ic region 410. For example, for the initial integrated circuit design layout 40 shown in FIG. 6, the comparative example must perform 30 × l iterations to obtain a layout pattern that improves the lithographic process.
Please refer to fig. 7. In some embodiments of the present disclosure, the first OPC 430 performed in operation 302 is performed on the initial integrated circuit pattern 420 within each integrated circuit region 410 for imaging variations as described above, except for imaging variations that are slit effect inverted, although the present disclosure is not limited thereto. The initial ic pattern 420 in each ic area 410 may undergo l-1 iterations to improve the image of the photolithography process, where l is the total number of predetermined operations in any ic area 410. In other words, in some embodiments of the present disclosure, the first OPC 430 includes m × n (l-1) iterations. For example, for the initial IC design layout 40 shown in FIG. 6, the first OPC 430 comprises 30 (l-1) iterations.
Referring to fig. 8, in operation 303, the integrated circuit regions 410 disposed in the same vertical row in the array of the initial integrated circuit design layout 40 are defined as a same group. Thus, m groups of integrated circuit regions 440-1, 440-2 … … 440-m are obtained. For example, the initial integrated circuit design layout 40 has a total of 5 vertical rows, so 5 groups of integrated circuit regions 440-1, 440-2, 440-3, 440-4, and 440-5 are available, as shown in FIG. 8.
It is noted that in some embodiments, operation 303 may proceed after operation 302. However, in other embodiments, operation 303 may be performed before operation 302, as desired by the process or software operation.
Please refer to fig. 9. In operation 304, a second OPC 450 is performed in a packet. In some embodiments, the second OPC 450 is used to correct image distortion due to slit effect. As mentioned above, the slit effect may cause different degrees of deformation of the feature patterns in the integrated circuit region 210 at different positions during the exposure process. Generally, the deformation caused by the slit effect is exhibited in the X direction. That is, the original integrated circuit patterns 420 within integrated circuit regions 410 of the same integrated circuit region group (i.e., the same column) exhibit the same degree of distortion, while the original integrated circuit patterns 420 within integrated circuit regions 410 of different integrated circuit region groups (i.e., different columns) exhibit different degrees of distortion. Therefore, the second OPC 450 performs the same iterative operations on the respective integrated circuit regions 410 within the same group. Thus, the second OPC 450 comprises m iterations. For example, the initial IC design layout 40 has 5 IC circuit area groups 440-1, 440-2, 440-3, 440-4 and 440-5, so the second OPC 450 comprises 5 iterations as shown in FIG. 9.
Please refer to fig. 10. After the second OPC 450 is performed, corrected integrated circuit patterns 422 are included in each integrated circuit region 410, and these corrected integrated circuit patterns 422 are used to form the corrected integrated circuit design layout 42. In other words, in operation 304, the second OPC 450 that corrects for the slit effect is performed in groups to obtain the corrected integrated circuit design layout 42.
In operation 305, the corrected integrated circuit design layout 42 may be output to a mask that may be used in the integrated circuit fab 130 to pattern features on the wafer 132 corresponding to dielectric, semiconductor, conductive, or other suitable wafer material layers.
Accordingly, the integrated circuit manufacturing method 30a according to the present disclosure performs image correction, for example, other than the slit effect, on the initial integrated circuit pattern 420 in each integrated circuit region 410 by using the first OPC 430, so that the first OPC 430 includes m × n (l-1) iterations, for example, 30 × 1 iterations, as described above. After the integrated circuit regions 410 disposed in the same vertical row are defined as the same integrated circuit region group, the respective integrated circuit region groups 440-1 to 440-m are grouped by the second OPC 450 to correct image deformation caused by the slit effect. The second OPC 450 comprises m iterations, such as 5 iterations, as described above. That is, the first OPC 430 and the second OPC 450 collectively include m × n (l-1) + m iterations. In some embodiments of the present disclosure, the first OPC 430 and the second OPC 450 comprise 5 × 6 × 1) +5 iterations, i.e., 30l-25 iterations. In comparison with the comparative example, the comparative example described above requires 30l times of repetition. Therefore, the integrated circuit manufacturing method provided by the present disclosure can definitely reduce the total operation times of OPC. In some embodiments, the OPC overall operation time of the integrated circuit manufacturing method provided by the present disclosure can be reduced by more than about 40%. Briefly, the present disclosure provides an OPC performing method and a mask fabricating method, which utilize grouping and level operations to reduce the number of OPC operations and the performing time while ensuring the mask pattern to be real, so as to achieve the TAT goal.
Referring to fig. 11, fig. 11 is a schematic diagram of an initial integrated circuit design layout 50 provided by the present disclosure. An initial integrated circuit design layout 50 is accepted, per operation 311. In the initial ic design layout 50, a plurality of ic circuits 510, such as m × n ic circuits 510, may be included, which are respectively labeled as 1, 2, 3 … … through n, but the labeling is not limited thereto. These integrated circuit regions 510 are arranged in an array of m columns and n rows. For example, in the present embodiment, the initial design layout 50 of the integrated circuit includes 30 integrated circuit regions 510 arranged in an array of 5 columns and 6 rows, but the disclosure is not limited thereto. The initial integrated circuit patterns 520 are included in each integrated circuit region 510, and the initial integrated circuit patterns 520 in the integrated circuit regions 510 are identical. The initial integrated circuit design layout 50 may be the same as the initial integrated circuit design layout 40, and therefore, the details thereof are not described herein.
With continued reference to fig. 11, at operation 312, the integrated circuit regions 510 disposed in the same column in the array of the integrated circuit design layout 50 are defined as a same group. Thus, m integrated circuit region groups 540-1, 540-2 … … 540-m can be obtained. For example, the initial integrated circuit design layout 50 has a total of 5 columns, so 5 groups of integrated circuit regions 540-1, 540-2, 540-3, 540-4 and 540-5 are available, as shown in FIG. 11.
Please refer to fig. 12. In operation 313, the first OPC 530 correcting the slit effect is grouped. The reason for the formation of the slit effect is as described above, and therefore, the detailed description thereof is omitted here. Since the initial integrated circuit patterns 520 in the same group (i.e., the same vertical row) of integrated circuit regions 510 exhibit the same degree of deformation, while the initial integrated circuit patterns 520 in different groups (i.e., different columns) of integrated circuit regions 510 exhibit different degrees of deformation, the first OPC 530 performs the same repetitive operations on the respective integrated circuit regions 510 in the same group. Thus, the first OPC 530 comprises m iterations. For example, the initial IC design layout 50 has 5 IC circuit area groups 540-1, 540-2, 540-3, 540-4 and 540-5, so the first OPC 530 comprises 5 iterations as shown in FIG. 12.
Please refer to fig. 13. In operation 314, a second OPC 530 is performed on each of the integrated circuit regions 510, respectively. It should be noted that the second OPC 530 is an iterative process performed on the image deformation, except for the slit effect, which may occur in each integrated circuit region 510 due to the proximity effect and the position effect. It may go through l-1 iterations in each integrated circuit region 510. In other words, in some embodiments of the present disclosure, the second OPC 530 comprises m × n (l-1) iterations, where l is the total number of predetermined operations in any one of the integrated circuit regions 510. For example, for the initial IC design layout 50 shown in FIG. 11, the second OPC 550 comprises 30 (l-1) iterations.
Please refer to fig. 14. After the second OPC 550 is performed, corrected integrated circuit patterns 522 are included in each integrated circuit region 510, and the corrected integrated circuit patterns 522 form the corrected integrated circuit design layout 52. In other words, in operation 314, the second OPC 450 is performed on each integrated circuit region 510 to obtain the corrected integrated circuit design layout 52.
In operation 315, the corrected integrated circuit design layout 52 may be output to a mask that may be used in the integrated circuit fab 130 to pattern features on the wafer 132 corresponding to dielectric, semiconductor, conductive, or other suitable wafer material layers.
Accordingly, in the integrated circuit manufacturing method 30b provided by the present disclosure, after the integrated circuit regions 510 disposed in the same vertical row are defined as the same group, the first OPC 530 is performed on each of the integrated circuit region groups 540-1 to 540-m in groups to correct the image distortion caused by the slit effect. The first OPC 530 comprises m iterations, such as 5 iterations, as described above. Next, since image correction other than the slit effect is performed on each integrated circuit region 510 by using the second OPC 550, the second OPC 550 includes m × n × l-1 iterations, such as 30 × l-1 iterations, as described above. That is, the first OPC 530 and the second OPC 550 collectively include m × n (l-1) + m iterations. In some embodiments of the present disclosure, the first OPC 530 and the second OPC 550 include 5 × 6 × 1) +5 iterations, i.e., 30l-25 iterations. The comparative example described above requires 30l times of repetition as compared with the comparative example described above. Therefore, the integrated circuit manufacturing method provided by the present disclosure can definitely reduce the total operation times of OPC. In some embodiments, the OPC overall operation time of the integrated circuit manufacturing method provided by the present disclosure can be reduced by more than about 40%. Briefly, the present disclosure provides an OPC performing method and a mask fabricating method, which utilize grouping and level operations to reduce the number of OPC operations and the performing time while ensuring the mask pattern to be real, so as to achieve the TAT goal.
Briefly, the present disclosure provides a method for separating the repetition of the slit effect, grouping the integrated circuit regions before or after performing OPC (repetition of other images), and performing the repetition of the slit effect and OPC for each group. It should be further noted that the independent repetitive operation is not limited to the repetitive operation of the slit effect, and the integrated circuit manufacturing method provided by the present disclosure can be adopted to reduce the number of OPC operations and the execution time to achieve the TAT target on the premise of ensuring the mask pattern to be true even if there are group differences in the image deformation.
In some embodiments, a method of manufacturing an integrated circuit is provided. The method comprises the following steps: receiving an initial integrated circuit design layout, wherein the initial integrated circuit design layout comprises m x n integrated circuit regions which are arranged into an array of m columns and n rows, and the same initial integrated circuit pattern is contained in each integrated circuit region; respectively carrying out first OPC on the initial integrated circuit patterns in each integrated circuit region, wherein the first OPC comprises m × n × l-1 repeated operations in total; defining a plurality of integrated circuit regions arranged in the same column in the array as a same group; and performing a second OPC in groups to obtain a corrected integrated circuit design layout.
In some embodiments, a method of manufacturing an integrated circuit is provided. The method comprises the following steps: receiving an initial integrated circuit design layout, wherein the initial integrated circuit design layout comprises m x n integrated circuit regions which are arranged into an array of m columns and n rows, and the same initial integrated circuit pattern is contained in each integrated circuit region; defining a plurality of integrated circuit regions arranged in the same column in the array as a same group; grouping and carrying out first OPC; and respectively carrying out second OPC on each integrated circuit region to obtain a corrected integrated circuit design layout, wherein the second OPC comprises m × n (l-1) repeated operations.
In some embodiments, a method of manufacturing an integrated circuit is provided. The method comprises the following steps: receiving an initial integrated circuit design layout, wherein the initial integrated circuit design layout comprises m x n integrated circuit regions which are arranged into an array of m columns and n rows, and the same initial integrated circuit pattern is contained in each integrated circuit region; performing first OPC on the initial integrated circuit patterns in each integrated circuit region respectively, wherein the first OPC comprises m × n × l-1 repeated operations in total; defining a plurality of integrated circuit regions arranged in the same column in the array as a same group to obtain m integrated circuit region groups; grouping a second OPC that corrects for a slit effect to obtain a plurality of corrected integrated circuit patterns, the corrected integrated circuit patterns forming a corrected integrated circuit design layout, wherein the second OPC comprises m iterations in total; and outputting the corrected integrated circuit design layout to a mask.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein.
Description of the symbols
10 Integrated Circuit fabrication System
110 design company
112 integrated circuit design layout
120 mask chamber
122 data preparation module
124 mask processing module
126-1 logical operation
126-2 Optical Proximity Correction (OPC)
126-3 direct writer
130 integrated circuit fabrication plant
140 integrated circuit device
20 initial integrated circuit design layout
210-1 ~ 210-n integrated circuit region
220 initial integrated circuit pattern
30a, 30b method
301 to 305 operations
311 to 315 operations
40 initial integrated circuit design layout
42 corrected integrated circuit design layout
410-1 to 410-m integrated circuit region
420 initial integrated circuit pattern
422 corrected integrated circuit pattern
430 first Optical Proximity Correction (OPC)
440-1 to 440-m IC circuit region group
450 second Optical Proximity Correction (OPC)
50 initial integrated circuit design layout
52 corrected integrated circuit design layout
510-1 ~ 510-m integrated circuit region
520 initial integrated circuit pattern
522 corrected integrated circuit pattern
530 first Optical Proximity Correction (OPC)
540-1 ~ 540-m integrated circuit region group
550 second Optical Proximity Correction (OPC)
Claims (10)
1. A method of manufacturing an integrated circuit, comprising:
receiving an original integrated circuit design layout, wherein the original integrated circuit design layout comprises m × n integrated circuit regions which are arranged into an array of m columns and n rows, and the same original integrated circuit pattern is contained in each integrated circuit region;
respectively carrying out first Optical Proximity Correction (OPC) on the original integrated circuit patterns in each integrated circuit region;
defining a plurality of integrated circuit regions arranged in the same column in the array as a same group; and
a second OPC is performed in groups to obtain a corrected integrated circuit design layout.
2. The method of claim 1 wherein the operation of defining a plurality of the integrated circuit regions in the array disposed in a same column as a same set is performed before or after the first OPC.
3. The method of claim 1, wherein the grouping for the second OPC further comprises: the same repeated operation is carried out on each integrated circuit region of the same group to obtain a plurality of corrected integrated circuit patterns, and the corrected integrated circuit patterns form the corrected integrated circuit design layout.
4. The method of claim 1, further comprising outputting the corrected integrated circuit design layout to a mask.
5. A method of manufacturing an integrated circuit, comprising:
receiving an original integrated circuit design layout, wherein the original integrated circuit design layout comprises m × n integrated circuit regions which are arranged into an array of m columns and n rows, and the same original integrated circuit pattern is contained in each integrated circuit region;
defining a plurality of integrated circuit regions arranged in the same column in the array as a same group;
grouping and carrying out first OPC; and
and respectively carrying out second OPC on each integrated circuit region to obtain a corrected integrated circuit design layout, wherein the second OPC comprises m × n (l-1) operations in total.
6. The method of claim 5, wherein the grouping corrects the first OPC further comprises: the same iteration is performed on the original integrated circuit patterns within each of the integrated circuit regions in the same group.
7. The method of claim 5, wherein after performing the second OPC, a plurality of corrected integrated circuit patterns are obtained and the corrected integrated circuit patterns form the corrected integrated circuit design layout.
8. The method of claim 5, further comprising outputting the corrected integrated circuit design layout to a mask.
9. A method of manufacturing an integrated circuit, comprising:
receiving an original integrated circuit design layout, wherein the original integrated circuit design layout comprises m × n integrated circuit regions which are arranged into an array of m columns and n rows, and the same original integrated circuit pattern is contained in each integrated circuit region;
respectively carrying out first OPC on the original integrated circuit patterns in each integrated circuit region;
defining a plurality of integrated circuit regions arranged in the same column in the array as a same group;
grouping and performing second OPC for correcting the slit effect to obtain a corrected integrated circuit design layout; and
outputting the corrected integrated circuit design layout to a mask.
10. The method of claim 9, wherein the first OPC is performed before the second OPC.
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| CN201911182217.8A CN112859508A (en) | 2019-11-27 | 2019-11-27 | Method for manufacturing integrated circuit |
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| CN201911182217.8A CN112859508A (en) | 2019-11-27 | 2019-11-27 | Method for manufacturing integrated circuit |
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Cited By (1)
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| WO2022266850A1 (en) * | 2021-06-22 | 2022-12-29 | 华为技术有限公司 | Integrated circuit placement method and apparatus |
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