JP4115615B2 - Mask pattern design method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a design of a photomask used in a photolithography process which is one of manufacturing processes of a semiconductor integrated circuit, and more particularly to a method of designing a mask pattern used for forming a gate electrode of a logic device.
[0002]
[Prior art]
In recent years, in the manufacture of semiconductor devices, higher integration and miniaturization of elements and wirings constituting a circuit have been promoted. For example, in the manufacture of RISC processors used as CPUs for EWS (Engineering Work Station) and PC (Personal Computer), the size of the gate electrode of a transistor is required to be 110 nm in 2002.
[0003]
FIG. 19 shows a pattern example of the gate and element region of the RISC processor. Here, the gate length of the gate wiring 11 is given to the fine gate portion 16 mounted on the element region 12. The connecting wiring part 17 connects the gate part 16 and the contact pad part 18. The gate wiring 11 is terminated by an end cap portion 19.
[0004]
By the way, with the recent miniaturization of circuit patterns, there has been a serious decrease in pattern transfer accuracy in a photolithography process in which a pattern on a photomask is transferred onto a semiconductor wafer.
[0005]
One of the techniques for improving the transfer accuracy is a phase shift mask exposure method for improving the contrast of an image projected on a semiconductor wafer by changing the phase of light passing through a photomask.
[0006]
Among the phase shift masks, the Levenson phase shift mask is provided with a phase shifter at one opening so as to give a phase difference of 180 degrees to the exposure light passing through the adjacent opening region with the light shielding region interposed therebetween.
[0007]
This Levenson phase shift mask is indispensable in order to achieve the above-described gate portion 16 having a line width of 110 nm by photolithography.
[0008]
Consider a case where a Levenson phase shift mask is used to form a gate pattern as shown in FIG. As a method for forming such a gate pattern, for example, as disclosed in Japanese Patent Laid-Open No. 7-106227, there is a method of performing multiple exposure of a Levenson phase shift mask and a normal photomask.
[0009]
As the first photomask, a Levenson phase shift mask in which an opening 14 is provided to sandwich the gate portion 16 as shown in FIG. 20A and phase shifter portions 15 are alternately provided to sandwich the gate portion 16 is used.
[0010]
As the second photomask, as shown in FIG. 20B, a normal photomask provided with a light shielding pattern 13 including a light shielding pattern portion 20 covering the connection wiring portion 17 and the contact pad portion and the gate portion 16 is used. These first and second photomasks are subjected to multiple exposure.
[0011]
As shown in FIG. 20 (c), a dark part where the exposure light is not irradiated is formed in a region where the light shielding part overlaps. Therefore, when a positive resist is used, the resist 21 is placed in the dark part as shown in FIG. 20 (d). The remaining pattern is formed. Here, the mask used for the second exposure is called a trim mask.
[0012]
As a method for designing the pattern data of the Levenson mask and trim mask, for example, there are the following steps. This will be described with reference to FIGS. FIG. 21 is a flowchart showing the steps of a conventional design method, and FIG. 22 is a top view of relevant parts for explaining the design of a photomask corresponding to the steps. However, the gate portion 16 is formed by a Levenson mask, and the connecting wiring portion 17, the contact pad portion 18, and the end cap portion 19 are formed by a trim mask.
[0013]
In step 211 shown in FIG. 21, first, the original design pattern of the gate wiring 31 and the element region 32 is input as shown in FIG. Next, in step 212, as shown in FIG. 22B, the element region 12 is expanded to become the zeroth region 33. Here, the element region 32 is expanded in order to design the fine gate portion slightly overhanging the element region 32. This is because the performance of the transistor is deteriorated when a connecting wiring portion wider than the fine gate portion is placed in the element region 32, so that the transistor region slightly protrudes.
[0014]
Next, in step 213, a region where the gate wiring 31 and the zeroth region 33 overlap is calculated as the first region 34. Here, a region where the width of the first region 34 is finally reduced becomes a fine gate portion. In step 214, as shown in FIG. 22C, the first region 34 is extended by a preset value P in the direction orthogonal to the gate portion 31 to form the second region 35.
[0015]
Thereafter, in step 215, as shown in FIG. 22D, the second region 35 overlaps with the adjacent second region 35, and in step 216, the second region 35 is combined with the second region 35. A region excluding the first region 34 is obtained by calculation, and is defined as a third region 36 as shown in FIG.
[0016]
Next, in step 217, the position of the side of the third region 36 is moved by the distance Q so as to narrow the width of the third region 36 in the short side direction as shown in FIG. Thereby, a fine gate portion having a desired size is designed.
[0017]
Next, in step 218, OPC (Optical Proximity Correction) processing is performed on the third region 36. If the OPC process is not performed, a phenomenon occurs in which the width of the gate portion is not uniformly finished when patterns exist at various intervals as in the gate wiring 16 of FIG.
[0018]
That is, when transferring the pattern of size A on the photomask, if the exposure amount at the time of exposure is set so that the resist on the substrate to be processed is finished to a desired size (A / exposure magnification), the pattern of size B is It is formed deviating from a desired value (B / exposure magnification). Accordingly, it is necessary to correct the design pattern size of the photomask according to the opening width so that the width of the gate portion is formed to a desired value.
[0019]
For example, there is a method of measuring the finished dimensions of the resist with respect to the width (opening width) of the third region 36 on the photomask in advance from an experiment, preparing a correction table, and correcting according to this. Alternatively, there is a method for predicting the finished size of the resist according to the width of the third region 36 by simulation.
[0020]
However, if the correction is made experimentally, correction including the dimensional conversion difference in the RIE (Reactive Ion Etching) process of the gate electrode after forming the resist pattern can be performed, and correction with higher accuracy is possible. . After that, in step 219 through step 218, the third region 36 is set as a design pattern for the opening 14 of the Levenson mask.
[0021]
Next, the design of the shifter pattern in the Levenson mask fabrication is performed in steps 220 to 224 as shown in FIG. First, steps 220 to 223 are performed in order to alternately arrange the shifter patterns in the openings 14. Here, the distance between the adjacent third regions 36 is evaluated, and a group of the third regions 36 that is equal to or less than the distance R is obtained.
[0022]
Further, in steps 221 to 223, shifter arrangements are determined alternately for each group, for example, 0 ° from the side closer to the design origin and then 180 °, 0 °, and 180 °. The 180 ° region is defined as a fourth region 37. Thereafter, as shown in step 224, the entire dimension S is thickened in order to design drawing data of the shifter pattern at the time of producing the Levenson mask.
[0023]
Next, in steps 225 and 226, as shown in FIG. 22 (h), as a trim mask design, the third region 36 is slightly reduced by the distance T and includes both the pattern of the gate wiring 31 and the pattern. Data is created and used as a design pattern for the light shielding part of the trim mask. The reduction of the third area 36 is a result of considering misalignment (alignment error) during exposure of the Levenson mask and the trim mask.
[0024]
[Problems to be solved by the invention]
However, the above-described conventional mask pattern design method has the following problems. As shown in FIGS. 23A to 23C, when the distance between the opening and the connecting wire is narrow, the width of the connecting wire may be narrowed or thickened due to an alignment error during multiple exposure. FIG. 23A shows a Levenson mask design pattern, and FIG. 23B shows a trim mask design pattern. When there is no alignment error, an image of multiple exposure as shown in FIG. 23C is obtained, and a desired pattern is formed as shown in FIG.
[0025]
However, as shown in FIG. 23 (e), when exposure is performed with the position of the trim mask shifted downward with respect to the Levenson mask, as shown in FIG. There is a problem that the dimension of () part is thin. In general, considering the influence on device performance, the dimensional design value ± 10% is required as the controllability of the dimension. On the other hand, the alignment error is much larger. Therefore, in the case shown in FIG. 23, a dimensional error corresponding to the alignment error occurs, but this is not an acceptable value for the controllability of the dimensionality.
[0026]
In addition, as shown in FIGS. 24A to 24E, there may be a case where the interval between the opening 14 and the connection wiring is narrow in the direction orthogonal to the gate portion. FIG. 24A shows a design pattern for a Levenson mask, and FIG. 24B shows a design pattern for a trim mask. In this case, as shown in a circle in FIG. 24B, a light shielding pattern close to the trim mask is generated. FIG. 24C shows a desired pattern.
[0027]
However, when the proximity part in the circle in FIG. 24B is a distance equal to or less than the resolution limit, the light shielding part is connected to the proximity part. Therefore, after multiple exposure, as shown in FIG. 6D, the size of the contact pad portion is determined at the boundary of the opening portion of the Levenson mask.
[0028]
For this reason, it is conceivable that the contact pad portion is formed larger than the intended dimension, and the dimension varies due to an alignment error between the exposures of both masks.
[0029]
As an OPC method, the opening width is corrected, and the dimensions of the gate portion are made uniform. However, when the large-area light-shielding region 13 exists adjacent to the opening 14 as in the gate portions A and E shown in FIG. 25, the correction of the opening width is not sufficient.
[0030]
FIG. 26 shows a projected image when the design pattern of the Levenson mask of FIG. 25 is transferred onto the substrate to be processed. The gate portions B, C, and D have almost the same profile of the projected image, and the resolution line widths 44 are almost equal. However, it can be seen that the outer gate portions A and E are different (narrower) from the inner gate portions B, C, and D.
[0031]
Thus, even after the opening width is exactly the same, the dimensions after transfer vary depending on the surrounding environment. However, in the conventional method, the opening width is not corrected in consideration of the outer environment. In addition, there is a method of performing correction in consideration of the surrounding environment by simulation, but there is a problem that accuracy is poor and calculation time is enormous as described above.
[0032]
The present invention has been made in order to solve the above-described conventional problems. The object of the present invention is to easily eliminate the dimensional variation of the connection wiring portion due to the alignment error, and to easily control the gate portion. And a semiconductor device manufactured using a mask pattern designed by this design method.
[0033]
[Means for Solving the Problems]
In order to achieve the above object, a feature of the present invention is a mask pattern design method for designing a mask pattern by generating a plurality of pattern data by performing a logical operation using pattern data of an element region and a wiring. The original design pattern of the wiring and the element region is input, the element region is expanded to be a 0th region, a region where the wiring and the 0th region are overlapped is calculated, and the first region is set as a gate portion. The second region is expanded by a predetermined value in a direction orthogonal to the second region, and the second region adjacent to and overlapped with the second region is combined, and the wiring adjacent to the second region within a predetermined distance or less is synthesized. Including a process of moving a part or all of the wiring so as to be equal to or greater than the set distance, and a component of the device that is close to the set distance or less to a part or all of the wiring subjected to the distance process A device that performs the process of moving away the constituent elements of the corresponding device from a part or all of the wiring subjected to the process of moving away from the set distance or more, and then performing the process of moving away. It is detected whether or not there are other components of the device that are close to the set distance or less, and if detected, the component of the corresponding device is first moved away from the component of the device that is more than the set distance. The process of moving away is repeated until no other device component is detected below the set distance. The wiring overlapping the 0th region is a wiring formed by a Levenson mask, and the other wiring is a wiring formed by a trim mask. That is.
[0042]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a mask pattern design method according to the present invention will be described below with reference to the drawings. However, the dimension values of the patterns and the like described below indicate the dimension values on the substrate to be processed, and are four times the values on the photomask.
[0043]
Example 1
FIG. 1 is a flowchart for explaining the steps of the mask pattern design method according to the first embodiment of the present invention. This flowchart describes a design method for the Levenson mask and trim mask. FIG. 2 is a top view of an essential part of a photomask for explaining the design method.
[0044]
In step 101 of FIG. 1, first, the original design pattern of the gate wiring and the element region is input. Here, the original design dimension of the gate wiring is 240 nm, and the photomask was designed so as to obtain a gate part dimension of a desired value of 110 nm on the substrate to be processed in the following steps.
[0045]
In step 102, the element region is expanded to be the 0th region, and then in step 103, a region where the gate wiring and the 0th region overlap is calculated and set as the first region. Here, the region where the width of the first region is finally reduced becomes the fine gate portion.
[0046]
In step 104, the first area is extended by a preset value P in the direction orthogonal to the gate portion to form the second area. Here, P was 150 nm. Next, as shown in step 105, the second region overlapped with the adjacent second region was synthesized.
[0047]
Thereafter, in steps 106 to 108, a connection wiring that is close to the gate portion at a distance AL or less is extracted, and a process of changing the design so as to keep it away from the gate portion is performed. Here, the distance AL is a preset reference value.
[0048]
First, in steps 106 and 107, a connection wiring portion that is close to the second region at a distance AL or less is extracted, and a point including this is set as a point to move.
[0049]
This will be described with reference to FIG. That is, as shown in FIG. 2A, the proximity distance (long side direction of the first area) between the second region 35 and the design pattern of the gate wiring 31 is evaluated, and at that time, the gate wiring close to the distance AL or less. The side (line segment) 41 of the figure was extracted. FIG. 2B shows a figure of the design pattern of the gate wiring 31. As shown in FIG. 2B, out of the corner points of the graphic including the adjacent sides, a point 42 where the distance in the long side direction of the first region is BL or less is extracted. In step 108, the point 42 is moved so that the proximity distance of the side becomes the distance AL as shown in FIG. For this purpose, the difference between the proximity distance and the distance AL at the time of processing in step 106 may be calculated and the difference distance BL may be moved. Note that the end cap portion 19 is excluded from processing because the variation in width and length hardly affects the performance of the device.
[0050]
Next, as shown in step 109, an area obtained by removing the first area from the second area is obtained by calculation to be a third area.
[0051]
Thereafter, as shown in step 110, the position of the side of the third region is moved by the distance Q so as to narrow the width of the third region in the short side direction. Thus, a fine gate portion having a desired size of 110 nm was designed. Here, the distance Q is 65 nm which is a half of 130 nm which is a difference obtained by subtracting the dimension of the gate portion 110 nm from the original dimension 240 nm of the gate wiring.
[0052]
Next, in step 111, the third area (opening width) is subjected to a first OPC (Optical Proximity Correction) process to correct the opening width.
[0053]
From the experiment, the finished dimension after RIE of the gate wiring was measured in advance with respect to the width (opening width) of the third region on the photomask, and a correction table shown in the table of FIG. The process for forming the gate wiring will be described later.
[0054]
Here, the correction values in the table of FIG. 17 are correction values given to one side of the opening width. For example, for an opening with an opening width of 450 nm, the opening width is corrected to 30 nm on one side. That is, 450 nm to 30 nm × 2 are thickened to 510 nm.
[0055]
Next, the shifter pattern design in the second OPC process and the Levenson mask fabrication is performed in steps 112 to 116.
[0056]
First, the distance between adjacent third regions was evaluated, and a group of third regions that was equal to or less than the distance R was obtained. Here, the distance R was 400 nm.
[0057]
Next, as shown in step 114, in the third region group, the dimensions of the light shielding portions on both sides of the opening portion were evaluated, and the outermost opening portion in the group was extracted. Then, a second correction was performed on the opening.
[0058]
Here, the outermost opening width is changed from P (150 nm) to 280 nm through the process of step 110, and further to 300 nm through the correction of step 111. Further, the correction values shown in the table of FIG. 18 were given. As a result, when the inner opening width was 510 nm, the outermost opening width was reduced by 10 nm on one side, and the result was 280 nm.
[0059]
The correction values shown in the table of FIG. 18 are values when the outermost opening width of the group is 300 nm, and are obtained from the experimental results as in the table of FIG. When the outer opening width is changed, the correction value needs to be changed.
[0060]
Thereafter, as shown in step 115, shifter patterns were alternately arranged with respect to the openings in the group. For example, the even number from the side closer to the design origin is the shifter and the fourth region.
[0061]
Next, through step 117, the third region is used as a design pattern for the opening of the Levenson mask.
[0062]
Further, as shown in step 118, the fourth area is made thicker by the entire dimension S in order to design drawing data of the shifter pattern at the time of producing the Levenson mask. Here, the S is 50 nm, which is about half of the desired 110 nm dimension of the gate portion.
[0063]
Further, as shown in steps 119 and 120, as the design of the trim mask, the third region is slightly reduced by the distance T, and pattern data including both of this and the pattern of the gate wiring 31 is generated and trimmed. The design pattern of the light shielding part of the mask was used. Here, T is set to 30 nm in consideration of alignment errors. As described above, the Levenson mask and trim mask were designed.
[0064]
Next, a method for manufacturing a semiconductor device using a photomask designed by the above-described design method will be described with reference to FIG.
[0065]
FIGS. 3A to 3H are cross-sectional views of the main part of the semiconductor substrate showing the gate wiring formation process. As shown in FIG. 3A, a gate oxide film 23 having a thickness of 3 nm is formed on a Si wafer (semiconductor silicon substrate) 22, and a polysilicon film 24 having a thickness of 160 nm is further stacked thereon. .
[0066]
Next, as shown in FIG. 3B, the positive resist 21 was adjusted to a thickness of 240 nm and applied to the entire surface of the substrate. After application, baking was performed at 90 ° C. for 120 seconds.
[0067]
Further, using the Levenson phase shift mask 27 designed by the above-described method shown in FIG. 3G, first exposure was performed as shown in FIG. 3C to form a latent image on the resist. Here, the latent image is a region where a chemical reaction of the resist is caused according to the projected image of the mask by irradiation with exposure light.
[0068]
As the exposure conditions, a scanner type exposure apparatus (wavelength 248 nm) was used, and NA (numerical aperture) was set to 0.5 and σ (coherency) was set to 0.3.
[0069]
Thereafter, the second exposure was performed as shown in FIG. 3D using the trim mask 28 designed by the above-described method shown in FIG. The exposure conditions are the same as those of the first exposure as the exposure apparatus, the illumination conditions are NA 0.55, σ is the outer shape 0.8 and the inner diameter 0.53 is shielded 2/3 annular illumination I went there.
[0070]
Next, as shown in FIG. 3E, the substrate is unloaded from the exposure apparatus, post-exposure bake (PEB) is performed under conditions of 110 ° C. and 120 sec, and then developed using an alkali developer. Then, the resist pattern 29 was formed by dissolving the resist in the photosensitive portion.
[0071]
Further, as shown in FIG. 3F, RIE (Reactive Ion Etching) using a gas containing fluorine is performed using the resist pattern 29 as a mask to form a pattern of the polysilicon film 24 and the gate oxide film 23.
[0072]
Thereafter, a semiconductor device was manufactured through processes such as forming a silicon nitride film (not shown).
[0073]
Here, the alignment error of the exposure apparatus used in Example 1 is a maximum of 60 nm. What is required as the controllability of the dimensions is that the dimensions of the gate portion are ± 11 nm with respect to the desired value 110 nm, and the connecting wiring portion is ± 24 nm with respect to the desired value 240 nm. Therefore, when the connection wiring part and the gate part are close to each other, the dimension of the connection wiring part may fluctuate beyond the required value of dimension controllability due to an alignment error.
[0074]
According to the present embodiment, the design pattern is changed so as to keep the adjacent connecting wiring portions away by the processing of Steps 106 to 108 in FIG. 1, thereby eliminating the dimensional variation of the connecting wiring portions due to the alignment error.
[0075]
Further, the OPC for correcting the opening width according to the original opening width is performed, and the steps shown in FIG. 1 are performed for the outermost opening width of the above group having a large area light-shielding region adjacent to the opening. Since further correction is added by performing the second OPC by the process of 114, as shown in the projection image profile of the design pattern of the Levenson mask after the second OPC in FIG. The width up to E can be made uniform.
[0076]
As described above, by adding the second OPC process, the controllability of the gate portion can be further improved. Moreover, since the dimension value after RIE is measured by experiment and the correction value is determined, the accuracy can be increased. Furthermore, the design can be completed easily in a much shorter time than the correction using simulation.
[0077]
Example 2
FIG. 5 is a flowchart showing the main part of the design process of the second embodiment of the present invention. In the second embodiment, the entire process is configured by inserting the process shown in FIG. 5 between step 108 and step 109 of the design process shown in FIG. 1 described in the first embodiment. By the way, in steps 106 to 108 shown in FIG. 1 of the first embodiment, the pattern design of the gate wiring adjacent to the gate portion is changed, and the adjacent figure is moved.
[0078]
However, depending on the design pattern of the device, there may be inconveniences due to design changes. For example, there is a concern that a problem such as a short circuit may occur when there is a pattern of another layer, for example, an element region or a contact, at a position very close to the destination of the connection wiring or the contact pad portion. Further, when the contact pad portion is moved, there is a concern that the position of the contact pad may be displaced or the contact resistance may increase. In order to avoid this, the design process shown in FIG. 5 is added in this example.
[0079]
First, in step 501, a figure of a layer other than the gate adjacent to the point moved in step 108 in FIG. 1 is extracted. At this time, the proximity distance may be set to about AL or more. Next, in step 502, it is checked whether or not the adjacent distance between the extracted graphic and the point is greater than or equal to AL, and in step 503, it is determined whether or not there is consistency with the graphic of another layer. When the figure of another layer does not exist within the proximity distance, it is determined that consistency with the other layer is achieved, and the process proceeds to step 505.
[0080]
If there is a figure in another layer, in step 504, the figure whose adjacent distance to the point is AL or less is also moved by the distance BL. This state is shown in FIGS. 6 (a) to 6 (d).
[0081]
FIG. 6A shows a desired pattern. As shown in FIG. 6B, when the element region 43 is close to the gate wiring 31 in the original design data, the adjacent point 42 is extracted, and as shown in FIG. Move. At this time, a process of extracting the element region 43 adjacent to the moved point 42 of the figure and moving it as shown in FIG. 6D is added.
[0082]
The figure moved as described above is further checked whether there is a figure in another layer within a close distance, and if it exists, the figure is moved. Such graphic movement processing is repeated. Finally, it is confirmed that there is no graphic of another layer within the proximity distance of the moved graphic, and it is determined in step 503 that consistency with the graphic of the other layer is achieved. Do until.
[0083]
Next, in step 505, the positional relationship between the contact pad connected to the connection wiring including the extracted point and the contact is confirmed. As a result, as shown in FIG. 7A, when the moved point 42 includes the point of the contact pad portion, in step 506, it is determined whether or not the position of the contact pad portion and the contact 30 is consistent. to decide. If consistency is obtained, the process proceeds to step 109 in FIG. 1. If consistency is not obtained as shown in FIG. 7B, the contact 30 is obtained in step 507 as shown in FIG. 7C. Is moved a distance BL.
[0084]
According to the present invention, as in the first embodiment, the design pattern is changed so as to keep the adjacent connection wiring portions away from each other, and thereby, the dimensional variation of the connection wiring portions due to the alignment error can be eliminated.
[0085]
Further, when the design is changed so that the contact pad portion 18 connected to the connecting wiring portion is moved, the pattern of the contact 30 connected thereto is similarly moved, so that the contact pad portion and the contact 30 can be moved. Deterioration of device performance due to an increase in contact resistance caused by misalignment can be prevented.
[0086]
Furthermore, since the connection wiring part or the contact pad part has moved, they are close to the element region, etc., and there is a concern about deterioration of device performance such as a short circuit. By extracting the figure of the layer other than the gate and moving it in the same way, it is possible to eliminate the abnormally close element region, etc., and to prevent the deterioration of the device performance due to the movement of the wiring figure it can.
[0087]
Example 3
FIG. 8 is a plan view showing a main part of the third embodiment of the present invention. According to the first and second embodiments described above, by moving the positions of the connecting wiring portion and the contact pad portion, the dimensional variation of the connecting wiring portion due to the alignment error can be prevented, and the deterioration of the device performance due to the movement can be prevented. is doing.
[0088]
However, even if the position of the side of the design pattern in the third region is moved within the range permitted by the device performance, and the position of the side of the design pattern at the opening of the Levenson mask is changed as shown in FIG. Good. 8A shows the positions of the sides of the opening 14 and the shifter opening 15 before the change, and FIG. 8B shows the positions of the sides of the opening 14 and the shifter opening 15 after the change. ing. In this case, since the length of the gate portion is shortened, it is desirable to move the position of the side of the design pattern of the element region accordingly.
[0089]
According to the present embodiment, by changing the design pattern so as to keep the adjacent gate portions away from each other, it is possible to eliminate the dimensional variation of the connection wiring portion due to the alignment error as in the first and second embodiments.
[0090]
Example 4
FIG. 9 is a flowchart showing a main part of the fourth embodiment of the present invention. In the first embodiment, the outermost opening width of the group of openings is corrected by performing the second OPC process of step 114 shown in FIG. 1, but the second OPC process is performed as in this example. You may perform in a process as shown to the flowchart of FIG.
[0091]
In step 901 of FIG. 9, first, the width of the third region 36 on the outermost side (A, B) of the group with respect to the pattern of the third region 36 shown in FIG. As shown, the width is corrected to be the same as the width of the third region 36 located adjacent to (C, D) across the gate portion.
[0092]
Next, in step 902, as shown in FIG. 10C, the width of the outermost third region 36 is further corrected outwardly by a distance U determined experimentally. However, in this example, the distance U was 50 nm.
[0093]
According to this embodiment, the distance U obtained experimentally is widened so that the gate part between the openings A and B located on the outermost side of the group is aligned with the dimension of the inner gate part such as between the openings C and D. By correcting, not only the dimensions of the gate part can be made uniform, but also the controllability of the gate part can be improved.
[0094]
Example 5
11 and 12 are flowcharts showing Embodiment 5 of the present invention. This example shows another example of the design method of the Levenson mask and the trim mask, and FIG. 11 shows the steps of the design method. FIG. 13 is a top view of an essential part of a photomask for explaining the designing method, and FIG. 14 is a sectional view of an essential part of the photomask after design.
[0095]
This embodiment will be described below. In steps 106 to 108 shown in FIG. 1 of the first embodiment, the pattern design of the gate wiring adjacent to the gate portion is changed and the adjacent figure is moved. In this example, the connecting wiring portion adjacent to the gate portion is moved to the Levenson mask. The pattern is designed to be formed by Accordingly, steps 107 and 108 in FIG. 1 are changed to the design process shown in FIG.
[0096]
In step 106 in FIG. 1, the line segment of the gate wiring 31 that is close to the second region 35 within the distance AL is extracted. Thereafter, in step 131 of this example, as shown in FIG. 13A, the figure constituting the adjacent gate wiring 31 at the distance DL is extracted from the line segment, and is indicated by a circle in FIG. The portion was designated as a sixth region 39. Here, when there is a certain figure constituting the gate wiring over the position of the distance DL, the figure is divided at the position of the distance DL. However, DL was 600 nm.
[0097]
In the next step 132, the figure within the distance DL is expanded to the entire dimension P. Here, the dimension P was set to 150 nm as in the first embodiment. This situation is indicated by the arrow in FIG. Thereafter, in step 133, as shown in FIG. 13C, an area obtained by removing the gate wiring from the graphic is obtained by calculation, and is defined as a seventh area 40.
[0098]
Further, in the next step 134, the OPC process is applied to the gate part in the same manner as the OPC process is applied to the dimensions of the gate part in step 111 of FIG. In step 111 of the first embodiment, correction was performed according to the correction values shown in the table of FIG. 17, but here, a new correction table was prepared and correction was performed accordingly.
[0099]
Further, a step shown in FIG. 12 is inserted between step 114 and step 115 shown in FIG. That is, the third region and the seventh region newly generated by the above design process are synthesized to form a new third region. Thereafter, after various steps shown in FIG. 1, the third region was used as design data for the opening of the first photomask.
[0100]
The photomask at the stage where the above design process is completed is as shown in FIG. Here, FIG. 14A is a Levenson mask, FIG. 14B is a trim mask, and FIG. 14C is a top view of an essential part of an exposure image obtained by multiple exposure of these masks. FIG. 14C is a top view showing the gate portion obtained after exposure. As shown in FIG. 14A, it can be seen that the opening portion of the Levenson mask extends not only to the fine gate portion but also to the connecting wiring portion.
[0101]
According to the present embodiment, the design pattern can be changed so that the adjacent connection wiring portions are formed by the Levenson mask, and the dimensional variation of the connection wiring portions due to the alignment error can be eliminated. The alignment error causes a misalignment of the wiring at the connecting portion of the Levenson mask and the trim mask, but this is not a problem in performance and can be ignored.
[0102]
(Appendix 1)
In general, when a memory such as SRAM is present in a design pattern in designing a processor, a certain cell pattern is repeatedly designed such as several mega for the memory portion. As described above, the pattern design may be changed using different conditions (for example, distances P, R, etc.) for the repeated pattern portion of the same cell pattern, or according to the design process of the first to fifth embodiments. Instead, an operation of manually changing the cell pattern may be performed.
[0103]
(Appendix 2)
As shown in FIG. 2D, all the figures including the side close to the second area and away from the second area are moved so that the proximity distance between the second area and the side becomes AL. Accordingly, the pattern may be changed as shown in FIG. At this time, of course, other graphics not connected to the graphics shown in FIG. 2D are not processed.
[0104]
(Appendix 3)
In the pattern design methods described in the first to fifth embodiments, OPC is performed to form the fine gate portion at a desired value. The connecting wiring portion is formed using a trim mask. In order to improve the dimensional controllability of the connecting wiring portion, an additional step of applying OPC to the trim mask pattern and the gate wiring region in the above design method is added. May be. Thereby, the dimensional controllability of the connection wiring part can also be improved.
[0105]
(Appendix 4)
A process as shown in FIG. 15 may be inserted between step 116 and step 117 of the first embodiment. From the third region, a design pattern of the opening portion of the Levenson mask and a pattern of the region covering the gate portion of the trim mask are created. In step 151, the distance between the outermost third regions of each group of adjacent third regions is calculated.
[0106]
As a result, for example, as shown in FIG. 16A, when the distance 45 between the groups of the openings of the Levenson mask is close to V or less, the following problem may occur.
[0107]
For example, if V is 100 nm, the dimension on the photomask is 400 nm, which is four times that. When producing a fine pattern of 400 nm or less on a photomask, the pattern may not be resolved depending on the performance of an EB (Electron Beam) drawing apparatus used for producing the photomask.
[0108]
Such a pattern below the resolution limit of the drawing apparatus should not exist as design data on the photomask.
[0109]
Therefore, in step 152, the outermost third region of the adjacent group with the distance V or less is extracted, and in step 153, the outermost third region of the adjacent group is moved outward in the direction orthogonal to the first region. To V / 2 and synthesize the third region. The result is shown in FIG. 16B, and the third region outside the two groups is synthesized by expanding the outermost third region of the group outward, that is, in a direction orthogonal to the gate portion. As a result, adjacent groups of the Levenson mask opening pattern and the trim mask shading pattern are expanded and combined, and a pattern equal to or less than the resolution limit of the drawing apparatus does not exist on the photomask.
[0110]
(Appendix 5)
In the first to fifth embodiments, the pattern design method for the pattern of the Levenson phase shift mask that is the first photomask and the pattern of the trim mask that is the second photomask has been described. By the way, the pattern of the first photomask and the pattern of the second photomask may be arranged in different regions in one photomask.
[0111]
By forming both patterns on one mask, alignment errors during multiple exposure can be reduced.
[0112]
In addition, with respect to the pattern design method of the present invention, the same effect can be obtained even if the order of the included steps is changed without departing from the gist of the present invention.
[0113]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to eliminate the dimensional variation of the connection wiring portion due to the alignment error, and it is possible to improve the controllability of the gate portion.
[Brief description of the drawings]
FIG. 1 is a flowchart illustrating steps of a mask pattern design method according to Embodiment 1 of the present invention.
FIG. 2 is a top view of relevant parts for explaining the design of the photomask of Example 1;
FIG. 3 is a cross-sectional view of a principal part of a semiconductor substrate for describing a gate wiring formation step of Example 1 described above.
FIG. 4 is a diagram showing a profile of a projected image of the photomask of Example 1 described above.
FIG. 5 is a flowchart illustrating a main part of a photomask design process according to a second embodiment of the present invention.
6 is a top view of relevant parts for explaining the design of the photomask of Example 2. FIG.
FIG. 7 is a top view of another main part for explaining the design of the photomask of the second embodiment.
FIG. 8 is a top view for explaining a photomask design process of Example 3 of the present invention.
FIG. 9 is a flowchart illustrating a photomask design process according to the fourth embodiment of the present invention.
FIG. 10 is a diagram for explaining the design of a photomask according to the fourth embodiment.
FIG. 11 is a flowchart illustrating a photomask design process according to a fifth embodiment of the present invention.
FIG. 12 is a flowchart illustrating the fifth embodiment.
FIG. 13 is a top view of relevant parts for explaining the photomask design process of Example 5;
14 is a top view of relevant parts for explaining the design of the photomask of Example 5. FIG.
FIG. 15 is a flowchart illustrating another photomask design process of the present invention.
FIG. 16 is a top view of relevant parts for explaining another photomask design process of the invention.
17 is a table showing first dimension correction values in the photomask design process of Example 1. FIG.
18 is a table showing second dimension correction values in the photomask design process of Example 1. FIG.
FIG. 19 is a top view of relevant parts showing a pattern example of a gate wiring of a conventional RISC processor.
FIG. 20 is a top view of relevant parts for explaining a photomask for multiple exposure used for forming a conventional gate wiring;
FIG. 21 is a flowchart for explaining a conventional design process of a photomask for multiple exposure.
FIG. 22 is a top view of relevant parts for explaining a manufacturing process according to a conventional design of a photomask for multiple exposure.
FIG. 23 is a diagram for explaining a problem in the conventional design of a photomask for multiple exposure.
FIG. 24 is a diagram for explaining a problem in the conventional design of a photomask for multiple exposure.
FIG. 25 is a diagram showing a design pattern of a conventional photomask for multiple exposure.
26 is a projection view showing a profile of the design pattern shown in FIG. 25. FIG.
[Explanation of symbols]
11, 31 Gate wiring
12, 32, 43 Device area
13 Shading part
14 opening
15 Shifter opening
16 Gate part
17 Connection wiring part
18 Contact pad
19 End cap
20 Shading pattern part covering the gate part
21 resist
22 Semiconductor silicon substrate
23 Gate oxide film
24 Polysilicon film
25 Latent image area
26 Exposure light
27 Levenson Mask
28 Trim mask
29 resist pattern
30 contacts
33 0th area
34 First area
35 Second area
36 Third area
37 4th area
38 5th area
39 Region 6
40 Seventh area
41 Adjacent line segments
42 Corner points of the extracted figure
44 Resolution line width
45 distance

Claims (2)

In a mask pattern design method for designing a mask pattern by generating a plurality of pattern data by performing a logical operation using pattern data of an element region and wiring,
Enter the original design pattern of the wiring and element area,
The element region is expanded to be the 0th region,
The overlapping area of the wiring and the 0th area is calculated as the first area,
Extending the first region by a preset value in a direction orthogonal to the gate portion to form a second region,
Combining the second region adjacent to and overlapping the second region;
Including a process of moving a part or all of the wiring close to the second area to be equal to or less than a preset distance to be equal to or greater than the set distance,
Detect whether there is a component of a device that is close to the set distance or less in part or all of the wiring that has been subjected to the processing to move away,
If detected, perform the process of moving away the constituent elements of the corresponding device from the part or all of the wiring subjected to the process of moving away more than the set distance,
After that, it is detected whether there is another component of the device that is close to the set distance or less in the component of the device that has been subjected to the away process, and if detected, the component of the device is moved away first a process done away from the components of the device said set distance or more, to the components of other devices below the set distance is no longer detected, have repeated rows,
The mask pattern design method, wherein the wiring overlapping the zeroth region is a wiring formed by a Levenson mask, and the other wiring is a wiring formed by a trim mask . When a part or all of the wiring is approaching the set distance or less in the second region,
Find a line segment close to any of the second regions,
Extracting the corner point of the figure located below the preset distance from the adjacent line segment, including the corner point of the figure located on the line segment,
2. The mask pattern design method according to claim 1, wherein the mask pattern design method is performed by an algorithm for moving the pattern in parallel in an adjacent direction.

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