KR101566639B1 - Method for improving error checking and correction performance of 3-d memory - Google Patents

Abstract

Disclosed is a method for improving error checking and correction performance of a memory. The method for improving the error checking and correction performance of the memory comprises the steps of: in a memory cell array with a matrix structure composed of memory cells and a spare cell array with a matrix structure composed of spare memory cells for replacing a defected memory cell which is a memory cell where a defect occurs, replacing a defected column of the memory cell array having the defected memory cell with a spare column of the spare cell array; storing a check bit of an error correction code in one or more memory cells within the defected column; storing defect information on the defected memory cell; selecting whether to use the memory cells storing the check bit in error checking and correction of the memory by using the detect information; and performing the error checking and correction of the memory using the memory cell selected according to the selection result.

Description

[0001] METHOD FOR IMPROVING ERROR CHECKING AND CORRECTION PERFORMANCE OF 3-D MEMORY [0002]

The present invention relates to a three-dimensional memory, and more particularly, to a method for improving error checking and correcting (ECC) performance of a three-dimensional memory.

As the memory density increases, the incidence of soft errors increases and the proportion of ECC memory increases. Soft errors may be caused by electromagnetic interference, static electricity, cosmic rays, and the like. For example, a charge generated by ionization radiation can cause a soft error in the integrated circuit. For example, when alpha particles pass through a three-dimensional memory, the alpha particles generate an electron-hole pair near the memory cell, and when the amount of charge of the generated electron-hole pair exceeds a certain threshold value, It may cause an error. In addition, when the degree of integration of the memory is increased, the defect occurrence rate of the memory cell can also be increased.

The error checking correction in the memory for checking and correcting errors (errors) generated in the memory is performed through error correction codes. In order to overcome the errors in memory, error check and correct are essential, and memory error correction codes such as SEC-DED-code and SEC-DED-DAEC code are used in memory design. It became an integral part.

In order to overcome the limitation of the storage capacity of a memory, studies on a three-dimensional memory have been actively conducted recently. In the case of a three-dimensional memory in which a plurality of memory layers are stacked, There is a problem in that the probability of occurrence is high. This is because the upper memory layer is the first to strike the upper memory layer among the plurality of memory layers in which most of the alpha particles are stacked, thereby protecting the lower memory layers from the alpha particles.

In addition, the reliability of the three-dimensional memory, which has been attracting attention recently, is determined by the reliability of the upper slice as a main factor and it is necessary to develop a method for improving the error checking correction performance of the upper memory layer of the three-dimensional memory.

SUMMARY OF THE INVENTION It is an object of the present invention to improve the error checking correction performance of a three-dimensional memory by storing a check bit used for error checking of an upper memory layer of a three-dimensional memory in a spare cell array of lower memory layers And to provide a method for improving the error checking correction performance of the three-dimensional memory.

According to an aspect of the present invention, there is provided a method for improving the error correction correction performance of a three-dimensional memory, including: a memory cell array having a matrix structure including memory cells; A plurality of memory layers each having a spare cell array of a matrix structure made up of spare memory cells for replacing the plurality of memory layers, and a master layer controlling the plurality of memory layers, The method comprising the steps of: a) forming a check bit, which is used for error checking of an upper memory layer stacked on top of the plurality of memory layers, on a lower memory layer stacked below the upper memory layer, Storing in at least one of the spare cell arrays; And b) performing error checking correction of the upper memory layer using stored check bits.

For example, a memory cell array having a matrix structure of memory cells may have an M (row) × N (column) structure, a spare cell array having a matrix structure of spare memory cells may have M X L (column, column) structure.

For example, in a three-dimensional memory in which four memory layers are stacked vertically, the memory layer stacked on the lowermost layer is referred to as layer 4, the memory layer stacked thereon is referred to as layer 3, If the memory layer is referred to as layer 2 and the stacked memory layer is referred to as layer 1 in layer 4, layer 3 and layer 2, layer 1 may be an upper memory layer, layer 4 and layer 3 Layer 2 can be an upper memory layer. Thus, the upper memory layer may be changed depending on whether the memory layer in which the concept is stacked below exists.

Error checking and correction refers to a method of checking and correcting errors in data using error correction codes. In general, inspection can be performed over a wider range than correction.

The error correction code may be a SEC-DED code or a SEC-DED-DAEC (linear-block code), but is not limited thereto .

In one embodiment, the step a) includes the steps of: determining whether a defect column having a defective memory cell exists in the memory cell array for each of the plurality of memory layers; Replacing the spare column of the spare cell array of the memory layer having the defective column with the defective column if the defective column is present; And storing a check bit used for error checking of the upper memory layer in a spare column not used for substitution among the plurality of memory layers.

For example, information on whether a defective column is present may be recorded during firmware reset or by a reset or booting process with built-in self-repair (BISR) . In addition, such information may be stored in a separate CAM (Content Addressable Memory) which may be provided in the three-dimensional memory. CAM is an associative memory that is a special memory used in very fast searching applications.

In one embodiment, the step of storing a check bit used for error checking correction of an upper memory layer in a spare column not used for substitution among the plurality of memory layers includes the steps of: So that a signal can be transmitted and received between the first and second electrodes; And storing a check bit used for error checking correction of the upper memory layer.

In one embodiment, the electrical connection between the spare column and the upper memory layer, which is not used for replacement, can be performed through control of the column selection line of the corresponding memory layer in which the spare column not used as an alternative is disposed .

The present invention has the effect of improving the error checking correction performance of the upper memory layer by storing the check bits used for the error check correction of the upper memory layer in the three-dimensional memory in the spare cell array of the lower memory layer .

In the case of three-dimensional memory, the error checking correction performance of the upper memory layer depends on the error checking correction performance of the entire three-dimensional memory, thereby improving the error checking correction performance of the upper memory layer. There is an effect that can be.

FIG. 1 is a diagram for explaining a structure of a three-dimensional memory to which a method for correcting error checking of a three-dimensional memory according to an embodiment of the present invention is applied.
FIG. 2 is a conceptual diagram for explaining a method of correcting errors in a three-dimensional memory according to an embodiment of the present invention.
3 is a flowchart of a method for correcting error checking of a three-dimensional memory according to an embodiment of the present invention.
4 is a conceptual diagram for explaining a method of storing check bits of an upper memory layer in a spare cell array of a lower memory layer according to an embodiment of the present invention.
5 is a conceptual diagram for explaining a method of storing check bits of an upper memory layer according to the first embodiment of the present invention in a spare cell array of a lower memory layer.
6 is a conceptual diagram for explaining a method of storing check bits of an upper memory layer in a spare cell array of a lower memory layer according to the second embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. Wherein like reference numerals refer to like elements throughout.

FIG. 1 is a diagram for explaining a structure of a three-dimensional memory to which a method for correcting error checking of a three-dimensional memory according to an embodiment of the present invention is applied.

Referring to FIG. 1, a three-dimensional memory to which an error checking and correcting method of a three-dimensional memory according to an exemplary embodiment of the present invention is applied includes a plurality of memory banks (Bank1 to Bank8) And a plurality of memory layers in which a plurality of memory banks are arranged are stacked. The plurality of memory layers are configured to transmit and receive signals to and from each other via a silicon floating electrode (TSV) disposed at the center for each of the memory layers. Each of the plurality of memory layers includes a column select line (CSL ) So that signals can be transmitted and received through at least one of the memory column and the spare column of the memory layer through the column select line. In addition, transmission and reception of signals between a plurality of memory layers can be controlled by a master layer.

Each of the memory banks includes a spare cell array having a matrix structure including a memory cell array having a matrix structure including memory cells and spare memory cells for replacing defective memory cells with defective memory cells.

1 shows a structure in which a plurality of memory banks are arranged on one memory layer. However, a plurality of memory layers in which one memory bank is arranged for each memory layer form a group, . Such a simplified structure can be confirmed through FIG. 2A.

FIG. 2 is a conceptual diagram for explaining an error checking and correcting method of a three-dimensional memory according to an embodiment of the present invention, FIG. 3 is a flowchart of an error checking and correcting method of a three- FIG. 8 is a conceptual diagram for explaining a method of storing check bits of an upper memory layer in a spare cell array of a lower memory layer according to an embodiment of the present invention. FIG. In FIG. 4, WL denotes a word line, BL denotes a bit line, CSL denotes a column seclect line, BL_spare denotes a bit line of a spare cell array, And CLS_spare means a column selection line for selecting a spare column for transmitting and receiving signals.

Referring to FIGS. 2 to 4, a method for correcting error checking of a three-dimensional memory according to an embodiment of the present invention includes replacing a memory cell array having a matrix structure made up of memory cells and a defective memory cell having a defective memory cell A method for correcting error checking of a three-dimensional memory having a plurality of memory layers each including a spare cell array having a matrix structure of spare memory cells for controlling the plurality of memory layers and a master layer controlling the plurality of memory layers, A check bit used for error checking of an upper memory layer stacked on top of the plurality of memory layers is set to one of a lower memory layer stacked below the upper memory layer and a spare memory cell array (S100) and the stored check bit It may include a step (S200) of performing the error check of the correction layer.

In order to perform a method of correcting error checking of a three-dimensional memory, a check bit used for error checking of an upper memory layer stacked on top of the plurality of memory layers is divided into a lower memory layer And at least one of the spare cell arrays of the upper memory layers (S100).

2, each of the plurality of memory layers includes a memory cell array and a spare cell array. The memory array is a matrix structure of memory cells, And a spare array may be a matrix structure including spare memory cells for replacing a defective memory cell in which a defect occurs in the memory cell.

For example, in order to improve the error checking and correcting ability of the upper memory layer stacked above the plurality of memory layers, a plurality of memory layers are stacked along the vertical direction, The spare cell array of the lower memory layers can be used as the spare cell array of the upper memory layer.

Referring to FIG. 4, each of the lower memory layers includes a column select line (CSL), and the column select line of the lower memory layers and the upper memory layer are electrically connected to each other. Can be used as the spare cell array of the upper memory layer.

For example, a signal can be transmitted and received between the upper memory layer and the lower memory layer via the silicon penetration electrode (TSV), and this signal can be transmitted to and received from the spare cell array of the lower memory layer through the column select line of the lower memory layer . Transmission and reception of such a signal can be performed by controlling ON / OFF of the column select line of the lower memory layer, and by electrically connecting the spare cell array of the lower memory layer to the upper memory layer through the column select line of the lower memory layer, A spare cell array of a memory layer can be used as a spare cell array of an upper memory layer. Therefore, the check bit used for error checking correction of the upper memory layer can be stored in the spare cell array of the lower memory layer. The method of storing the check bit used for error checking of the upper memory layer in the spare cell array of the upper memory layer is the same as that of the commonly used check bit storing method, and thus a detailed description thereof will be omitted.

In operation S100, it is determined whether a defective column having a defective memory cell exists in the memory cell array for each of the plurality of memory layers (S120). If the defective column exists, (S140) of replacing the spare column of the spare cell array of the upper memory layer with the defective column (S140) and storing a check bit used for error checking of the upper memory layer in a spare column not used for substitution among the plurality of memory layers S160).

It is determined whether a defect column having a defective memory cell exists in the memory cell array for each of the plurality of memory layers (S120). This is to repair the memory cell array by replacing the defective column of the memory cell array having the defective memory cell with the spare column of the spare cell array. For example, the replacement of a defective column and a spare column may be performed by turning on / off a signal line connecting the defective column and the spare column. The signal line may be, for example, a column signal line (CSL).

If the defect column is present according to the determination result, the spare column of the spare cell array of the memory layer having the defective column is replaced with the defective column (S140). Referring to FIG. 6, one defective memory cell exists in the memory cell array of the upper memory layer (layer 1), and the defective column including the defective memory cell is repaired as a spare cell of the spare cell array. The repaired memory layer is shown on the right side of FIG. 6, and the replaced defect column is marked in black. Through this alternative scheme, the lower memory layers (layer 2 through layer 4) can be repaired.

When replacement is completed, a check bit used for error checking of the upper memory layer is stored in a spare column not used for substitution among a plurality of memory layers (S160). For example, it is possible to control a signal to be transmitted / received through a column signal line CSL which controls an unsubstituted spare column, and then store a check bit used in error checking of the upper memory layer in the spare column. That is, the memory cell may be electrically connected through the column signal line CSL so that a signal can be transmitted / received between the spare column not used for replacement and the upper memory layer.

The method for storing the check bit used for error checking of the upper memory layer is the same as that of the first embodiment except that there is no defect memory in the plurality of memory layers below and the case where there is a defect memory in the plurality of memory layers . ≪ / RTI >

Example 1

5 is a conceptual diagram for explaining a method of storing check bits of an upper memory layer according to the first embodiment of the present invention in a spare cell array of a lower memory layer.

Referring to FIG. 5, a plurality of memory layers (layer 1 to layer 4) may each include a spare cell array having a 2X2 structure, and a plurality of memory layers have no defective memory cells. 2 to layer 4) Each spare cell array can be used as a spare cell array of an upper memory layer (layer 1).

Therefore, the check bit used for error checking of the upper memory layer (layer 1) is stored in the spare cell array of the upper memory layer (layer 1) indicated by 0 and 1 of the upper memory layer (layer 1) And the check bit used for error checking correction of the upper memory layer (layer 1) is a spare bit of each of the lower memory layers (layer 2 to layer 4) indicated by 2 to 7 of the upper memory layer (layer 1) May be stored in a cell array.

Example 2

6 is a conceptual diagram for explaining a method of storing check bits of an upper memory layer in a spare cell array of a lower memory layer according to the second embodiment of the present invention.

Referring to FIG. 6, a plurality of memory layers (layers 1 to 4) may each include a spare cell array having a 2X2 structure, and a plurality of memory layers have defective memory cells. The column may be replaced with a spare cell column provided in the corresponding memory layer so that the memory array may be repaired. When the repair is completed, the check bit used for error check correction of the upper memory layer (layer 1) may be stored in a spare column not used for replacement among the spare cell array of each of the lower memory layers (layer 2 to layer 4) .

Therefore, the check bit used for error check correction of the upper memory layer (layer 1) can be stored in a spare column of the upper memory layer (layer 1) indicated by 0 of the upper memory layer (layer 1) , The check bit used for error checking correction of the upper memory layer (layer 1) is not used for replacement of the lower memory layers (layer 2 to layer 4) indicated by 1 to 3 of the upper memory layer (layer 1) Can be stored in a spare column.

Next, the error check correction of the upper memory layer is performed using the stored check bits (S200). The error checking may be performed by a commonly used method, for example, the SEC-DED Hsiao code method.

The error checking and correcting method of the three-dimensional memory according to the embodiment of the present invention is characterized in that the check bits used for error checking of the upper memory layer can be stored in the spare cell array of the lower memory layer, Can be improved. This will be described with reference to [Table 1].

[Table 1] shows the results of a maximally bearable bit error rate. The conventional ECC is a result of measuring the maximum allowable bit error rate of a three-dimensional memory through a conventional error checking correction method, The ECC according to the present invention shows a result of measuring a maximum allowable bit error rate of a three-dimensional memory by applying a method of correcting errors in a three-dimensional memory according to an embodiment of the present invention. (256MB × 4, 128MB × 8, and 64MB × 16), which are composed of 4-layer, 8-layer, and 16-layer memories using 32-bit and 64-bit words, respectively. -DED Hsiao code method was used. NL is the number of stacked memory layers, and mS is used for error checking of the upper memory layer. In Table 1, nLmS (n = 4, 8, 16, m = 1, 2, 3 and 4) The number of spare columns in which the check bits are stored.

Conventional ECC The ECC Increase rate (times) 32-bit 64-bit 32-bit 64-bit 32-bit 64-bit 4L1S 2.65E-6 1.83E-6 5.21E-6 3.60E-6 Approximately 1.97 Approximately 1.97 4L2S 3.34E-6 2.30E-6 1.11E-5 7.60E-6 Approximately 3.32 Approximately 3.30 4L3S 4.21E-6 2.90E-6 1.46E-5 1.01E-5 Approximately 3.47 Approximately 3.47 4L4S 5.30E-6 3.65E-6 1.84E-5 1.27E-5 Approximately 3.48 Approximately 3.47 8L1S 3.33E-6 2.30E-6 1.19E-5 8.23E-5 Approximately 3.59 Approximately 3.58 8L2S 4.19E-6 2.90E-6 1.55E-5 1.07E-5 Approximately 3.70 Approximately 3.69 8L3S 5.29E-6 3.65E-6 1.96E-5 1.35E-5 Approximately 3.70 Approximately 3.70 8L4S 6.65E-6 4.60E-6 2.47E-5 1.70E-5 Approximately 3.71 Approximately 3.70 16L1S 4.18E-6 2.89E-6 1.42E-5 9.80E-5 Approximately 3.39 Approximately 3.39 16L2S 5.26E-6 3.64E-6 1.79E-5 1.23E-5 Approximately 3.40 Approximately 3.39 16L3S 6.64E-6 4.58E-6 2.26E-5 1.55E-5 Approximately 3.40 Approximately 3.39 16L4S 8.36E-6 5.77E-6 2.84E-5 1.96E-5 Approximately 3.40 Approximately 3.39

Referring to Table 1, when the result of the maximum permissible bit error rate measured by applying the error checking correction method of the three-dimensional memory according to the embodiment of the present invention is smaller than the maximum permissible bit It can be confirmed that the error rate is increased from about 1.97 times to about 3.70 times as much as the result of the error rate. As a result, it can be expected that the error checking and correcting method of the three-dimensional memory according to the embodiment of the present invention can be operated stably even in an environment where many soft errors may occur.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. Accordingly, the true scope of the present invention should be determined by the following claims.

Claims (4)

A plurality of memory layers each including a memory cell array having a matrix structure made up of memory cells and a spare cell array having a matrix structure made up of spare memory cells for replacing defective memory cells defective in the memory cells are stacked And a master layer for controlling the plurality of memory layers, the method comprising the steps of:
a check bit used for error checking of an upper memory layer stacked on an upper one of the plurality of memory layers is divided into a lower memory layer stacked below the upper memory layer and a spare memory cell array Storing in at least one of; And
b) performing error checking correction of the upper memory layer using stored check bits,
The step a)
Determining whether a defective column having a defective memory cell exists in the memory cell array for each of the plurality of memory layers;
Replacing the spare column of the spare cell array of the memory layer having the defective column with the defective column if the defective column is present; And
Storing a check bit used for error checking of the upper memory layer in a spare column not used for substitution among the plurality of memory layers.
delete The method according to claim 1,
The step of storing a check bit used for error checking of an upper memory layer in a spare column not used for substitution among the plurality of memory layers,
Electrically connecting the spare memory column and the upper memory layer so that signals can be transmitted and received; And
And storing a check bit used for error checking of the upper memory layer.
The method of claim 3,
The electrical connection between the spare memory column and the spare memory layer, which is not used for replacement,
Dimensional memory is controlled through control of a column selection line included in a memory layer in which a spare column not used for substitution is disposed.

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