KR20070078175A - A nand flash memory device and method of manufacturing the same - Google Patents

Abstract

A NAND flash memory device and its manufacturing method are provided to prevent the generation of an OPC(Optical Proximity Correction) error and a pattern distortion in an exposure process by forming regularly active and field dummy patterns within a pickup region between cell blocks. A NAND flash memory device includes cell blocks, a well pickup, and a dummy pattern. The cell blocks(C) are spaced apart from each other on a semiconductor substrate with an active region(A) and an isolation region(B). The cell block includes a gate line and source/drain select lines at both sides of the gate line. The well pickup(E) is formed at a first region between the cell blocks. The dummy pattern(F) is formed at a second region between the cell blocks. The dummy pattern is composed of active and field dummy patterns(F-1,F-2) alternately arranged with each other.

Description

A NAND flash memory device and method of manufacturing the same

1A to 1C are layout views of devices sequentially shown to explain a NAND flash memory device and a method of manufacturing the same according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

A: active area B: field area

C: cell block D: gate line

E: Well Pickup F: Dummy Pattern

F-1: Active Dummy Pattern F-2: Field Dummy Pattern

P: pickup area

The present invention relates to a NAND flash memory device and a method of manufacturing the same, and more particularly, to a NAND flash memory device that prevents bit-fail by preventing distortion of the last pattern of a cell block and a method of manufacturing the same. .

An active region and a field region are repeatedly determined in the cell block of the NAND flash memory, and a tunnel oxide film and a polysilicon film for floating gate are stacked in the active region. The word line is formed in a direction orthogonal to the active region and the field region, and the polysilicon film for floating gate is patterned by the word line to form a floating gate under the word line. When the active region and the field region are determined and a floating gate polysilicon film is formed in the active region, a pattern not affecting the operation of the device is inserted in the outermost active region (cell block transistor region). Formation can be facilitated. These patterns are not the main patterns used in the implementation of the memory device, but dummy patterns that only assist in the formation of the main patterns. Such dummy patterns play a very important role in the formation of a correctly defined main pattern. Meanwhile, a well pickup region is formed between the cell block and the cell block, and a well pickup is formed at the center of the well pickup region.

However, since the dummy pattern is not formed in the well pickup region, when the active region and the field region in which the polysilicon film for floating gate is formed and the field region are determined, the patterns formed on the outermost active region are distorted due to the characteristics of the exposure equipment and the etching loading effect. This can cause the following problems.

First, due to the characteristics of the exposure equipment, the depth of focus may be due to an optical error correction (OPC) error in which the outermost pattern collapses or bridges, and the effects of scratches on the lens of the exposure equipment. ; DOF) There is a high possibility of pattern distortion during exposure due to lack of margin.

Second, due to the loading effect during the etching process, the dummy pattern area having a weak overlay margin becomes more vulnerable to pattern distortion. That is, when the polysilicon layer is etched in a state in which the overlay margin between the device isolation layer and the photoresist pattern is insufficient, the tunnel oxide layer on the upper portion of the active region is very thin, and thus the upper portion of the active region is etched. Even if the active region is not etched, if the control gate and the active region are too close to each other, the device may be stressed by repeated driving of the device, causing leakage to a thin portion of the tunnel oxide layer. As a result, when a dielectric film is present between the active region and the gate line, and a high voltage is applied during programming or erasing, the dielectric layer is insulated and a short is generated between the gate and the active region.

An object of the present invention devised to solve the above problems is to form a dummy pattern in the pickup area between the cell block and the cell block to prevent the pattern formed on the outer edge of the cell block from being distorted due to the effect of OPC error or lens aberration. In addition, the present invention provides a NAND flash memory device and a method of manufacturing the same, which also prevent distortion caused by a loading effect during an etching process.

A NAND flash memory device according to an embodiment of the present invention may include a plurality of gate lines formed to be spaced at a predetermined distance orthogonal to an active region and a field region on a semiconductor substrate, and a source selection line and a drain selection formed on both sides of the plurality of gate lines. Cell blocks including a line, a well pickup formed in a predetermined region between the cell block and the cell block, and a dummy pattern regularly formed between the cell block and the cell block except the region in which the well pickup is formed. A NAND flash memory device is provided.

A method of manufacturing a NAND flash memory device according to an exemplary embodiment of the present invention may include sequentially forming a tunnel oxide film, a first polysilicon film, and a nitride film on a semiconductor substrate on which a cell region, a pickup region, and a peripheral region are defined. Etching a portion of the nitride film, the first polysilicon film, the tunnel oxide film, and the semiconductor substrate to form a first trench in the cell region, and simultaneously forming an active dummy pattern between the cell region and the cell region, and etching a predetermined region. Forming a second trench in the peripheral region deeper than the first trench depth, and then forming an isolation layer in the first and second trenches to fill the first and second trenches to form an isolation layer; Forming a second polysilicon film on the entire structure and etching the second polysilicon film on the device isolation layer to the first poly in the cell region At the same time of forming the floating gate consisting of a silicon film and a second polysilicon film provides a process for the preparation of a NAND flash memory device including a single field which dummy pattern is formed in series between said cell area and cell area.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1C are layout diagrams of devices sequentially shown to explain a NAND flash memory device according to an exemplary embodiment of the present invention. This is because the active dummy pattern F-1 is formed in the pick-up area P between the cell block C and the cell block C during a floating gate (FG) forming process using self-aligned shallow trench isolation (SA-STI). ) And the field dummy pattern (F-2), the process step is the same as the manufacturing method of the NAND flash memory device to which SA-STI is applied. In addition, the present invention uses a dual trench formation method having different trench depths formed in the cell region and the peripheral region during the trench isolation process for device isolation.

Referring to FIG. 1A, a tunnel oxide film, a first polysilicon film, and a nitride film are sequentially formed on a semiconductor substrate in which an active region A and a field region B are defined, and then the active region A of the cell block C is formed. ) Forms a first photoresist pattern. When the photoresist pattern is formed on the active area A of the cell block C, the active area A and the field area B are determined in the pickup area P between the cell block C and the cell block C. The active dummy pattern F-1 is formed, but is formed in the pickup region P except for the region where the well pickup E is formed. At this time, when the active dummy pattern F-1 is formed in the pickup region P, the width a and the pitch b of the photoresist pattern formed on the active region A of the cell block C are considered. The width of the photoresist pattern formed on the active region C of the cell block C is greater than the width a and the pitch b in consideration of the overlap margin with the second polysilicon film for floating gate, which is a subsequent process. Or small.

Referring to FIG. 1B, a portion of the nitride film, the first polysilicon film, the tunnel oxide film, and the semiconductor substrate formed in the field region B using the photoresist pattern as a mask is sequentially etched to form the cell block C and the pickup region P. The first trench is formed in the trench, and the second trench is formed in the peripheral region, and then the photoresist pattern is removed. An insulating layer is formed in the first and second trenches to fill the first and second trenches, thereby forming an isolation layer in the field region B. FIG.

As described above, the active dummy pattern F-1 is formed in the pickup area P to determine the active area A and the field area B. FIG. However, since the active dummy pattern F-1 formed in the pick-up region P is adversely affected during the subsequent process of forming the control gate, the cell block C may be formed during the process of forming the second trench for device isolation in the peripheral region. And the active dummy pattern F-1 region M formed in the pickup region P between the cell block C and the cell block C are removed by using a mask. At this time, the active dummy patterns F-1 are not completely removed, but remain partially.

Referring to FIG. 1C, after removing the nitride film formed on the active region A, a second polysilicon film for floating gate is formed on the entire structure. After forming the second photoresist pattern on the active region C, the second polysilicon layer is etched using the second photoresist pattern as a mask to form a floating gate including the first and second polysilicon layers. At this time, due to the floating gate formed on the active region A, a space pattern in the form of a space is formed in the field region B of the cell block C, and a region where the well pickup E is formed. A field dummy pattern F-2 having a space shape is formed in the field area B of the pick-up area P, which is excluded.

The field dummy pattern F-2 formed in the pickup region P is formed in consideration of the width c and pitch d of the space pattern formed in the cell block C, but overlaps with the device isolation layer. In consideration of this, it may be formed larger or smaller than the width c and the pitch d of the space pattern formed in the cell block C.

The field dummy pattern F-2 formed in the pick-up area P does not need to be removed because a problem does not occur by a subsequent process. As described above, the OPC is formed by forming dummy patterns F including the active dummy pattern F-1 and the field dummy pattern F-2 in the pickup region P between the cell block C and the cell block C. Due to the influence of error and lens aberration, it is possible to prevent the last pattern of the cell block C from being distorted during the exposure process and to prevent distortion caused by the loading effect during the etching process.

Subsequently, after the dielectric film and the conductive layer are formed on the entire structure, the conductive layer, the dielectric film, and the second and first polysilicon films are patterned to cross the gate line D in the direction crossing the active region A and the field region B. FIG. ) And a source select line (SSL) and a drain select line (DSL) are defined on both sides of the plurality of gate lines (D).

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention has the following effects.

First, by regularly forming dummy patterns in the pickup area between the cell block and the cell block, it is possible to prevent the last pattern of the cell block from being distorted due to the influence of OPC error or lens aberration.

Second, it is possible to prevent the distortion of the pattern due to the loading effect during the etching process.

Claims (11)

Cell blocks including a plurality of gate lines formed to be spaced at a predetermined distance orthogonal to the active region and the field region on the semiconductor substrate, and source select lines and drain select lines formed on both sides of the plurality of gate lines; A well pickup formed in a predetermined region between the cell block and the cell block; And And a dummy pattern regularly formed between the cell block and the cell block except for the region where the well pickup is formed. The NAND flash memory device of claim 1, wherein the dummy pattern comprises an active dummy pattern and a field dummy pattern. The NAND flash memory device of claim 2, wherein the active dummy pattern is larger or smaller than a width of the pattern of the active region formed in the cell block and a pitch between the pattern and the pattern of the active region. The NAND flash memory device of claim 2, wherein the field dummy pattern is larger or smaller than a width of the pattern of the field region formed in the cell block and a pitch between the pattern and the pattern of the field region. 3. The NAND flash memory device of claim 2, wherein the active dummy pattern is removed in a process of forming a device isolation trench in the peripheral area. The NAND flash memory device of claim 2, wherein the field dummy pattern has a space between the active region and the active region. Sequentially forming a tunnel oxide film, a first polysilicon film, and a nitride film on a semiconductor substrate in which a cell region, a pickup region, and a peripheral region are defined; Etching a portion of the nitride film, the first polysilicon film, the tunnel oxide film, and the semiconductor substrate to form a first trench in the cell region, and simultaneously forming an active dummy pattern between the cell region and the cell region; After etching a predetermined region to form a second trench in the peripheral region deeper than the first trench depth, an isolation layer is formed in the first and second trenches to fill the first and second trenches to form an isolation layer. Doing; And A second polysilicon film is formed on the entire structure, and the second polysilicon film is etched on the device isolation layer to form a floating gate including the first polysilicon film and the second polysilicon film in the cell region. And forming a field dummy pattern between the cell region and the cell region. The NAND flash memory device of claim 7, wherein the active dummy pattern is larger or smaller than a width of the pattern of the active region formed in the cell block and a pitch between the pattern and the pattern of the active region. The NAND flash memory device of claim 7, wherein the field dummy pattern is larger or smaller than a width of the pattern of the field region formed in the cell block and a pitch between the pattern and the pattern of the field region. The NAND flash memory device of claim 7, wherein the active dummy pattern is removed during the second trench formation process of the peripheral region. The NAND flash memory device of claim 7, wherein the field dummy pattern has a space between the active region and the active region.

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