CN107112355B - 具有金属栅的分裂栅非易失性闪存存储器单元及其制造方法 - Google Patents

具有金属栅的分裂栅非易失性闪存存储器单元及其制造方法 Download PDF

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CN107112355B
CN107112355B CN201580072463.1A CN201580072463A CN107112355B CN 107112355 B CN107112355 B CN 107112355B CN 201580072463 A CN201580072463 A CN 201580072463A CN 107112355 B CN107112355 B CN 107112355B
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C.陈
M.吴
J.杨
C.苏
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Silicon Storage Technology Inc
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Abstract

本发明公开了一种非易失性存储器单元，该非易失性存储器单元包括第一导电类型的衬底，该第一导电类型的衬底具有第二导电类型的第一区域、该述第二导电类型的与该第一区域间隔开的第二区域，在第一区域和第二区域之间形成沟道区域。浮栅被设置在与第一区域相邻的沟道区域的第一部分上方并与其绝缘。选择栅被设置在与第二区域相邻的沟道区域的第二部分上方，该选择栅由金属材料形成并且通过二氧化硅层和高K绝缘材料层而与沟道区域的第二部分绝缘。控制栅被设置在浮栅上方并与其绝缘。擦除栅被设置在第一区域上方并与其绝缘，并且被设置成与所述浮栅横向相邻并与其绝缘。

Description

具有金属栅的分裂栅非易失性闪存存储器单元及其制造方法
技术领域
本发明涉及具有选择栅、浮栅、控制栅和擦除栅的非易失性闪存存储器单元。
背景技术
具有选择栅、浮栅、控制栅和擦除栅的分裂栅非易失性闪存存储器单元在本领域中是熟知的。参见例如美国专利6,747,310和7,868,375。在浮栅上方具有悬垂物的擦除栅在本领域中也是熟知的。参见例如美国专利5,242,848。所有这三个专利全文以引用方式并入本文。
二氧化硅已被用作用于分裂栅非易失性闪存存储器的选择栅(也被称为WL(字线))的栅极电介质。随着闪存存储器单元的尺寸减小，二氧化硅的厚度变得更薄，以增加用于较高电流驱动的栅极电容。然而，在选择栅氧化物减小到低于2nm时，氧化物泄漏电流显著增加。如下所述，利用后栅或替换金属栅(HKMG-高K金属栅)来替换二氧化硅可减轻泄漏，并且同时增强用于单元读取电流的选择栅电流驱动。
因此，本发明的一个目的是随着存储器单元的尺寸继续缩小而改善其性能。
发明内容
本发明公开了一种非易失性存储器单元，该非易失性存储器单元包括：第一导电类型的衬底，该第一导电类型的衬底具有第二导电类型的第一区域、该述第二导电类型的与该第一区域间隔开的第二区域，在第一区域和第二区域之间形成沟道区域；浮栅，该浮栅被设置在与第一区域相邻的沟道区域的第一部分上方并与其绝缘；选择栅，该选择栅被设置在与第二区域相邻的沟道区域的第二部分上方，该选择栅由金属材料形成并且通过二氧化硅层和高K绝缘材料层而与沟道区域的第二部分绝缘；控制栅，该控制栅被设置在浮栅上方并与其绝缘；以及擦除栅，该擦除栅被设置在第一区域上方并与其绝缘，并且被设置成与所述浮栅横向相邻并与其绝缘。
公开了一种形成非易失性存储器单元的方法，该方法包括：在第一导电类型的衬底中形成第二导电类型的间隔开的第一区域和第二区域，在该第一区域和第二区域之间限定沟道区域；形成浮栅，该浮栅被设置在与第一区域相邻的沟道区域的第一部分上方并与其绝缘；形成控制栅，该控制栅被设置在浮栅上方并与其绝缘；形成第一多晶硅块，该第一多晶硅块被设置在与第二区域相邻的沟道区域的第二部分上方并与其绝缘；形成第二多晶硅块，该第二多晶硅块被设置在第一区域上方并与其绝缘，并且被设置成与浮栅横向相邻并与其绝缘；移除第一多晶硅块并且利用金属材料块来替换该第一多晶硅块；以及在金属材料块和沟道区域的第二部分之间形成绝缘层，该绝缘层包括二氧化硅层和高K绝缘材料层。
通过查看说明书、权利要求书和附图，本发明的其他目的和特征将变得显而易见。
附图说明
图1A-图1M是示出形成本发明的存储器单元的步骤的横截面视图。
图2A-图2D是示出形成本发明的存储器单元的替代实施方案的步骤的横截面视图。
图3A-图3B是示出形成本发明的存储器单元的第二替代实施方案的步骤的横截面视图。
具体实施方式
参见图1A-图1M，其示出了用于制造存储器单元的过程中的步骤的横截面视图，在该存储器单元中选择栅和擦除栅由高导电金属材料形成。该过程始于在P型单晶硅的衬底10上形成二氧化硅(氧化物)层12。此后，在二氧化硅层12上形成第一多晶硅(或非晶硅)层14，如图1A所示。随后在垂直于图1A的视图的方向上对第一多晶硅层14进行图案化。
另一个绝缘层16诸如二氧化硅(或甚至复合层，诸如ONO(氧化物、氮化物、氧化物))被形成在第一多晶硅层14上。第二多晶硅层18然后被形成在氧化物层16上。另一个绝缘层20被形成在第二多晶硅层18上并且在随后的干法蚀刻期间用作硬掩模。在优选的实施方案中，层20是包含氮化硅20a、二氧化硅20b和氮化硅20c的复合层。所得的结构被示出于图1B中。硬掩模可为氧化硅20b和氮化硅20c的复合层。硬掩模也可利用厚的氮化硅层20a形成。
在该结构上涂覆光刻胶材料(未示出)，并且执行掩模步骤，从而暴露光刻胶材料的所选择的部分。对光刻胶进行显影并且将该光刻胶用作掩模，从而蚀刻该结构。具体地，复合层20、第二多晶硅层18、绝缘层16被各向异性蚀刻，直到第一多晶硅层14被暴露。所得的结构被示出于图1C中。尽管仅示出了两个“叠堆”：S1和S2，但是应当清楚的是存在彼此分离的多个此类“叠堆”。
二氧化硅22被形成在该结构上。随后是氮化硅层24的形成。氮化硅24被各向异性蚀刻，从而留下在叠堆S1和S2中的每个叠堆旁边的复合间隔物26(其为二氧化硅22和氮化硅24的组合)。间隔物的形成是本领域所熟知的，并且涉及材料在结构轮廓上方的沉积，随后进行各向异性蚀刻过程，由此将该材料从该结构的横向表面移除，同时该材料在该结构的竖直取向表面上在很大程度上保持完整(具有圆化的上表面)。所得的结构被示出于图1D中。
氧化物层被形成在改结构上方，随后进行各向异性蚀刻，从而留下在叠堆S1和S2旁边的氧化物间隔物30。光刻胶28被形成在叠堆S1和S2之间的区域上方以及其他交替的成对叠堆S1和S2之间的区域上方。出于该讨论的目的，该对叠堆S1和S2之间的区域将被称为“内部区域”，并且内部区域之外(即，在相邻对叠堆S1和S2之间)的区域将被称为“外部区域”。外部区域中暴露的间隔物30通过各向同性蚀刻而被移除。所得的结构被示出于图1E中。
在光刻胶28被移除之后，将内部区域和外部区域中的第一多晶硅14的暴露部分各向异性地蚀刻。氧化物层12的一部分也将在多晶硅过度蚀刻期间被蚀刻(移除)。较薄的剩余氧化物层将优选地留在衬底10上，以便防止对衬底10的损坏。所得的结构被示出于图1F中。
氧化物层被形成在结构上方，随后进行各向异性蚀刻，从而留下叠堆S1和S2旁边的氧化物的间隔物31以及衬底34上的氧化物层33。另一个氧化物层被形成在结构上方，从而使间隔物31和层33增厚。然后对光刻胶材料32进行涂覆和遮蔽，从而留下叠堆S1和S2之间的内部区域中的开口。再次，类似于在图1E中示出的图，光刻胶位于其他交替成对的叠堆之间。使所得的结构经受离子注入34(即，注入到衬底10的暴露部分中)。然后通过例如湿法蚀刻来移除邻近叠堆S1和S2的氧化物间隔物31以及内部区域中的氧化物层33。所得的结构被示出于图1G中。
移除叠堆S1和S2的外部区域中的光刻胶材料32。应用高温热退火步骤，以激活离子注入34并且形成源极结(即，第一区域或源极区域34)。二氧化硅36被形成在每个地方。该结构再次被光刻胶材料38覆盖并且执行掩摸步骤，从而暴露叠堆S1和S2的外部区域并留下覆盖叠堆S1和S2之间的内部区域的光刻胶材料38。进行氧化物各向异性蚀刻，然后进行各向同性湿法蚀刻，以从叠堆S1和S2的外部区域移除氧化物36和氧化物33，并且可能减小叠堆S1和S2的外部区域中的氧化物间隔物31的厚度。所得的结构被示出于图1H中。
在移除光刻胶材料38之后，绝缘层40被形成在该结构上方。优选地，绝缘层包括作为界面层(IL)和第二高K材料(即，具有大于氧化物诸如HfO2、ZrO2、TiO2、Ta2O5或其他适当的材料等的介电常数的介电常数K)层的第一薄氧化物层。可改变IL厚度，以实现分裂栅闪存单元的选择栅的不同的阈值电压。随后可进行任选的热处理以增强对栅极电介质的水分控制。可在该结构上沉积封盖层诸如TiN、TaN、TiSiN，以在随后的处理步骤中保护高K材料免受损坏。然后将多晶硅沉积在该结构上方，随后进行CMP蚀刻，从而得到叠堆S1和S2的内部区域中的多晶硅块42，以及叠堆S1和S2的外部区域中的多晶硅块44。所得的结构被示出于图1I中。
可进行N+多晶硅预注入。在这之后进行光刻胶涂覆、掩模曝光和选择性移除，随后进行选择性多晶硅蚀刻，以移除多晶硅块44的一部分(使得剩余的多晶硅块44被适当地确定尺寸，以用于最终的选择栅)。在衬底10的邻近多晶硅块44的暴露部分中执行LDD注入。进行氧化物和氮化物沉积，然后进行氮化物蚀刻，以在多晶硅块44旁边形成氧化物48和氮化物50的绝缘间隔物46。然后进行N+注入和退火，以在衬底10中形成第二(漏极)区域52。所得的结构被示出于图1J中。
执行金属过程，以在衬底10的暴露部分上(沿第二区域52的表面部分)形成硅化物54。硅化物也被形成在多晶硅块42,44的暴露上表面上。在结构上方形成氮化物层56，随后形成层间电介质(ILD)材料58。然后执行CMP蚀刻，以移除多晶硅块42和44上方的氮化物56和ILD 58(这也移除这些多晶硅块上的硅化物)。所得的结构被示出于图1K中。
然后执行多晶硅蚀刻，以移除多晶硅块42和44，从而留下开放的沟槽。将功函数金属栅材料60诸如TiAlN1-x沉积在结构上。可通过改变氧空位或氮浓度来进一步调谐其功函数。通过调谐功函数来调整分裂栅闪存器的选择栅阈值电压。在结构上沉积厚的金属层(例如，铝、Ti、TiAlN、TaSiN等)，随后进行CMP回蚀刻，从而留下用于填充第一区域34上方的沟槽的金属块62以及用于填充邻近第二区域52的沟槽的金属块64。可应用后金属热处理来优化存储器单元的性能。所得的结构被示出于图1L中。应当注意，作为绝缘层40的一部分的高K材料(诸如HfO2、ZrO2、TiO2等)层的形成可正好在层60的形成之前形成，而不是如上文相对于图1L所述那样更早地形成。
绝缘层66(例如，ILD)被形成在结构上方。使用适当的光刻胶涂覆、掩模曝光、选择性光刻胶蚀刻和ILD蚀刻，通过ILD层66形成下至硅化物54并暴露该硅化物的接触开口。使用适当的沉积和CMP蚀刻利用导电材料(例如，钨)来填充接触开口，以形成电触点68。金属接触线70然后被形成在ILD层66上方并且与电触点68接触。所得的结构被示出于图1M中。
如图1M所示，存储器单元成对地形成，其共享公共第一区域34和公共擦除栅62。每个存储器单元包括在第一区域和第二区域34和52之间延伸的沟道区域72，并且具有被设置在浮栅14下方的第一部分以及被设置在选择栅64下方的第二部分。控制栅18被设置在浮栅14上方。通过具有由金属形成的擦除栅62和选择栅64，以及将触点68与第二区域52连接的硅化物54，连同由在选择栅64下方的氧化物和高K膜形成的绝缘层40，由于选择栅下的栅极电介质，因此存储器单元的速度和性能比具有常规多晶硅栅极和常规氧化物的存储器单元有所增强。
图2A-图2D示出了替代实施方案，其中执行上文相对于图1A-图1M所述的相同的处理步骤，除非另有说明。从图1H的结构开始并且相对于上文相对于图1I所述的处理步骤，在移除光刻胶材料38之后并且在绝缘层40被形成在结构上方之后，可在叠堆S1和S2的外部区域上方形成光刻胶76，由此进行蚀刻以移除位于叠堆S1和S2的内部区域中的绝缘层40的高K材料层(但是将绝缘层40的高K材料层维持在将形成选择栅的位置下方)，如图2A所示。
在上文相对于图1I所述的剩余处理完成之后，光刻胶78被形成在多晶硅块44上方，随后进行多晶硅蚀刻，以使多晶硅块42的上表面凹陷，如图2B所示。相对于以上图1K，然后如上所述通过形成硅化物54、氮化物56和ILD 58来处理该结构。然而，由于多晶硅块42是凹陷的，这导致硅化物54保留在多晶硅块42上，并且氮化物56和ILD 58被形成在多晶硅块42上，如图2C所示。然后进行如上所述的剩余处理步骤，从而得到图2D所示的最终结构。由于多晶硅块42被保护以免受用于移除多晶硅块44的多晶硅蚀刻，因此多晶硅块42作为擦除栅而保持完整。此外，通过在其上表面上形成硅化物54来增强其导电性。因此，该实施方案将金属选择栅64与硅化物增强多晶硅擦除栅42组合在一起。这还移除擦除栅42和浮栅14之间的高K膜，以便对其间的隧道氧化物的厚度进行更好的控制。
图3A-图3B示出了第二替代实施方案，其中执行上文相对于图1A-图1M所述的相同的处理步骤，除非另有说明。该实施方案开始于用于形成图2A的结构的相同处理，其中叠堆S1和S2的内部区域中的高K材料层被移除。然后进行上文相对于图1I-图1M所述的剩余的处理步骤，不同的是在进行用于移除多晶硅块42和44的多晶硅蚀刻之前，在多晶硅块42上方形成光刻胶80以防止其移除，如图3A所示。由于多晶硅块42被保护以免受移除多晶硅块44的多晶硅蚀刻，因此多晶硅块42作为擦除栅而完全保持完整。然后进行如上相对于图1K至图1M所述的剩余的处理步骤，从而得到图3B所示的最终结构。该实施方案将金属选择栅64与全尺寸多晶硅擦除栅42组合，并且将擦除栅42和浮栅14之间的高K膜移除，以用于对其间的隧道氧化物的厚度进行更好的控制。
应当理解，本发明并不限于上述的和在本文中示出的实施方案，而是涵盖落在所附权利要求书的范围内的任何和所有变型形式。举例来说，本文中对本发明的提及并不意在限制任何权利要求或权利要求术语的范围，而是仅参考可由这些权利要求中的一项或多项权利要求涵盖的一个或多个特征。上文所述的材料、过程和数值的示例仅为示例性的，而不应视为限制权利要求。另外，根据权利要求和说明书显而易见的是，并非所有方法步骤都需要以所示出或所声称的精确顺序来执行，而是需要以允许本发明的存储器单元的适当形成的任意顺序来执行。最后，单个材料层可被形成作为多个此类或类似材料层，并且反之亦然。
应该指出的是，如本文所用，术语“在…上方”和“在…上”两者包容地包括“在…上直接”(其间未设置中间材料、元件或空间)和“在…上间接”(其间设置有中间材料、元件或空间)。类似地，术语“相邻”包括“直接相邻”(其间未设置中间材料、元件或空间)和“间接相邻”(其间设置有中间材料、元件或空间)，“被安装到”包括“被直接安装到”(其间未设置中间材料、元件或空间)和“被间接安装到”(其间设置有中间材料、元件或空间)，并且“被电连接到”包括“被直接电连接到”(其间没有将元件电连接在一起的中间材料或元件)、和“被间接电连接到”(期间有将元件电连接在一起的中间材料或元件)。例如，“在衬底上方”形成元件可包括在其间没有中间材料/元件的情况下在衬底上直接形成元件，以及在其间有一个或多个中间材料/元件的情况下在衬底上间接形成元件。

Claims (10)

1.一种非易失性存储器单元，包括：
第一导电类型的衬底，所述第一导电类型的衬底具有第二导电类型的第一区域、所述第二导电类型的与所述第一区域间隔开的第二区域，在所述第一区域和所述第二区域之间形成沟道区域；
浮栅，所述浮栅被设置在与所述第一区域相邻的所述沟道区域的第一部分上方并与其绝缘；
选择栅，所述选择栅被设置在与所述第二区域相邻的所述沟道区域的第二部分上方，所述选择栅由金属材料形成并且通过二氧化硅层和高K绝缘材料层而与所述沟道区域的所述第二部分绝缘；
控制栅，所述控制栅被设置在所述浮栅上方并与其绝缘；和
擦除栅，所述擦除栅被设置在所述第一区域上方并与其绝缘，并且被设置成与所述浮栅横向相邻并与其绝缘，其中所述擦除栅由多晶硅材料形成，并且仅通过二氧化硅与所述浮栅绝缘；以及
设置在所述擦除栅的上表面上的硅化物。
2.根据权利要求1所述的存储器单元，其中所述高K绝缘材料是HfO2、ZrO2、和TiO2中的至少一者。
3.根据权利要求1所述的存储器单元，其中所述选择栅的上表面比所述擦除栅的所述上表面更高于所述衬底。
4.根据权利要求1所述的存储器单元，还包括：
硅化物，所述硅化物被设置在所述第二区域中的所述衬底的一部分上。
5.根据权利要求1所述的存储器单元，还包括：
功函数金属层，所述功函数金属层沿所述选择栅的底表面和侧表面延伸。
6.一种形成非易失性存储器单元的方法，包括：
在第一导电类型的衬底中形成第二导电类型的间隔开的第一区域和第二区域，在所述第一区域和所述第二区域之间限定沟道区域；
形成浮栅，所述浮栅被设置在与所述第一区域相邻的所述沟道区域的第一部分上方并与其绝缘；
形成控制栅，所述控制栅被设置在所述浮栅上方并与其绝缘；
在所述第一区域上和在所述浮栅的一部分上形成二氧化硅；
在与所述第二区域相邻的所述沟道区域的第二部分上形成二氧化硅；
在所述第一区域上和在所述浮栅的所述部分上的二氧化硅上、以及在所述沟道区域的所述第二部分上的二氧化硅上形成高K绝缘材料层；
去除在所述第一区域上和在所述浮栅的所述部分上的二氧化硅上的所述高K绝缘材料；
形成第一多晶硅块，所述第一多晶硅块被设置在所述沟道区域的所述第二部分上的二氧化硅上的高K绝缘材料层上，以及形成第二多晶硅块，所述第二多晶硅块被设置在所述第一区域上和在所述浮栅的所述部分上的二氧化硅上，其中所述第二多晶硅块被设置在所述第一区域上方并与之绝缘，在横向上设置成与所述浮栅相邻并与其绝缘，并且仅通过所述二氧化硅与所述浮栅绝缘；
移除所述第一多晶硅块并且利用金属材料块来替换所述第一多晶硅块；以及
在所述第二多晶硅块的上表面上形成硅化物，
其中所述金属材料块是选择栅，并且所述第二多晶硅块是擦除栅。
7.根据权利要求6所述的方法，其中所述高K绝缘材料层是HfO2、ZrO2、和TiO2中的至少一者。
8.根据权利要求6所述的方法，其中所述金属材料块的上表面比所述第二多晶硅块的所述上表面更高于所述衬底。
9.根据权利要求6所述的方法，还包括：
在所述第二区域中的所述衬底的一部分上形成硅化物。
10.根据权利要求6所述的方法，还包括：
形成功函数金属层，所述功函数金属层沿所述金属材料块的底表面和侧表面延伸。
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