US20160197088A1 - Split Gate Non-volatile Flash Memory Cell Having Metal Gates And Method Of Making Same - Google Patents
Split Gate Non-volatile Flash Memory Cell Having Metal Gates And Method Of Making Same Download PDFInfo
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- US20160197088A1 US20160197088A1 US14/589,650 US201514589650A US2016197088A1 US 20160197088 A1 US20160197088 A1 US 20160197088A1 US 201514589650 A US201514589650 A US 201514589650A US 2016197088 A1 US2016197088 A1 US 2016197088A1
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 52
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 19
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- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
Definitions
- the present invention relates to a non-volatile flash memory cell which has a select gate, a floating gate, a control gate, and an erase gate.
- Silicon dioxide has been used as a gate dielectric for select gate, also called WL (word-line), of split gate non-volatile flash memory. As flash memory cells have reduced in size, the thickness of the silicon dioxide has become thinner to increase the gate capacitance for higher current drive. However, as the select gate oxide is reduced to below 2 nm, the oxide leakage current increases significantly. As discussed below, replacing silicon dioxide with gate last, or replacement metal gate (HKMG—High-K Metal Gate) can alleviate the leakage and at the same time enhance the select gate current drive for cell read current.
- HKMG High-K Metal Gate
- a non-volatile memory cell comprises a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type spaced apart from the first region, forming a channel region therebetween, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the first region, a select gate disposed over a second portion of the channel region which is adjacent to the second region, the select gate being formed of a metal material and being insulated from the second portion of the channel region by a layer of silicon dioxide and a layer of high K insulating material, a control gate disposed over and insulated from the floating gate, and an erase gate disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.
- a method of forming a non-volatile memory cell comprises forming, in a substrate of a first conductivity type, spaced apart first and second regions of a second conductivity type, defining a channel region therebetween, forming a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the first region, forming a control gate disposed over and insulated from the floating gate, forming a first block of polysilicon disposed over and insulated from a second portion of the channel region which is adjacent to the second region, forming a second block of polysilicon disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate, removing the first block of polysilicon and replacing the first block of polysilicon with a block of metal material, and forming an insulation layer between the block of metal material and the second portion of the channel region that comprises a layer of silicon dioxide and a layer of high K insulating material.
- FIGS. 1A-1M are cross sectional views illustrating steps in forming the memory cell of the present invention.
- FIGS. 2A-2D are cross sectional views illustrating steps in forming an alternate embodiment of the memory cell of the present invention.
- FIGS. 3A-3B are cross sectional views illustrating steps in forming a second alternate embodiment of the memory cell of the present invention.
- FIGS. 1A-1M there are shown cross-sectional views of the steps in the process to make a memory cell in which the select gate and the erase gate are formed of highly conductive metal material.
- the process begins by forming a layer of silicon dioxide (oxide) 12 on a substrate 10 of P type single crystalline silicon. Thereafter a first layer 14 of polysilicon (or amorphous silicon) is formed on the layer 12 of silicon dioxide, as illustrated in FIG. 1A .
- the first layer 14 of polysilicon is subsequently patterned in a direction perpendicular to the view of FIG. 1A .
- Another insulating layer 16 such as silicon dioxide (or even a composite layer, such as ONO (oxide, nitride, oxide)) is formed on the first layer 14 of polysilicon.
- a second layer 18 of polysilicon is then formed on the oxide layer 16 .
- Another insulating layer 20 is formed on the second layer 18 of polysilicon and used as a hard mask during subsequent dry etching.
- the layer 20 is a composite layer, comprising silicon nitride 20 a , silicon dioxide 20 b , and silicon nitride 20 c .
- the resulting structure is shown in FIG. 1B .
- the hard mask may be a composite layer of silicon oxide 20 b and silicon nitride 20 c .
- the hard mask may also be formed with a thick silicon nitride layer 20 a.
- Photoresist material (not shown) is coated on the structure, and a masking step is performed exposing selected portions of the photoresist material.
- the photoresist is developed and using the photoresist as a mask, the structure is etched.
- the composite layer 20 , the second layer 18 of polysilicon, the insulating layer 16 are anisotropically etched, until the first layer 14 of polysilicon is exposed.
- the resultant structure is shown in FIG. 1C . Although only two “stacks”: S 1 and S 2 are shown, it should be clear that there are a number of such “stacks” that are separated from one another.
- Silicon dioxide 22 is formed on the structure. This is followed by the formation of silicon nitride layer 24 .
- the silicon nitride 24 is anisotropically etched leaving a composite spacer 26 (which is the combination of the silicon dioxide 22 and silicon nitride 24 ) alongside each of the stacks S 1 and S 2 .
- Formation of spacers is well known in the art, and involves the deposition of a material over the contour of a structure, followed by an anisotropic etch process, whereby the material is removed from horizontal surfaces of the structure, while the material remains largely intact on vertically oriented surfaces of the structure (with a rounded upper surface).
- the resultant structure is shown in FIG. 1D .
- a layer of oxide is formed over the structure, followed by an anisotropical etch leaving spacers 30 of the oxide alongside the stacks S 1 and S 2 .
- a photoresist 28 is formed over the regions between the stacks S 1 and S 2 , and other alternating pairs of stacks S 1 and S 2 .
- the region between the pair of stacks S 1 and S 2 will be called the “inner region” and the regions outside of the inner region (i.e. between adjacent pairs of stacks S 1 and S 2 ) will be referred to as the “outer regions”.
- the exposed spacers 30 in the outer regions are removed by isotropic etch.
- the resulting structure is shown in FIG. 1E .
- the exposed portions first polysilicon 14 in the inner and outer regions are anisotropically etched.
- Part of oxide layer 12 will also be etched (removed) during the poly over-etching.
- a thinner layer of remaining oxide will preferably stay on the substrate 10 so as to prevent damage to the substrate 10 .
- the resultant structure is shown in FIG. 1F .
- a layer of oxide is formed over the structure, followed by an anisotropical etch leaving spacers 31 of the oxide alongside the stacks S 1 and S 2 and a layer 33 of oxide on substrate 34 .
- Another oxide layer is formed over the structure, thickening spacers 31 and layer 33 .
- Photoresist material 32 is then coated and masked leaving openings in the inner regions between the stacks S 1 and S 2 . Again, similar to the drawing shown in FIG. 1E , the photoresist is between other alternating pairs of stacks.
- the resultant structure is subject to an ion implant 34 (i.e. into exposed portions of substrate 10 ).
- the oxide spacers 31 adjacent to the stacks S 1 and S 2 and oxide layer 33 in the inner region are then removed by e.g. a wet etch.
- the resultant structure is shown in FIG. 1G .
- the photoresist material 32 in the outer regions of the stacks S 1 and S 2 is removed.
- a high-temperature thermal annealing step is applied to activate the ion implant 34 and to form the source junction (i.e. first or source region 34 ).
- Silicon dioxide 36 is formed everywhere.
- the structure is once again covered by photoresist material 38 and a masking step is performed exposing the outer regions of the stacks S 1 and S 2 and leaving photoresist material 38 covering the inner region between the stacks S 1 and S 2 .
- An oxide anisotropical etch followed by isotropic wet etch are performed, to remove oxide 36 and oxide 33 from the outer regions of stacks S 1 and S 2 , and possibly to reduce the thickness of the oxide spacers 31 in the outer regions of the stacks S 1 and S 2 .
- the resultant structure is shown in FIG. 1H .
- the insulation layer includes a first layer of thin oxide as the interfacial layer (IL) and a second layer of a high K material (i.e. having a dielectric constant K greater than that of oxide, such as HfO 2 , ZrO 2 , TiO 2 , Ta 2 O 5 , or other adequate materials, etc.).
- the IL thickness may be varied to achieve different threshold voltage for the select gate of the split-gate flash cell.
- An optional thermal treatment may follow to enhance moisture control on the gate dielectric.
- a capping layer such as TiN, TaN, TiSiN, may be deposited on the structure to protect the high K material from damaging in the subsequent processing steps.
- Polysilicon is then deposited over the structure, followed by a CMP etch, resulting in a block 42 of polysilicon in the inner region of the stacks S 1 and S 2 , and blocks 44 of polysilicon in the outer regions of the stacks S 1 and S 2 .
- the resultant structure is shown in FIG. 1I .
- An N+ poly pre-implant may be performed. This is followed by a photoresist coating, mask exposure and selective removal, followed by selective poly etch, to remove a portion of poly blocks 44 (so that the remaining poly blocks 44 are properly sized for the eventual select gates).
- An LDD implant is performed in the exposed portions of substrate 10 adjacent poly blocks 44 .
- Oxide and nitride depositions, followed by nitride etch, are performed to form insulation spacers 46 of oxide 48 and nitride 50 alongside poly blocks 44 .
- An N+ implant and anneal is then performed to form second (drain) regions 52 in substrate 10 .
- the resultant structure is shown in FIG. 1J .
- a metallization process is performed to form silicide 54 on the exposed portions substrate 10 (along surface portion of second regions 52 ). Silicide is also formed on the exposed upper surfaces of poly blocks 42 , 44 .
- a layer 56 of nitride is formed over the structure, followed by an inter-layer dielectric (ILD) material 58 .
- a CMP etch is then performed to remove nitride 56 and ILD 58 above poly blocks 42 and 44 (which also removes the silicide on those poly blocks).
- the resultant structure is shown in FIG. 1K .
- a poly etch is then performed to remove poly blocks 42 and 44 , leaving open trenches behind.
- Work function metal gate material 60 such as TiAlN 1-x , is deposited on the structure. Its work function can be further tuned by changing oxygen vacancies or nitrogen concentration. The select gate threshold voltage of the split-gate flash is adjusted through the tuning of the work function.
- a thick layer of metal e.g. aluminum, Ti, TiAlN, TaSiN, etc.
- metal block 62 filling the trench over first region 34 and metal blocks 64 filling trenches adjacent second regions 52 .
- a post-metal thermal treatment may be applied to optimize the performance of the memory cell.
- the resultant structure is shown in FIG. 1L .
- the formation of the layer of high K material such as HfO 2 , ZrO 2 , TiO 2 , etc. as part of insulation layer 40 could be formed just before the formation of layer 60 instead of earlier as described above with respect to FIG. 1L .
- An insulation layer 66 (e.g. ILD) is formed over the structure. Contact openings are formed through the ILD layer 66 down to and exposing the silicide 54 using an appropriate photo resist coating, mask exposure, selective photo resist etch and ILD etch. The contact openings are filled with conductive material (e.g. tungsten) using an appropriate deposition and CMP etch to form electrical contacts 68 . Metal contact lines 70 are then formed over ILD layer 66 and in contact with the electrical contacts 68 . The resultant structure is shown in FIG. 1M .
- the memory cells are formed in pairs that share a common first region 34 and common erase gate 62 .
- Each memory cell includes a channel region 72 extending between the first and second regions 34 and 52 , and have a first portion disposed under the floating gate 14 and a second portion disposed under the select gate 64 .
- the control gate 18 is disposed over the floating gate 14 .
- FIGS. 2A-2D illustrate an alternate embodiment where the same processing steps described above with respect to FIGS. 1A-1M are performed except where noted.
- photo resist 76 can be formed over the outer regions of stacks S 1 and S 2 , whereby an etch is performed to remove the layer of high K material of insulation layer 40 in the inner region of stacks S 1 and S 2 , (but maintains the layer of high K material of insulation layer 40 underneath where the select gates will be formed), as illustrated in FIG. 2A .
- photo resist 78 is formed over poly blocks 44 , followed by a poly etch to recess the upper surface of poly blocks 42 , as illustrated in FIG. 2B .
- the structure is then processed as discussed above through the formation of silicide 54 , nitride 56 and ILD 58 with respect to FIG. 1K above.
- poly block 42 is recessed, that results in silicide 54 remaining on poly block 42 , and nitride 56 and ILD 58 being formed on poly block 42 , as illustrated in FIG. 2C .
- the remaining processing steps as discussed above are performed, resulting in the final structure shown in FIG. 2D .
- poly block 42 is protected from the poly etch that removes poly blocks 44 , poly block 42 remains intact as the erase gate. Moreover, its conductivity is enhanced by the formation of silicide 54 on its upper surface. Therefore, this embodiment combines a metal select gate 64 with a silicide enhanced polysilicon erase gate 42 . It also removes the high K film between the erase gate 42 and floating gate 14 for better control over the thickness of the tunnel oxide therebetween.
- FIGS. 3A-3B illustrate a second alternate embodiment where the same processing steps described above with respect to FIGS. 1A-1M are performed except where noted.
- This embodiment starts with the same processing for forming the structure of FIG. 2A , where the layer of high K material in the inner region of stacks S 1 and S 2 is removed.
- the remaining processing steps described above with respect to FIGS. 1I-1M are then performed, except that before the poly etch used to remove poly blocks 42 and 44 , photoresist 80 is formed over poly block 42 to prevent its removal, as shown in FIG. 3A . Because poly block 42 is protected from the poly etch that removes poly blocks 44 , poly block 42 remains fully intact as the erase gate. Then, the remaining processing steps as discussed above with respect to FIGS.
- This embodiment combines a metal select gate 64 with a full sized polysilicon erase gate 42 , and the high K film between the erase gate 42 and floating gate 14 is removed for better control over the thickness of the tunnel oxide therebetween.
- the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together).
- forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements therebetween.
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Abstract
Description
- The present invention relates to a non-volatile flash memory cell which has a select gate, a floating gate, a control gate, and an erase gate.
- Split gate non-volatile flash memory cells having a select gate, a floating gate, a control gate and an erase gate are well known in the art. See for example U.S. Pat. Nos. 6,747,310 and 7,868,375. An erase gate having an overhang over the floating gate is also well known in the art. See for example, U.S. Pat. No. 5,242,848. All three of these patents are incorporated herein by reference in their entirety.
- Silicon dioxide has been used as a gate dielectric for select gate, also called WL (word-line), of split gate non-volatile flash memory. As flash memory cells have reduced in size, the thickness of the silicon dioxide has become thinner to increase the gate capacitance for higher current drive. However, as the select gate oxide is reduced to below 2 nm, the oxide leakage current increases significantly. As discussed below, replacing silicon dioxide with gate last, or replacement metal gate (HKMG—High-K Metal Gate) can alleviate the leakage and at the same time enhance the select gate current drive for cell read current.
- Accordingly, it is one of the objectives of the present invention to improve the performance of memory cells as they continue to shrink in size.
- A non-volatile memory cell comprises a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type spaced apart from the first region, forming a channel region therebetween, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the first region, a select gate disposed over a second portion of the channel region which is adjacent to the second region, the select gate being formed of a metal material and being insulated from the second portion of the channel region by a layer of silicon dioxide and a layer of high K insulating material, a control gate disposed over and insulated from the floating gate, and an erase gate disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.
- A method of forming a non-volatile memory cell comprises forming, in a substrate of a first conductivity type, spaced apart first and second regions of a second conductivity type, defining a channel region therebetween, forming a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the first region, forming a control gate disposed over and insulated from the floating gate, forming a first block of polysilicon disposed over and insulated from a second portion of the channel region which is adjacent to the second region, forming a second block of polysilicon disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate, removing the first block of polysilicon and replacing the first block of polysilicon with a block of metal material, and forming an insulation layer between the block of metal material and the second portion of the channel region that comprises a layer of silicon dioxide and a layer of high K insulating material.
- Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.
-
FIGS. 1A-1M are cross sectional views illustrating steps in forming the memory cell of the present invention. -
FIGS. 2A-2D are cross sectional views illustrating steps in forming an alternate embodiment of the memory cell of the present invention. -
FIGS. 3A-3B are cross sectional views illustrating steps in forming a second alternate embodiment of the memory cell of the present invention. - Referring to
FIGS. 1A-1M there are shown cross-sectional views of the steps in the process to make a memory cell in which the select gate and the erase gate are formed of highly conductive metal material. The process begins by forming a layer of silicon dioxide (oxide) 12 on asubstrate 10 of P type single crystalline silicon. Thereafter afirst layer 14 of polysilicon (or amorphous silicon) is formed on thelayer 12 of silicon dioxide, as illustrated inFIG. 1A . Thefirst layer 14 of polysilicon is subsequently patterned in a direction perpendicular to the view ofFIG. 1A . - Another
insulating layer 16, such as silicon dioxide (or even a composite layer, such as ONO (oxide, nitride, oxide)) is formed on thefirst layer 14 of polysilicon. Asecond layer 18 of polysilicon is then formed on theoxide layer 16. Another insulatinglayer 20 is formed on thesecond layer 18 of polysilicon and used as a hard mask during subsequent dry etching. In the preferred embodiment, thelayer 20 is a composite layer, comprisingsilicon nitride 20 a,silicon dioxide 20 b, andsilicon nitride 20 c. The resulting structure is shown inFIG. 1B . The hard mask may be a composite layer ofsilicon oxide 20 b andsilicon nitride 20 c. The hard mask may also be formed with a thicksilicon nitride layer 20 a. - Photoresist material (not shown) is coated on the structure, and a masking step is performed exposing selected portions of the photoresist material. The photoresist is developed and using the photoresist as a mask, the structure is etched. Specifically, the
composite layer 20, thesecond layer 18 of polysilicon, theinsulating layer 16 are anisotropically etched, until thefirst layer 14 of polysilicon is exposed. The resultant structure is shown inFIG. 1C . Although only two “stacks”: S1 and S2 are shown, it should be clear that there are a number of such “stacks” that are separated from one another. -
Silicon dioxide 22 is formed on the structure. This is followed by the formation ofsilicon nitride layer 24. Thesilicon nitride 24 is anisotropically etched leaving a composite spacer 26 (which is the combination of thesilicon dioxide 22 and silicon nitride 24) alongside each of the stacks S1 and S2. Formation of spacers is well known in the art, and involves the deposition of a material over the contour of a structure, followed by an anisotropic etch process, whereby the material is removed from horizontal surfaces of the structure, while the material remains largely intact on vertically oriented surfaces of the structure (with a rounded upper surface). The resultant structure is shown inFIG. 1D . - A layer of oxide is formed over the structure, followed by an anisotropical
etch leaving spacers 30 of the oxide alongside the stacks S1 and S2. Aphotoresist 28 is formed over the regions between the stacks S1 and S2, and other alternating pairs of stacks S1 and S2. For the purpose of this discussion, the region between the pair of stacks S1 and S2 will be called the “inner region” and the regions outside of the inner region (i.e. between adjacent pairs of stacks S1 and S2) will be referred to as the “outer regions”. The exposedspacers 30 in the outer regions are removed by isotropic etch. The resulting structure is shown inFIG. 1E . - After the
photoresist 28 is removed, the exposed portionsfirst polysilicon 14 in the inner and outer regions are anisotropically etched. Part ofoxide layer 12 will also be etched (removed) during the poly over-etching. A thinner layer of remaining oxide will preferably stay on thesubstrate 10 so as to prevent damage to thesubstrate 10. The resultant structure is shown inFIG. 1F . - A layer of oxide is formed over the structure, followed by an anisotropical
etch leaving spacers 31 of the oxide alongside the stacks S1 and S2 and alayer 33 of oxide onsubstrate 34. Another oxide layer is formed over the structure, thickeningspacers 31 andlayer 33.Photoresist material 32 is then coated and masked leaving openings in the inner regions between the stacks S1 and S2. Again, similar to the drawing shown inFIG. 1E , the photoresist is between other alternating pairs of stacks. The resultant structure is subject to an ion implant 34 (i.e. into exposed portions of substrate 10). Theoxide spacers 31 adjacent to the stacks S1 and S2 andoxide layer 33 in the inner region are then removed by e.g. a wet etch. The resultant structure is shown inFIG. 1G . - The
photoresist material 32 in the outer regions of the stacks S1 and S2 is removed. A high-temperature thermal annealing step is applied to activate theion implant 34 and to form the source junction (i.e. first or source region 34).Silicon dioxide 36 is formed everywhere. The structure is once again covered by photoresist material 38 and a masking step is performed exposing the outer regions of the stacks S1 and S2 and leaving photoresist material 38 covering the inner region between the stacks S1 and S2. An oxide anisotropical etch followed by isotropic wet etch are performed, to removeoxide 36 andoxide 33 from the outer regions of stacks S1 and S2, and possibly to reduce the thickness of theoxide spacers 31 in the outer regions of the stacks S1 and S2. The resultant structure is shown inFIG. 1H . - After photoresist material 38 is removed, an
insulation layer 40 is formed over the structure. Preferably, the insulation layer includes a first layer of thin oxide as the interfacial layer (IL) and a second layer of a high K material (i.e. having a dielectric constant K greater than that of oxide, such as HfO2, ZrO2, TiO2, Ta2O5, or other adequate materials, etc.). The IL thickness may be varied to achieve different threshold voltage for the select gate of the split-gate flash cell. An optional thermal treatment may follow to enhance moisture control on the gate dielectric. A capping layer, such as TiN, TaN, TiSiN, may be deposited on the structure to protect the high K material from damaging in the subsequent processing steps. Polysilicon is then deposited over the structure, followed by a CMP etch, resulting in ablock 42 of polysilicon in the inner region of the stacks S1 and S2, and blocks 44 of polysilicon in the outer regions of the stacks S1 and S2. The resultant structure is shown inFIG. 1I . - An N+ poly pre-implant may be performed. This is followed by a photoresist coating, mask exposure and selective removal, followed by selective poly etch, to remove a portion of poly blocks 44 (so that the remaining poly blocks 44 are properly sized for the eventual select gates). An LDD implant is performed in the exposed portions of
substrate 10 adjacent poly blocks 44. Oxide and nitride depositions, followed by nitride etch, are performed to forminsulation spacers 46 ofoxide 48 andnitride 50 alongside poly blocks 44. An N+ implant and anneal is then performed to form second (drain)regions 52 insubstrate 10. The resultant structure is shown inFIG. 1J . - A metallization process is performed to form
silicide 54 on the exposed portions substrate 10 (along surface portion of second regions 52). Silicide is also formed on the exposed upper surfaces of poly blocks 42, 44. Alayer 56 of nitride is formed over the structure, followed by an inter-layer dielectric (ILD)material 58. A CMP etch is then performed to removenitride 56 andILD 58 above poly blocks 42 and 44 (which also removes the silicide on those poly blocks). The resultant structure is shown inFIG. 1K . - A poly etch is then performed to remove
poly blocks metal gate material 60, such as TiAlN1-x, is deposited on the structure. Its work function can be further tuned by changing oxygen vacancies or nitrogen concentration. The select gate threshold voltage of the split-gate flash is adjusted through the tuning of the work function. A thick layer of metal (e.g. aluminum, Ti, TiAlN, TaSiN, etc.) is deposited on the structure, followed by a CMP etch back, leavingmetal block 62 filling the trench overfirst region 34 andmetal blocks 64 filling trenches adjacentsecond regions 52. A post-metal thermal treatment may be applied to optimize the performance of the memory cell. The resultant structure is shown inFIG. 1L . It should be noted that the formation of the layer of high K material such as HfO2, ZrO2, TiO2, etc. as part ofinsulation layer 40 could be formed just before the formation oflayer 60 instead of earlier as described above with respect toFIG. 1L . - An insulation layer 66 (e.g. ILD) is formed over the structure. Contact openings are formed through the
ILD layer 66 down to and exposing thesilicide 54 using an appropriate photo resist coating, mask exposure, selective photo resist etch and ILD etch. The contact openings are filled with conductive material (e.g. tungsten) using an appropriate deposition and CMP etch to formelectrical contacts 68.Metal contact lines 70 are then formed overILD layer 66 and in contact with theelectrical contacts 68. The resultant structure is shown inFIG. 1M . - As shown in
FIG. 1M , the memory cells are formed in pairs that share a commonfirst region 34 and common erasegate 62. Each memory cell includes achannel region 72 extending between the first andsecond regions gate 14 and a second portion disposed under theselect gate 64. Thecontrol gate 18 is disposed over the floatinggate 14. By having erasegates 62 andselect gates 64 being formed of metal, andsilicide 54 connectingcontacts 68 withsecond regions 52, along withinsulation layer 40 formed of oxide and a high K film underneath theselect gates 64, the speed and performance of the memory cell is enhanced over memory cells with conventional polysilicon gates and conventional oxide as the gate dielectric under the select gates. -
FIGS. 2A-2D illustrate an alternate embodiment where the same processing steps described above with respect toFIGS. 1A-1M are performed except where noted. Starting with the structure ofFIG. 1H , and with respect to the process steps discussed above with respect toFIG. 1I , after the photoresist material 38 is removed, and after theinsulation layer 40 is formed over the structure, photo resist 76 can be formed over the outer regions of stacks S1 and S2, whereby an etch is performed to remove the layer of high K material ofinsulation layer 40 in the inner region of stacks S1 and S2, (but maintains the layer of high K material ofinsulation layer 40 underneath where the select gates will be formed), as illustrated inFIG. 2A . - After the remaining processing discussed above with respect to
FIG. 1I is completed, photo resist 78 is formed over poly blocks 44, followed by a poly etch to recess the upper surface of poly blocks 42, as illustrated inFIG. 2B . The structure is then processed as discussed above through the formation ofsilicide 54,nitride 56 andILD 58 with respect toFIG. 1K above. However, sincepoly block 42 is recessed, that results insilicide 54 remaining onpoly block 42, andnitride 56 andILD 58 being formed onpoly block 42, as illustrated inFIG. 2C . Then the remaining processing steps as discussed above are performed, resulting in the final structure shown inFIG. 2D . Becausepoly block 42 is protected from the poly etch that removes poly blocks 44,poly block 42 remains intact as the erase gate. Moreover, its conductivity is enhanced by the formation ofsilicide 54 on its upper surface. Therefore, this embodiment combines a metalselect gate 64 with a silicide enhanced polysilicon erasegate 42. It also removes the high K film between the erasegate 42 and floatinggate 14 for better control over the thickness of the tunnel oxide therebetween. -
FIGS. 3A-3B illustrate a second alternate embodiment where the same processing steps described above with respect toFIGS. 1A-1M are performed except where noted. This embodiment starts with the same processing for forming the structure ofFIG. 2A , where the layer of high K material in the inner region of stacks S1 and S2 is removed. The remaining processing steps described above with respect toFIGS. 1I-1M are then performed, except that before the poly etch used to removepoly blocks photoresist 80 is formed overpoly block 42 to prevent its removal, as shown inFIG. 3A . Becausepoly block 42 is protected from the poly etch that removes poly blocks 44,poly block 42 remains fully intact as the erase gate. Then, the remaining processing steps as discussed above with respect toFIGS. 1K to 1M are performed, resulting in the final structure shown inFIG. 3B . This embodiment combines a metalselect gate 64 with a full sized polysilicon erasegate 42, and the high K film between the erasegate 42 and floatinggate 14 is removed for better control over the thickness of the tunnel oxide therebetween. - It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of the appended claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed, but rather in any order that allows the proper formation of the memory cell of the present invention. Lastly, single layers of material could be formed as multiple layers of such or similar materials, and vice versa.
- It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements therebetween.
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EP15819943.0A EP3243220A1 (en) | 2015-01-05 | 2015-12-08 | Split gate non-volatile flash memory cell having metal gates and method of making same |
PCT/US2015/064534 WO2016111796A1 (en) | 2015-01-05 | 2015-12-08 | Split gate non-volatile flash memory cell having metal gates and method of making same |
KR1020177021605A KR102003624B1 (en) | 2015-01-05 | 2015-12-08 | Detachable gate non-volatile flash memory cell with metal gates and method of fabricating same |
CN201580072463.1A CN107112355B (en) | 2015-01-05 | 2015-12-08 | Split gate non-volatile flash memory cell with metal gate and method of making same |
JP2017535785A JP6611809B2 (en) | 2015-01-05 | 2015-12-08 | Split gate nonvolatile flash memory cell having metal gate and method of manufacturing the same |
TW104142469A TWI569306B (en) | 2015-01-05 | 2015-12-17 | Split gate non-volatile flash memory cell having metal gates and method of making same |
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2015
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- 2015-12-08 WO PCT/US2015/064534 patent/WO2016111796A1/en active Application Filing
- 2015-12-08 KR KR1020177021605A patent/KR102003624B1/en active IP Right Grant
- 2015-12-08 CN CN201580072463.1A patent/CN107112355B/en active Active
- 2015-12-08 EP EP15819943.0A patent/EP3243220A1/en not_active Withdrawn
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Cited By (15)
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US11652162B2 (en) * | 2016-04-20 | 2023-05-16 | Silicon Storage Technology, Inc. | Method of forming a three-gate non-volatile flash memory cell using two polysilicon deposition steps |
KR102112114B1 (en) * | 2016-11-29 | 2020-05-19 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor device and manufacturing method thereof |
US10943996B2 (en) * | 2016-11-29 | 2021-03-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing semiconductor device including non-volatile memories and logic devices |
US20190097028A1 (en) * | 2016-11-29 | 2019-03-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10325918B2 (en) | 2016-11-29 | 2019-06-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US20190229124A1 (en) * | 2016-11-29 | 2019-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
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US10879253B2 (en) | 2016-11-29 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
CN108172580A (en) * | 2016-11-29 | 2018-06-15 | 台湾积体电路制造股份有限公司 | Semiconductor devices and its manufacturing method |
US10950611B2 (en) | 2016-11-29 | 2021-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US10950715B2 (en) * | 2016-11-29 | 2021-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing semiconductor device including non-volatile memories and logic devices |
US11594620B2 (en) | 2016-11-29 | 2023-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
DE102017116221B4 (en) | 2016-11-29 | 2023-04-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | A method of manufacturing a semiconductor device having a non-volatile memory arranged in a memory cell area and a field effect transistor arranged in a logic circuit area, and a semiconductor device having a non-volatile memory |
KR20180060946A (en) * | 2016-11-29 | 2018-06-07 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor device and manufacturing method thereof |
US11825651B2 (en) | 2016-11-29 | 2023-11-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
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US9379121B1 (en) | 2016-06-28 |
CN107112355B (en) | 2020-08-07 |
TWI569306B (en) | 2017-02-01 |
WO2016111796A1 (en) | 2016-07-14 |
JP6611809B2 (en) | 2019-11-27 |
JP2018501661A (en) | 2018-01-18 |
KR102003624B1 (en) | 2019-07-24 |
TW201635336A (en) | 2016-10-01 |
EP3243220A1 (en) | 2017-11-15 |
KR20170101303A (en) | 2017-09-05 |
CN107112355A (en) | 2017-08-29 |
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