CN107094349A - Printed circuit board and preparation method thereof - Google Patents

Printed circuit board and preparation method thereof Download PDF

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Publication number
CN107094349A
CN107094349A CN201710470840.8A CN201710470840A CN107094349A CN 107094349 A CN107094349 A CN 107094349A CN 201710470840 A CN201710470840 A CN 201710470840A CN 107094349 A CN107094349 A CN 107094349A
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China
Prior art keywords
impedance
circuit board
printed circuit
layer
parameter
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CN201710470840.8A
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CN107094349B (en
Inventor
程柳军
陈蓓
李艳国
王红飞
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Shenzhen Fastprint Circuit Tech Co Ltd
Guangzhou Fastprint Circuit Technology Co Ltd
Yixing Silicon Valley Electronic Technology Co Ltd
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Shenzhen Fastprint Circuit Tech Co Ltd
Yixing Silicon Valley Electronic Technology Co Ltd
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Application filed by Shenzhen Fastprint Circuit Tech Co Ltd, Yixing Silicon Valley Electronic Technology Co Ltd filed Critical Shenzhen Fastprint Circuit Tech Co Ltd
Priority to CN201710470840.8A priority Critical patent/CN107094349B/en
Publication of CN107094349A publication Critical patent/CN107094349A/en
Priority to PCT/CN2017/120093 priority patent/WO2018233271A1/en
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/025Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/025Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0253Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07Electric details
    • H05K2201/0776Resistance and impedance
    • H05K2201/0784Uniform resistance, i.e. equalizing the resistance of a number of conductors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention discloses a kind of printed circuit board and preparation method thereof, the preparation method of the printed circuit board comprises the following steps:Stepped construction is designed, impedance design, and sawing sheet and optimization impedance design, make internal layer circuit and post processing forms the printed circuit board of Multilayer Structure.Described printed circuit board and preparation method thereof, by the way that the factor of influence impedance value is monitored and adjusted in sawing sheet and the production process of making internal layer circuit, can solve printed circuit board because in production process each factor cause the unmanageable problem of interior layer impedance, stably the interior layer impedance of control printed circuit board meets high-precision requirement, improve the high speed transmission of signals performance of printed circuit board, and then the impedance qualification rate of printed circuit board can be improved, reduce impedance scrappage, production cost is reduced, is reduced because handing over phase tardy problem caused by the bad problem of impedance.

Description

Printed circuit board and preparation method thereof
Technical field
The present invention relates to printed circuit board technology field, more particularly to a kind of printed circuit board and preparation method thereof.
Background technology
As PCB (Printed Circuit Board, printed circuit board) tends to high speed and high frequency direction is developed, For PCB impedance control precision more and more higher.The impedance control precision of PCB product is generally ± 10%, also has part high-end Product requirement impedance control can reach higher precision, and such as impedance control precision reaches ± 7% or ± 5%, and such product quantity It is more and more.
Traditional, when carrying out impedance design to PCB, it will usually impedance is simulated using some impedance computation softwares Prediction, then the requirement such as a set of suitable control program of the selection such as laminated construction, line width, thickness of dielectric layers according to client, is produced When product make just according to design when control program carry out making and allow the impedance that the impedance of product meets the requirements of the customers.But, by It is more in the factor of influence PCB impedances, and PCB Making programmes are relatively complicated, the product obtained using conventional method is especially had There is the product of high-precision impedance control demand, its impedance qualification rate is poor, and then cause product rejection rate height, cost of manufacture high, There is friendship phase tardy problem in product.
The content of the invention
Based on this, it is necessary to provide a kind of printed circuit board and preparation method thereof, the printed circuit board and preparation method thereof The impedance qualification rate of product can be improved, production cost is reduced, reduced because handing over phase tardy problem caused by the bad problem of impedance.
Its technical scheme is as follows:
A kind of preparation method of printed circuit board, comprises the following steps:
S1, stepped construction design:Laminated construction design is carried out according to the design requirement of printed circuit board, printed circuit is obtained The initial medium thickness degree and initial dielectric constant of each dielectric layer of plate, obtain the thick value of initial copper of each layer of printed circuit board, Wherein, the initial medium thickness degree of layer where the impedance line of printed circuit board is H0, initial dielectric constant be Er0, initial copper thickness value For T0, it is H as the initial medium thickness degree of the screen layer of the impedance line0', initial dielectric constant be Er0′;
S2, impedance design:Required according to the impedance control of printed circuit board, carrying out impedance using impedance design software sets Meter, obtains the initial impedance design parameter of the impedance line of printed circuit board;
S3, sawing sheet and optimization impedance design:Core plate and prepreg are carried out by sawing sheet according to PCB layouts size, choosing should The core plate and prepreg of same batch after sawing sheet are tested, the actual core thickness H of layer where obtaining impedance line1And reality Core plate dielectric constant Er1, obtain the actual prepreg thickness H of the screen layer as the impedance line2With actual prepreg dielectric Constant Er2, respectively by H1、H2、Er1、Er2With corresponding H0、H0′、Er0、Er0' contrasted, if H1、H2With H0、H0' difference In preset thickness control tolerance, Er1、Er2With Er0、Er0' difference default dielectric constant control tolerance in, then still select The initial impedance design parameter obtained in step S2 is used as new impedance design parameter;If H1、H2With H0、H0' difference default Beyond thickness control tolerance, Er1、Er2With Er0、Er0' difference default dielectric constant control tolerance beyond, then by H1、H2、 Er1、Er2Bring impedance design software into and optimize the first impedance design parameter after impedance design, and output adjustment as new Impedance design parameter;
S4, making internal layer circuit:Internal layer circuit making is carried out to the core plate of layer where the impedance line after step S3, Test obtains the thick value T of actual copper of the core plate of impedance line place layer after development, before etching, by (T-T ') and T0Contrasted, if (T-T ') and T0Difference default copper thickness control tolerance in, then the new impedance design parameter conduct obtained in optional step S3 Newest impedance design parameter;If (T-T ') and T0Difference default copper thickness control tolerance beyond, then bring T into impedance designs Software optimizes the second impedance design parameter after impedance design, and output adjustment as newest impedance design parameter, its In, T ' expression brown influence values;
Make FA plates to be etched, the practical impedance design parameter of the FA plates is tested after etching, and practical impedance is designed Parameter is contrasted with newest impedance design parameter, if both differences can be carried out in default impedance parameter control tolerance Follow-up batch production;If both differences adjust the manufacturing parameter of etching, made again beyond default impedance parameter control tolerance Make FA plates and test etching after impedance design parameter, until difference default impedance parameter control tolerance in, then with adjustment after The manufacturing parameter of etching produced in batches;
S5, post processing form the printed circuit board of Multilayer Structure.
In one of the embodiments, before step S1, the preparation method of the printed circuit board also includes step:
S0, file optimization design:After the completion of PCB routing, in the spacious area of the graphic designs of printed circuit board And/or isolated line region laying balance copper point.
In one of the embodiments, in the step S1:At the beginning of the core plate of layer where the impedance line of printed circuit board 100 μm of beginning thickness of dielectric layers >, and/or, it is used as the initial medium thickness degree > 100 of the prepreg of the screen layer of the impedance line μm。
In one of the embodiments, in the step S1:The initial copper of layer is thick where the impedance line of printed circuit board It is worth for 8 μm, 12 μm or 18 μm, is 8 μm, 12 μm or 18 μm as the initial copper thickness value of the screen layer of the impedance line.
In one of the embodiments, in the step S1:Each dielectric layer of printed circuit board is low-k Elastomeric material.
In one of the embodiments, the step S5 specifically includes following steps:
S51, brown, pressing:The core plate of layer where impedance line is subjected to brown processing and obtains brown layer, and using after sawing sheet The prepreg of same batch overlapped so that prepreg is located between core plate, forms laminated plate, passes through heat pressing process pair Superimposed sheet carries out pressing and forms multi-layer sheet;
S52, drilling, plating, outer-layer circuit etching, welding resistance:Multi-layer sheet is drilled, electroplated, outer-layer circuit etching with And welding resistance makes, the printed circuit board of complete Multilayer Structure is formed.
In one of the embodiments, in the step S51:When carrying out heat pressing process, the pressing program of material is adjusted, The consumption of padded coaming when adjusting lamination so that the heating rate of material lowers 0.2 DEG C/min~0.5 DEG C/min.
In one of the embodiments, in the step S4, the manufacturing parameter of the etching after with adjustment carries out batch After production stage, in addition to step:Carry out taking a sample test inspection in batch production process, the impedance line of product after test etching Whether impedance design parameter is hindered in default impedance parameter control tolerance, if proceeding batch production;If not existing, root The manufacturing parameter of etching is adjusted according to test result.
In one of the embodiments, after step s 5, the preparation method of the printed circuit board also includes following step Suddenly:
S6, testing impedance:The impedance value for the printed circuit board tested using TDR equipment after batch production, and according to impedance Tolerance is controlled to judge whether the interior layer impedance of printed circuit board is qualified.
A kind of printed circuit board, is made using the preparation method of printed circuit board as described above and obtained.
The beneficial effects of the present invention are:
The preparation method of the printed circuit board, carries out stepped construction design successively according to customer demand first and impedance is set Meter, obtains each initial parameter of each dielectric layer of printed circuit board, and then obtain in printed circuit board by impedance design software Impedance line initial impedance design parameter, then after sawing sheet according to the material actual parameter after actual sawing sheet to initial impedance Design parameter is adjusted amendment, and is influenceed during making internal layer circuit according to actual production factor to new resistance Anti- design parameter is adjusted amendment, and the manufacturing parameter to etching is adjusted, and obtains the printed circuit board of Multilayer Structure.Institute The preparation method for stating printed circuit board, by entering in sawing sheet and the production process of making internal layer circuit to the factor of influence impedance value Row monitoring and adjust, it is possible to resolve printed circuit board because in production process each factor cause the unmanageable problem of interior layer impedance, surely Surely control the interior layer impedance of printed circuit board to meet high-precision requirement, improve the high speed transmission of signals of printed circuit board Can, and then the impedance qualification rate of printed circuit board can be improved, impedance scrappage is reduced, production cost is reduced, reduced because of impedance Phase tardy problem is handed over caused by bad problem.
The printed circuit board, is made using the preparation method of above-mentioned printed circuit board and obtained, the impedance of product is qualified Rate is high, production cost is low, is less prone to the bad problem of impedance.
Brief description of the drawings
Fig. 1 is the flowage structure schematic diagram one of the preparation method of the printed circuit board described in the embodiment of the present invention;
Fig. 2 is the flowage structure schematic diagram two of the preparation method of the printed circuit board described in the embodiment of the present invention;
Fig. 3 is the exemplary construction schematic diagram of the printed circuit board described in the embodiment of the present invention.
Description of reference numerals:
100th, prepreg, 200, core plate, 300, single-ended impedance line, 400, differential impedance line.
Embodiment
For the ease of understanding the present invention, the present invention is described more fully below with reference to relevant drawings.In accompanying drawing Give the better embodiment of the present invention.But, the present invention can be realized in many different forms, however it is not limited to herein Described embodiment.On the contrary, the purpose for providing these embodiments is to make to understand more the disclosure Plus it is thorough comprehensive.
It should be noted that when element is referred to as " being fixed on " another element, it can be directly on another element Or can also have element placed in the middle.When an element is considered as " connection " another element, it can be directly connected to To another element or it may be simultaneously present centering elements.On the contrary, when element be referred to as " directly existing " another element " on " when, In the absence of intermediary element.Term as used herein " vertically ", " level ", "left", "right" and similar statement are For illustrative purposes, it is unique embodiment to be not offered as.
Unless otherwise defined, all of technologies and scientific terms used here by the article is with belonging to technical field of the invention The implication that technical staff is generally understood that is identical.Term used in the description of the invention herein is intended merely to description tool The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term as used herein " and/or " including one or more The arbitrary and all combination of related Listed Items.Term as used herein " first ", " second " etc. are used herein In distinguishing object, but these objects should not be limited by these terms.
As shown in figure 1, a kind of preparation method of printed circuit board, comprises the following steps:
S1, stepped construction design:Laminated construction design is carried out according to the design requirement of printed circuit board, printed circuit is obtained The initial medium thickness degree and initial dielectric constant of each dielectric layer of plate, obtain the thick value of initial copper of each layer of printed circuit board, Wherein, the initial medium thickness degree of layer where the impedance line of printed circuit board is H0, initial dielectric constant be Er0, initial copper thickness value For T0, it is H as the initial medium thickness degree of the screen layer of the impedance line0', initial dielectric constant be Er0′.Specifically, can root According to customer demand, according to the design requirement of PCB thickness of slab, bus plane, stratum etc., and signal frequency, signal rate on PCB Laminated construction design is carried out Deng selection suitable material, and it is normal to obtain the initial medium thickness degree and initial dielectric of each dielectric layer Number, obtains the thick value of initial copper of each layer of printed circuit board.
Alternatively, in step sl, the initial medium thickness degree > 100 of the core plate of layer where the impedance line of printed circuit board μm, and/or, it is used as 100 μm of the initial medium thickness degree > of the prepreg of the screen layer of the impedance line.And then, impedance line institute Initial medium thickness degree in the core plate of layer, as the impedance line screen layer prepreg initial medium thickness degree compared with Thickness, more preferably, impedance design parameter can be controlled preferably uniformity when carrying out impedance design.Alternatively, the resistance of printed circuit board The initial copper thickness value of layer where anti-line is 8 μm, 12 μm or 18 μm, be 8 μm as the initial copper thickness value of the screen layer of the impedance line, 12 μm or 18 μm.And then, copper thickness value is thicker, and more preferably, impedance design parameter can be more preferable during progress impedance design for copper thickness uniformity Control, impedance control difficulty reduction.Alternatively, each dielectric layer of printed circuit board is low-k elastomeric material, can Further reduce impedance control difficulty.Specifically, low-k elastomeric material refers to the material that dielectric constant Er is less than 4.0.
S2, impedance design:Required according to the impedance control of printed circuit board, and according to each data obtained in step S1, Impedance design is carried out using impedance design software, the initial impedance design parameter of the impedance line of printed circuit board is obtained.Specifically, When the impedance line is single-ended impedance line, the initial impedance design parameter is initially upper line width values W10With initial lower line width values W20;When the impedance line is differential impedance line, the initial impedance design parameter is initially upper line width values W10, it is initial offline Width values W20With initial lower line width values W20/ initial line is away from value S0
S3, sawing sheet and optimization impedance design:Core plate and prepreg are carried out by sawing sheet according to PCB layouts size, choosing should The core plate and prepreg of same batch after sawing sheet are tested, the actual core thickness H of layer where obtaining impedance line1And reality Core plate dielectric constant Er1, obtain the actual prepreg thickness H of the screen layer as the impedance line2With actual prepreg dielectric Constant Er2, respectively by H1、H2、Er1、Er2With corresponding H0、H0′、Er0、Er0' contrasted, if H1、H2With H0、H0' difference In preset thickness control tolerance, Er1、Er2With Er0、Er0' difference default dielectric constant control tolerance in, then still select The initial impedance design parameter obtained in step S2 is used as new impedance design parameter;If H1、H2With H0、H0' difference default Beyond thickness control tolerance, Er1、Er2With Er0、Er0' difference default dielectric constant control tolerance beyond, then by H1、H2、 Er1、Er2Bring impedance design software into and optimize the first impedance design parameter after impedance design, and output adjustment as new Impedance design parameter.
Thickness of dielectric layers, dielectric constant due to different batches PCB material etc. have certain fluctuation, and this fluctuation is for normal The impedance control of rule impedance product (impedance control accuracy tolerance >=± 10%) has certain influence but less big, and for high accuracy The influence of impedance product (impedance control accuracy tolerance < ± 10% such as ± 7% or ± 5%) can not be ignored, and be easily caused this most The impedance control of whole high-precision product is exceeded.The step S3, by after sawing sheet, choosing the core plate and semi-solid preparation with batch Piece, retests the H obtained after sawing sheet1、H2、Er1、Er2Value, then by H1With H0、H2With H0′、Er1With Er0、Er2With Er0' point Do not contrasted, control tolerance and default dielectric constant control tolerance to adjust accordingly amendment according to preset thickness, obtain new Impedance design parameter, and then to being adjusted according to actual production factor to impedance control, it is possible to resolve printed circuit board is because of life Production factor causes the unmanageable problem of interior layer impedance, improves the impedance qualification rate of product.
Alternatively, the thickness value of core plate and prepreg can be obtained using 9 method tests, calculating, Resonant-cavity Method can be used Test obtains the dielectric constant values of core plate and prepreg., can when choosing the core plate and prepreg of the same batch after the sawing sheet Choose 1~3 core plate and 1~3 prepreg is tested respectively, then the average corresponding thickness value of acquisition and dielectric Constant value, tests more accurate, also more accurate to impedance control.Alternatively, preset thickness control tolerance can be ± 1%, Refer to≤± 1% in preset thickness control tolerance, refer to > ± 1% beyond preset thickness control tolerance.Default dielectric is normal Numerical control tolerance can be ± 0.1, refer to≤± 0.1 in default dielectric constant control tolerance, in the control of default dielectric constant Refer to > ± 0.1 beyond tolerance.And then, the control accuracy of internal layer impedance is high, can meet actual demand.
S4, making internal layer circuit:Internal layer circuit making is carried out to the core plate of layer where the impedance line after step S3, Test obtains the thick value T of actual copper of the core plate of impedance line place layer after development, before etching, by (T-T ') and T0Contrasted, if (T-T ') and T0Difference default copper thickness control tolerance in, then the new impedance design parameter conduct obtained in optional step S3 Newest impedance design parameter;If (T-T ') and T0Difference default copper thickness control tolerance beyond, then bring T into impedance designs Software optimizes the second impedance design parameter after impedance design, and output adjustment as newest impedance design parameter, its In, T ' expression brown influence values;Make FA plates to be etched, the practical impedance design parameter of the FA plates is tested after etching, and will Practical impedance design parameter is contrasted with newest impedance design parameter, if both differences control tolerance in default impedance parameter It is interior, then can subsequently it be produced in batches;If both differences adjust the production of etching beyond default impedance parameter control tolerance Parameter, remakes FA plates and the impedance design parameter tested after etching, until difference is in default impedance parameter control tolerance, Then produced in batches with the manufacturing parameter of the etching after adjustment.
The step S4, by make internal layer circuit when, test development after, etching before impedance line where layer core plate The thick value T of actual copper, and by (T-T ') and T0Contrasted, and then impedance design parameter is entered according to default copper thickness control tolerance The further adjustment amendment of row, obtains newest impedance design parameter, to the shadow of impedance when then being produced further according to actual etching Ring and amendment is adjusted to the manufacturing parameter of etching, can effectively solve printed circuit board because the factor of production causes interior layer impedance to be difficult to The problem of control, improve the impedance qualification rate of product.In addition, in comparison process, follow-up brown influence is also taken into full account, it is right Impedance control is more accurate, can effectively improve the impedance qualification rate of product.
In the present embodiment, the specific step of internal layer circuit making is carried out to the core plate of layer where the impedance line after step S3 Suddenly it is:Core plate table copper is roughened using chemical micro etching method, cleaned, then pad pasting, and figure is carried out using LDI exposure machines Transfer.The thick value T of actual copper can be tested using copper thickness measuring instrument.Likewise, when above-mentioned core plate and prepreg are 1~3, It can be tested respectively, the thick value of the corresponding copper of acquisition of then averaging is tested more accurate.Alternatively, copper thickness control is preset Tolerance can be ± 1 μm, refer to≤± 1 μm in preset thickness control tolerance, refer to > beyond preset thickness control tolerance It is ± 1 μm, high to impedance control precision.Alternatively, the T ' is 0.5 μm, meets actual brown influence.
Further, in the step S4, the manufacturing parameter of the etching after with adjustment carry out batch production step it Afterwards, in addition to step:Carry out taking a sample test inspection in batch production process, the impedance design ginseng of the impedance line of product after test etching Whether number is hindered in default impedance parameter control tolerance, if proceeding batch production;If not existing, according to test result Manufacturing parameter to etching is adjusted.By carrying out taking a sample test inspection, etching parameter can be finely tuned in real time according to test result, entered One step controls the interior layer impedance of internal layer circuit so that the interior layer impedance of multilayer printed circuit board meets high-precision requirement, effectively carries High impedance qualification rate.
S5, post processing form the printed circuit board of Multilayer Structure.
The preparation method of the printed circuit board, carries out stepped construction design successively according to customer demand first and impedance is set Meter, obtains each initial parameter of each dielectric layer of printed circuit board, and then obtain in printed circuit board by impedance design software Impedance line initial impedance design parameter, then after sawing sheet according to the material actual parameter after actual sawing sheet to initial impedance Design parameter is adjusted amendment, and is influenceed during making internal layer circuit according to actual production factor to new resistance Anti- design parameter is adjusted amendment, and the manufacturing parameter to etching is adjusted, and obtains the printed circuit board of Multilayer Structure.
Usually, the factor of influence PCB impedances mainly has line width, thickness of dielectric layers, copper thickness, dielectric constant, welding resistance thickness Degree etc..The impedance control of outer layer impedance line is more difficult than internal layer, and the line loss of outer layer microstrip line etc. is also than internal layer banding Line is bigger, thus the high-speed impedance line of High-Speed PCB product is typically located at PCB internal layer.The making side of the printed circuit board A kind of method, it is possible to provide the preparation method of the multilayer printed circuit board of layer impedance in high accuracy, passes through sawing sheet and making internal layer circuit Manufacturing process in influence impedance value factor correct, it is possible to resolve printed circuit board because in production process each factor cause The interior unmanageable problem of layer impedance, stably controls the interior layer impedance of printed circuit board to meet high-precision requirement, improves print The high speed transmission of signals performance of circuit board processed, and then the impedance qualification rate of printed circuit board can be improved, impedance scrappage is reduced, Production cost is reduced, is reduced because handing over phase tardy problem caused by the bad problem of impedance, be particularly suitable for use in high-precision impedance product The making of (internal layer impedance control precision is less than ± 10%, is such as ± 7%, ± 5% tolerance), can be effectively improved high-precision impedance The problem of impedance qualification rate of product is low.
Further, as shown in Figure 1 and Figure 2, before step S1, the preparation method of the printed circuit board also includes step Suddenly:
S0, file optimization design:After the completion of PCB routing, in the spacious area of the graphic designs of printed circuit board And/or isolated line region laying balance copper point.The regions such as spacious area, isolated line by the graphic designs in PCB laying balance Copper point, can lift the residual copper distributing homogeneity of figure, and then reach the requirement of high-precision impedance control.In the present embodiment, put down Weighing apparatus copper point can be laid according to actual conditions, and PCB files are suitably optimized, the basis of PCB electric properties is not being influenceed On, reach high-precision impedance control requirement.Alternatively, the balance copper point can be laid in certain size, spacing square or Circle, its size, spacing can be determined according to the residual copper rate of graphics field, it is ensured that the residual copper rate in the balance copper point region of laying It is suitable with graphics field.
Further, the step S5 specifically includes following steps:
S51, brown, pressing:The core plate of layer where impedance line is subjected to brown processing and obtains brown layer, and using after sawing sheet The prepreg of same batch overlapped so that prepreg is located between core plate, forms laminated plate, passes through heat pressing process pair Superimposed sheet carries out pressing and forms multi-layer sheet;
S52, drilling, plating, outer-layer circuit etching, welding resistance:Multi-layer sheet is drilled, electroplated, outer-layer circuit etching with And welding resistance makes, the printed circuit board of complete Multilayer Structure is formed.Specifically, conventional impedance control can be used in step S52 The printed circuit board manufacture craft of precision processed is made.
By using above-mentioned steps, subsequent treatment can be carried out to the product of the batch production after the control of S4 steps, entered And obtain the printed circuit board of Multilayer Structure.
Further, in step s 51:When carrying out heat pressing process, the pressing program of material is adjusted, is buffered during adjustment lamination The consumption of material so that the heating rate of material lowers 0.2 DEG C/min~0.5 DEG C/min.Specifically, the heating rate phase of material 0.2 DEG C/min~0.5 DEG C/min is lowered for the conventional parameter that makes.And then, it can improve Jie in the case where ensureing that filler is good The thickness evenness of matter layer, further reduction impedance control difficulty, improves the impedance qualification rate of product.Further, in step Between S51 and S52, core plate can not carry out processing of doing over again, in order to avoid influence impedance control.
In the present embodiment, after step s 5, the preparation method of the printed circuit board is further comprising the steps of:
S6, testing impedance:The impedance value for the printed circuit board tested using TDR equipment after batch production, and according to impedance Tolerance is controlled to judge whether the interior layer impedance of printed circuit board is qualified.And then, the product after making can be detected, judged Whether the interior layer impedance of product is qualified, easy to operate.In the present embodiment, 35ps TDR equipment can be less than using the rise time Tested, the impedance value of the printed circuit board of layer impedance in high accuracy can be tested.
The preparation method of printed circuit board described in the present embodiment, by printed circuit board is carried out file optimization design, Laminated construction design, impedance design etc., are monitored to each factor for influenceing impedance value and adjust in real time in process of production, energy Printed circuit board is enough solved because the factors such as design and producing cause the unmanageable problem of interior layer impedance, multilayer can be stably controlled The interior layer impedance of printed circuit board meets high-precision requirement, and is remarkably improved different zones signal wire in the big plate of same Impedance uniformity, it is to avoid PCB high speeds signal wire causes the signal integrities such as signal reflex and distortion because of impedance mismatch problem Sex chromosome mosaicism, so as to improve the high speed transmission of signals performance of printed circuit board, the impedance for being obviously improved high-precision impedance PCB is qualified Rate, reduction impedance scrappage and its friendship phase tardy problem that brings etc., its have it is workable, work well, effectively lifted The advantages of impedance qualification rate.
A kind of printed circuit board, is made using the preparation method of printed circuit board as described above and obtained.Specifically, this reality The printed circuit board for applying example is Multilayer Structure, and it includes multiple core plates and prepreg, and the core plate forms circuit through making Figure, multiple core plates are combined with prepreg, and obtain multilayer printed circuit board through pressing.Also, the biography of the printed circuit board Defeated line has the requirement of internal layer impedance control, and its internal layer impedance control precision is high-precision for such as ± 7%, ± 5% tolerance less than ± 10% Degree control is required.The printed circuit board, is made using the preparation method of above-mentioned printed circuit board and obtained, the impedance of product is closed Lattice rate is high, production cost is low, is less prone to the bad problem of impedance.
For the preparation method of the printed circuit board that more fully understands the present embodiment, with reference to an instantiation to the system Describe in detail and illustrate as method:
As shown in figure 3, the printed circuit board that need to be made is 8 Rotating fields, the arrangement difference of each layer is as follows:ART01 layers are SIG01 layers, ART02 layers are GND01 layers, and ART03 layers are SIG02 layers, and ART04 layers are GND02 layers, and ART05 layers are POWER layers, ART06 layers are SIG03 layers, and ART07 layers are GND03 layers, and ART08 layers are SIG04 layers.Wherein, SIG02 layers, SIG03 layers are high speed The wiring layer of the impedance line of signal, wherein, every layer is arranged with single-ended impedance line 300 and differential impedance line 400, the resistance of impedance line Anti- required precision is strict, and impedance control tolerance is within ± 5%.For the making of the printed circuit board of layer impedance in this high accuracy Method correspondence comprises the following steps:
S0, file optimization design:PCB files are suitably optimized, in the spacious area of the inner figure of PCB layouts, isolated Balance copper point is laid in the regions such as line, lifts the residual copper distributing homogeneity of figure, wherein, balance copper point can be laid in circle, circle Diameter can be 1.25mm, and the centre-to-centre spacing of adjacent circle up and down can be 2mm.
S1, laminated construction design:Signal in the design requirement and PCB of thickness of slab, bus plane, stratum according to PCB etc. The requirement such as frequency, speed, selection Low Dk/Low Loss modification FR4 materials carry out laminated construction design.Wherein, can basis Experience Design obtain SIG01 layers to GND01 layers dielectric layer (prepreg 100), GND01 layers to SIG02 layers of dielectric layer (core Plate 200), SIG02 layers to GND02 layers of dielectric layer (prepreg 100), GND02 layers to POWER layers of dielectric layer (core plate 200), POWER layers to SIG03 layers of dielectric layer (prepreg 100), SIG03 layers to GND03 layers of dielectric layer (core plate 200), The initial medium thickness degree and initial dielectric constant of GND03 layers to SIG04 layers of dielectric layer (prepreg 100).And be designed to It is 18 μm to the thick value of SIG01 layers, GND01 layers, GND03 layers and SIG04 layers of initial copper, SIG02 layers, SIG03 layers, GND02 Layer and POWER layer initial copper thickness value be 12 μm.VLP types may be selected in copper foil type.
S2, impedance design:After the completion of laminated construction design, according to the data obtained in impedance control requirement and S1, use Impedance design software carries out corresponding impedance design, obtains the initial impedance design parameter of each impedance line of printed circuit board. In the example, SIG02 layers and SIG03 layers of impedance line has impedance control requirement, and SIG02 layers and SIG03 layers of impedance line is High-speed signal transmission lines, impedance control tolerance is ± 5%, and the single-ended impedance required value of each impedance layer is 50ohm, difference resistance Anti- required value is 100ohm.SIG02 layers of reference screen layer is GND01 layers and GND02 layers, SIG03 layers of reference screen layer For POWER layers and GND03 layers.The initial of the single-ended impedance line that meets above-mentioned process conditions can be calculated by impedance design software Impedance design parameter is initial upper line width values W10With initial lower line width values W20, the initial impedance design parameter of differential impedance line is Initial upper line width values W10, initial lower line width values W20With initial lower line width values W20/ initial line is away from value S0
S3, sawing sheet and optimization impedance design:The core plate and prepreg of specified material are cut into according to PCB layouts size Certain size.By taking SIG02 layers of single-ended impedance line 300 as an example, choose and can be used for ART02 layers and ART03 layers of core plate 3, use 9 methods, which are tested the thickness of every piece of core plate and calculated, is worth to H1, choose the prepreg available for ART03 layers and ART04 layers 3 are pressed into plate respectively, its thickness are tested with 9 methods and is calculated being worth to H2, core plate and half is surveyed admittedly using Resonant-cavity Method Change the dielectric constant difference Er of piece1And Er2, respectively by H1、H2、Er1、Er2With corresponding H0、H0′、Er0、Er0' contrasted, obtain To the new impedance design parameter of SIG02 layers of single-ended impedance lines.Likewise, differential impedance line, SIG03 for SIG02 layers The single-ended impedance line and SIG03 layers of differential impedance line of layer can obtain corresponding new impedance design ginseng using previous step Number.
S4, making internal layer circuit:Core plate table copper is roughened using chemical micro etching method, cleaned, 25 μm are then pasted The LDI dry films of thickness, and pattern transfer is carried out using LDI exposure machines.After development, using the test of copper thickness measuring instrument before etching The actual copper thickness value of ART03 layers and ART06 layers of core plate is respectively T1And T2, by (T1- 0.5) the initial copper thickness with ART03 layers is worth Contrasted, by (T2- 0.5) the thick value of initial copper with ART06 layers is contrasted, and obtains the newest impedance of the impedance line of each layer Design parameter.Further, selection ART02 is used with ART03 layers, ART06 and each one piece of ART07 layers of core plate as FA plates 4.2m/min etching speed makes first plate, tests the impedance of ART03 layers and ART06 layers after the completion of etching using wire width measuring instrument The practical impedance design parameter of line, is then contrasted with impedance design parameter newest in previous step respectively, it is determined that being with this Manufacturing parameter during etching produce or manufacturing parameter is adjusted, until meeting after condition with the etching after adjustment Manufacturing parameter is produced in batches.Every 10 pieces of core plates take a sample test one piece of progress practical impedance design parameter inspection in batch production process Survey, finely tune etching manufacturing parameter in real time according to test result.
S51, brown, pressing:Control qualified core plate to carry out brown processing line above-mentioned line width and obtain brown layer, and use It is foregoing tested thickness, the same batch prepreg of dielectric constant is followed closely to form superimposed sheet through bonding, riveter, prepreg be located at core Between plate, and multi-layer sheet is formed to superimposed sheet progress pressing by heat pressing process.Further, being optimized and revised during pressing to press Temperature programming section time lengthening 3min, the consumption of brown paper is consistent with conventional upper plate during lamination so that the heating of actual measurement material Speed drops to 2.8 DEG C/min compared to 3.2 DEG C/min of normal parameter.
S52, drilling, plating, outer-layer circuit etching, welding resistance etc.:Routinely the printed circuit board of impedance control precision makes The making such as technique is drilled, electroplated, outer-layer circuit etching, welding resistance, form the printed circuit of 8 veneer structures of structural integrity Plate;
S6, testing impedance:The rise time is used to test the printing of 8 veneer structure for 22.3ps vector network analyzer The impedance value of circuit board, judges whether each impedance value is satisfied by the requirement of ± 5% tolerance, judges whether product is qualified.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited In contradiction, the scope of this specification record is all considered to be.
Embodiment described above only expresses the several embodiments of the present invention, and it describes more specific and detailed, but simultaneously Can not therefore it be construed as limiting the scope of the patent.It should be pointed out that coming for one of ordinary skill in the art Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.

Claims (10)

1. a kind of preparation method of printed circuit board, it is characterised in that comprise the following steps:
S1, stepped construction design:Laminated construction design is carried out according to the design requirement of printed circuit board, printed circuit board is obtained The initial medium thickness degree and initial dielectric constant of each dielectric layer, obtain the thick value of initial copper of each layer of printed circuit board, wherein, The initial medium thickness degree of layer where the impedance line of printed circuit board is H0, initial dielectric constant be Er0, initial copper thickness value be T0, It is H as the initial medium thickness degree of the screen layer of the impedance line0', initial dielectric constant be Er0′;
S2, impedance design:Required according to the impedance control of printed circuit board, impedance design is carried out using impedance design software, obtained Obtain the initial impedance design parameter of the impedance line of printed circuit board;
S3, sawing sheet and optimization impedance design:Core plate and prepreg are carried out by sawing sheet according to PCB layouts size, the sawing sheet is chosen The core plate and prepreg of same batch afterwards are tested, the actual core thickness H of layer where obtaining impedance line1With actual core plate Dielectric constant Er1, obtain the actual prepreg thickness H of the screen layer as the impedance line2With actual prepreg dielectric constant Er2, respectively by H1、H2、Er1、Er2With corresponding H0、H0′、Er0、Er0' contrasted, if H1、H2With H0、H0' difference pre- If in thickness control tolerance, Er1、Er2With Er0、Er0' difference in default dielectric constant control tolerance, then still optional step The initial impedance design parameter obtained in S2 is used as new impedance design parameter;If H1、H2With H0、H0' difference in preset thickness Control beyond tolerance, Er1、Er2With Er0、Er0' difference default dielectric constant control tolerance beyond, then by H1、H2、Er1、Er2 Bring impedance design software into and optimize the first impedance design parameter after impedance design, and output adjustment and set as new impedance Count parameter;
S4, making internal layer circuit:Internal layer circuit making is carried out to the core plate of layer where the impedance line after step S3, in development Afterwards, the thick value T of the actual copper of the core plate of layer where test obtains impedance line before etching, by (T-T ') and T0Contrasted, if (T- T ') and T0Difference default copper thickness control tolerance in, then the new impedance design parameter obtained in optional step S3 is as most New impedance design parameter;If (T-T ') and T0Difference default copper thickness control tolerance beyond, then bring T into impedance designs soft Part optimizes the second impedance design parameter after impedance design, and output adjustment as newest impedance design parameter, wherein, T ' expression brown influence values;
Make FA plates to be etched, test the practical impedance design parameter of the FA plates after etching, and by practical impedance design parameter Contrasted with newest impedance design parameter, if both differences can be carried out follow-up in default impedance parameter control tolerance Batch production;If both differences adjust the manufacturing parameter of etching, remake FA beyond default impedance parameter control tolerance Plate and the impedance design parameter tested after etching, until difference is in default impedance parameter control tolerance, then with the erosion after adjustment The manufacturing parameter at quarter is produced in batches;
S5, post processing form the printed circuit board of Multilayer Structure.
2. the preparation method of printed circuit board according to claim 1, it is characterised in that before step S1, in addition to Step:
S0, file optimization design:After the completion of PCB routing, in the spacious area of the graphic designs of printed circuit board and/or Lay balance copper point in isolated line region.
3. the preparation method of printed circuit board according to claim 1, it is characterised in that in the step S1:Printing 100 μm of the initial medium thickness degree > of the core plate of layer where the impedance line of circuit board, and/or, it is used as the screen layer of the impedance line Prepreg 100 μm of initial medium thickness degree >.
4. the preparation method of printed circuit board according to claim 1, it is characterised in that in the step S1:Printing The initial copper thickness value of layer where the impedance line of circuit board is 8 μm, 12 μm or 18 μm, is used as the initial copper of the screen layer of the impedance line Thickness value is 8 μm, 12 μm or 18 μm.
5. the preparation method of printed circuit board according to claim 1, it is characterised in that in the step S1:Printing Each dielectric layer of circuit board is low-k elastomeric material.
6. the preparation method of printed circuit board according to claim 1, it is characterised in that the step S5 specifically include with Lower step:
S51, brown, pressing:The core plate of layer where impedance line is subjected to brown processing and obtains brown layer, and using same after sawing sheet The prepreg of batch is overlapped so that prepreg is located between core plate, forms laminated plate, by heat pressing process to overlapping Plate carries out pressing and forms multi-layer sheet;
S52, drilling, plating, outer-layer circuit etching, welding resistance:Multi-layer sheet is drilled, electroplated, outer-layer circuit is etched and hindered Work is welded, the printed circuit board of complete Multilayer Structure is formed.
7. the preparation method of printed circuit board according to claim 6, it is characterised in that in the step S51:Carry out During heat pressing process, the pressing program of material is adjusted, the consumption of padded coaming during adjustment lamination so that the heating rate of material is lowered 0.2 DEG C/min~0.5 DEG C/min.
8. the preparation method of printed circuit board according to claim 1, it is characterised in that in the step S4, with The manufacturing parameter of etching after adjustment is carried out after batch production step, in addition to step:Taken out in batch production process Survey and examine, whether the impedance design parameter of the impedance line of product is hindered in default impedance parameter control tolerance after test etching, if Proceeding batch production;If not existing, the manufacturing parameter of etching is adjusted according to test result.
9. the preparation method of the printed circuit board according to claim any one of 1-8, it is characterised in that step S5 it Afterwards, it is further comprising the steps of:
S6, testing impedance:The impedance value for the printed circuit board tested using TDR equipment after batch production, and according to impedance control Tolerance judges whether the interior layer impedance of printed circuit board is qualified.
10. a kind of printed circuit board, it is characterised in that using the system of the printed circuit board as described in claim any one of 1-9 Make method making to obtain.
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107872921A (en) * 2017-08-30 2018-04-03 奥士康精密电路(惠州)有限公司 A kind of design method of characteristic impedance
WO2018233271A1 (en) * 2017-06-20 2018-12-27 广州兴森快捷电路科技有限公司 Printed circuit board and fabrication method therefor
CN109815609A (en) * 2019-01-31 2019-05-28 生益电子股份有限公司 A kind of impedance big data automatically analyzes and optimization method and system
CN109870641A (en) * 2019-02-26 2019-06-11 广州兴森快捷电路科技有限公司 Printed circuit plate producing process and its semi-finished product impedance detection method
CN110493980A (en) * 2019-09-26 2019-11-22 恩达电路(深圳)有限公司 The production method of multilayer impedance flexible circuit board
TWI719704B (en) * 2019-11-05 2021-02-21 新加坡商鴻運科股份有限公司 Device and method for setting pcb layout parameters and storage medium
CN112580290A (en) * 2020-12-25 2021-03-30 广州兴森快捷电路科技有限公司 PCB manufacturing method, PCB manufacturing device and storage medium
CN112654158A (en) * 2020-12-09 2021-04-13 广州广合科技股份有限公司 Control method for improving impedance precision
CN114501823A (en) * 2022-04-15 2022-05-13 成都万创科技股份有限公司 PCB lamination optimization method and PCB

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4560962A (en) * 1983-08-30 1985-12-24 Burroughs Corporation Multilayered printed circuit board with controlled 100 ohm impedance
JPH09246729A (en) * 1996-03-08 1997-09-19 Hitachi Aic Inc Printed wiring board and manufacture thereof
CN104470212A (en) * 2013-09-25 2015-03-25 珠海方正科技高密电子有限公司 Circuit board impedance line compensation method and device
CN104470266A (en) * 2014-12-09 2015-03-25 深圳怡化电脑股份有限公司 Method for controlling high-speed PCB signal impedance
JP2015204309A (en) * 2014-04-10 2015-11-16 凸版印刷株式会社 Printed wiring board and method of manufacturing the same
CN105653752A (en) * 2014-12-05 2016-06-08 王丽香 Digital signal impedance match circuit designing method
CN105916303A (en) * 2016-05-16 2016-08-31 浪潮电子信息产业股份有限公司 PCB and method for producing same
CN106341948A (en) * 2016-09-09 2017-01-18 郑州云海信息技术有限公司 PCB design method and PCB
CN106604550A (en) * 2016-12-16 2017-04-26 郑州云海信息技术有限公司 Line impedance adjusting method and system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4547958B2 (en) * 2004-03-26 2010-09-22 凸版印刷株式会社 Manufacturing method of multilayer wiring board
CN101227800B (en) * 2008-02-03 2011-05-04 华为终端有限公司 Apparatus and method for implementing high-precision buried resistance
CN105813374B (en) * 2016-04-11 2018-09-25 广州兴森快捷电路科技有限公司 A kind of management-control method of outer layer impedance
CN107094349B (en) * 2017-06-20 2019-08-27 广州兴森快捷电路科技有限公司 Printed circuit board and preparation method thereof

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4560962A (en) * 1983-08-30 1985-12-24 Burroughs Corporation Multilayered printed circuit board with controlled 100 ohm impedance
JPH09246729A (en) * 1996-03-08 1997-09-19 Hitachi Aic Inc Printed wiring board and manufacture thereof
CN104470212A (en) * 2013-09-25 2015-03-25 珠海方正科技高密电子有限公司 Circuit board impedance line compensation method and device
JP2015204309A (en) * 2014-04-10 2015-11-16 凸版印刷株式会社 Printed wiring board and method of manufacturing the same
CN105653752A (en) * 2014-12-05 2016-06-08 王丽香 Digital signal impedance match circuit designing method
CN104470266A (en) * 2014-12-09 2015-03-25 深圳怡化电脑股份有限公司 Method for controlling high-speed PCB signal impedance
CN105916303A (en) * 2016-05-16 2016-08-31 浪潮电子信息产业股份有限公司 PCB and method for producing same
CN106341948A (en) * 2016-09-09 2017-01-18 郑州云海信息技术有限公司 PCB design method and PCB
CN106604550A (en) * 2016-12-16 2017-04-26 郑州云海信息技术有限公司 Line impedance adjusting method and system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
杨盟辉: "高频PCB基材介电常数与介电损耗的特性与改性进展", 《印制电路信息》 *

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018233271A1 (en) * 2017-06-20 2018-12-27 广州兴森快捷电路科技有限公司 Printed circuit board and fabrication method therefor
CN107872921A (en) * 2017-08-30 2018-04-03 奥士康精密电路(惠州)有限公司 A kind of design method of characteristic impedance
CN107872921B (en) * 2017-08-30 2019-10-29 奥士康精密电路(惠州)有限公司 A kind of design method of characteristic impedance
CN109815609A (en) * 2019-01-31 2019-05-28 生益电子股份有限公司 A kind of impedance big data automatically analyzes and optimization method and system
CN109870641A (en) * 2019-02-26 2019-06-11 广州兴森快捷电路科技有限公司 Printed circuit plate producing process and its semi-finished product impedance detection method
CN110493980A (en) * 2019-09-26 2019-11-22 恩达电路(深圳)有限公司 The production method of multilayer impedance flexible circuit board
TWI719704B (en) * 2019-11-05 2021-02-21 新加坡商鴻運科股份有限公司 Device and method for setting pcb layout parameters and storage medium
CN112654158A (en) * 2020-12-09 2021-04-13 广州广合科技股份有限公司 Control method for improving impedance precision
CN112580290A (en) * 2020-12-25 2021-03-30 广州兴森快捷电路科技有限公司 PCB manufacturing method, PCB manufacturing device and storage medium
CN114501823A (en) * 2022-04-15 2022-05-13 成都万创科技股份有限公司 PCB lamination optimization method and PCB
CN114501823B (en) * 2022-04-15 2022-07-01 成都万创科技股份有限公司 PCB lamination optimization method and PCB

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