CN105163483B - A kind of wiring board Dk resolution charts and wiring board Dk test methods - Google Patents
A kind of wiring board Dk resolution charts and wiring board Dk test methods Download PDFInfo
- Publication number
- CN105163483B CN105163483B CN201510573318.3A CN201510573318A CN105163483B CN 105163483 B CN105163483 B CN 105163483B CN 201510573318 A CN201510573318 A CN 201510573318A CN 105163483 B CN105163483 B CN 105163483B
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- China
- Prior art keywords
- wiring board
- impedance line
- impedance
- line
- core plate
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2617—Measuring dielectric properties, e.g. constants
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
Abstract
The present invention is intended to provide a kind of cost is low, measuring accuracy is high and can obtain the wiring board Dk resolution charts that the wiring board Dk test methods of multi-layer coreboard and prepreg Dk values and this method use at the same time.On core plate in graphic designs assist side of the present invention, the figure is made of via hole and impedance line, and the via hole is conducted with the impedance line, and the impedance line is not wide impedance line；1. the method for the present invention selects material -2. to select prepreg and core plate including step（core）- 3. designing the design configuration of folded structure -4. -5., routinely flow feeds intake and makes wiring board -6. using TDR measurement impedances -7. cut into slices and test to test zone -8. being simulated using SI8000 softwares -9. export corresponding Dk.Present invention can apply to hole machined apparatus field.
Description
Technical field
The present invention relates to wiring board Dk testing fields, more particularly to a kind of wiring board Dk resolution charts and wiring board Dk tests
Method.
Background technology
With high-speed line plate（Namely high-speed line plate）Rapid development, the impedance control problem in traditional circuit plate gets over
Hair protrudes.Lower loss in order to obtain, it is desirable to which wiring board impedance control is less than the deviation range within 10%, or even 5%.
In assist side impedance control, Dk is a most important variable.Accurate dielectric layer Dk data in wiring board processing have been obtained,
Very important precondition can be provided for high-precision impedance allowance control.
Traditional Dk test methods are measured mainly in accordance with SPDR methods in IPC TM650, and sample used covers for wiring board
Copper coin etches away the core plate after copper sheet or the prepreg before wiring board copper-clad plate pressing, and obtained Dk is only prefect dielectric
Dk.But substantial amounts of copper foil surface roughening, baking, chemical medicinal liquid processing, mechanical stress processing etc. are introduced in assist side processing
Technique, can play the role of change to Dk of wiring board itself.Therefore, SPDR methods obtain Dk values and wiring board itself
True Dk is far apart.When this results in design impedance, the deviation of Dk can make simulated impedance deviate actual value, so as to also result in
The impedance control precision problem of actual circuit board finished product.
In addition, SPDR methods need to use resonator and VNA, involved equipment price is sufficiently expensive, to wiring board work
For factory, cost performance is very low, therefore rare wiring board factory can buy.
The content of the invention
The technical problems to be solved by the invention are to overcome the deficiencies of the prior art and provide that a kind of cost is low, measuring accuracy
It is high and the wiring board Dk test methods of multi-layer coreboard and prepreg Dk values can be obtained at the same time.
Present invention also offers the wiring board Dk resolution charts applied in above-mentioned wiring board Dk test methods, the figure
It is simple in structure, impedance line antijamming capability can be effectively improved.
Technical solution is used by wiring board Dk resolution charts of the present invention：Graphic designs of the present invention are in circuit
On core plate in plate, the figure is made of via hole and impedance line, and the via hole is conducted with the impedance line, the resistance
Anti- line is not wide impedance line.
Further, the line width that section impedance line is tested on the impedance line is less than the line width in other regions.
Further, the periphery of the tested section impedance line is provided with some ground holes, the aperture of the ground hole
It is identical with the aperture of the via hole, it is 1.0~1.5mm.
Further, ground hole, the aperture of the ground hole and the via hole are provided with the periphery of the via hole
Aperture it is identical, be 1.0~1.5mm.
Further, positioned at the tested section impedance of ground hole aperture edge distance of the tested section impedance line periphery
Line edge spacing is 2mm, the edge spacing of via hole described in the ground hole Edge Distance positioned at via hole periphery for 3~
5mm。
Technical solution is used by wiring board Dk test methods of the present invention：The process employs line as described above
Road plate Dk resolution charts, this method comprise the following steps：
（1）It is corresponding for the every kind of prepreg design included in wiring board to be measured based on wiring board Dk resolution charts
Impedance line, the impedance value of the impedance line are set as 50ohm；
（2）Design is made just like step（1）The wiring board of the impedance line, the wiring board pass through TDR Test, obtain line
The impedance measured value of road plate middle impedance line；
（3）The corresponding impedance line of all and prepreg on the wiring board is done into section test, obtains impedance line
Line width, thickness of dielectric layers and copper thickness parameter；
（4）Step（2）The impedance measured value and step of acquisition（3）The section test parameter of middle acquisition is updated to SI8000
Simulated in impedance computation software, obtain the Dk values of wiring board medium to be measured.
Further, the step（2）In, if if the wiring board by the copper foil positioned at outer layer and dried layer prepreg and
Dry core plate composition, between any two layers of core plate, between copper foil and core plate by prepreg interval, in the one side of the core plate
Impedance line reference layer is set, impedance line is set on another side, when assist side is laminated, if core plate described in dried layer is identical setting
Mode, when core plate impedance line reference layer one side upward when, the one side with impedance line reference layer of whole core plates upward, band
The one side of impedance line is downward；When the one of the impedance line reference layer of core plate is face-down, the band impedance line reference layer of whole core plates
One side downward, the one side with impedance line is upward.
Further, the step（3）In, the position of section is located at the quilt on the impedance line in wiring board Dk resolution charts
Survey section.
Further, the impedance line is single-ended stripline cable architecture, can also be difference banding elder generation structure.
The beneficial effects of the invention are as follows：For the present invention by designing unique wiring board testing impedance figure, use is not wide
Impedance line design, so as to be accurately positioned with impedance line specific location on the corresponding wiring board of TDR values, so as to improve Dk
The precision of test, furthermore, it is possible to obtain more than four kinds of wiring board copper-clad plate core plate and the Dk values of prepreg at the same time；The present invention
Corresponding folded structure is designed according to the prepreg species of required measurement, can increase with prepreg species and increase level, reach
Cover the purpose of all prepreg tests；In addition, the present invention is not related to resonator and VNA needed for SPDR methods, therefore into
This is low, and general wiring board enterprise can be received.
Brief description of the drawings
Fig. 1 is the easy structure schematic diagram of the wiring board Dk resolution charts；
Fig. 2 is the simple cross-sectional structure schematic diagram that wiring board of the present invention is formed；
Fig. 3 is the corresponding TDR Test result corresponding diagram of impedance line graph；
Fig. 4 is the schematic diagram that SI8000 impedance computations software carries out analog result demonstration；
Fig. 5 is the signal of SI8000 impedance computations software progress analog result demonstration when using differential impedance cable architecture
Figure.
Embodiment
As shown in Figures 1 to 5, wiring board Dk resolution charts of the present invention, the core plate 1 in the graphic designs assist side
On, the figure is made of via hole 2 and impedance line 3, and the via hole 2 is conducted with the impedance line 3, the impedance line 3
For not wide impedance line.The line width that section impedance line is tested on the impedance line 3 is less than the line width in other regions.Described
The periphery of tested section impedance line is provided with some ground holes 4, the aperture of the ground hole 4 and the aperture phase of the via hole 2
Together, it is 1.0~1.5mm.Ground hole 4 is provided with the periphery of the via hole 2, the aperture of the ground hole 4 is led with described
The aperture of through hole 2 is identical, is 1.0~1.5mm.Positioned at the tested section impedance line periphery 4 aperture edge of ground hole away from
It is 2mm from tested section impedance line edge spacing, via hole 2 described in 4 Edge Distance of ground hole positioned at the periphery of via hole 2
Edge spacing be 3~5mm.
In the method for the present invention, the testing process of Dk is as follows：1. selection material -2. select prepreg and core plate
（core）- design configuration -5. routinely flow feeds intake and makes wiring board-of folded structure -4. is 3. designed 6. using TDR measurement resistances
It is anti-- 7. to cut into slices and test to test zone -8. using the simulation of SI8000 softwares -9. to export corresponding Dk.
The present invention designs the impedance line of single-ended stripline cable architecture first, and corresponding impedance is designed for every kind of prepreg
Line, the impedance value of the impedance line is 50ohm；Then the wiring board plate for being designed with the impedance line is made；It is described
Wiring board plate passes through TDR Test, obtains the measured value of the impedance line, under normal circumstances, the design load and reality of the impedance line
Measured value has the deviation within 10%；Then all impedance lines corresponding with prepreg model on the wiring board are cut again
Built-in testing, obtains line width, thickness of dielectric layers, copper thickness parameter；Finally, the measured value of each impedance line and section measurement are obtained
Parameter be updated in SI8000 softwares and simulate, obtain Dk values.In this course, have wiring board testing impedance graphic designs and
Wiring board folds structure structure design, and graphic designs therein are by designing unique wiring board testing impedance figure.This method uses
Not wide impedance line design, so as to be accurately positioned with impedance line specific location on the corresponding wiring board of TDR values so that
Improve the precision of Dk tests；The present invention designs corresponding folded structure according to the prepreg species of required measurement, can be with prepreg
Species increases and increases level, achievees the purpose that all prepreg tests of covering.
The detailed process of above-mentioned steps is as follows：
1. select material：The definite material category for needing to test；
2. select prepreg and core plate（core）：Different prepreg options are included in same material, such as 1080,
2116th, the model such as 7628,3313, the thickness and Dk of each model are different from；Core plate, is also core, is to pass through prepreg
Pressing cures what is obtained, can press to obtain by one or more, identical or different prepreg.In the present invention, core plate is suppressed
Prepreg need to be identical with the prepreg species of Dk to be tested, number is identical（Multilayer circuit board is that have core plate and semi-solid preparation
Piece compacting forms, while core plate is using preceding needing pressing one-time, so when the present invention requires core plate compacting to reduce factor of influence
Prepreg it is identical with the prepreg species and number that the multilayer circuit board of test DK described in the invention uses.）
3. the folded structure of design：In the present invention, impedance line design is designed in even number in odd-level, the reference layer of the impedance line
Layer, and outer layer is not related to impedance line；It need to ensure that prepreg structure is identical in the core plate on impedance line two sides；Can be according to needing to survey
The prepreg species of examination increases and increases the lamination number of plies, as shown in Figure 1；
4. graphic designs：Impedance line graphic designs use the design of unequal width, are easy to tell value area on TDR
Between, so that it is determined that the impedance actual value of the PCB；
The TDR Test result of the latter half in Fig. 3（Curved portion）To estimate situation, actual waveform has a little bias,
One-to-one relationship predominantly between explanation impedance line graph and the impedance value of TDR Test herein；Shown impedance line graph is deposited
It is that institute is designed described in folded structure on odd-level just like Fig. 2（Circuit board finished product cross-sectional view as shown in Figure 2, is indicated
The other impedance line of layer corresponding layer not on, and do not interfere with each other with other layer impedance lines）, and due to corresponding prepreg
It is different and with different line widths, dielectric thickness, Dk, but it is 50ohm to design impedance value；The impedance line is by turning on via
Outer layer is drawn out to, the conducting via is only used for testing impedance and is made of and using conventional bore mode, its boring aperture is 1.0
~1.5mm；In addition to impedance line graphic designs, to increase impedance value measuring accuracy, impedance line antijamming capability is improved, also in impedance
Line interval adds ground hole；The ground hole aperture is identical with the via hole aperture, and aperture edge distance is tested
Section impedance line edge spacing 2mm；Ground hole need to be set at 3~5mm around the conducting via；The ground hole aperture and institute
It is identical to state conducting via, is 1mm~1.5mm, the ground hole belongs to PCB conventional designs.
5. routinely flow, which feeds intake, makes wiring board；
The PCB for designing figure and folded structure is made by selected material, forms finished product wiring board.
6. use TDR measurement impedances：Impedance value is measured to each impedance line of design and numbers differentiation；
Tested 7. cutting into slices to test zone：Take section section to do section test to the impedance line indicated in Fig. 3, obtain line
The data of wide, thickness of dielectric layers and copper thickness, and corresponded with its impedance value；
8. simulated using SI8000 softwares：Above-mentioned various parameters are substituted into SI8000 softwares and are simulated, Dk is set to become
Amount, finally obtains simulation result, interface is as shown in Figure 4；
9. export corresponding Dk values：The Dk values by SI8000 emulation with all prepregs used during Design PCB
Model corresponds, and forms Dk tables of data.
When using differential impedance cable architecture, relatively stablize when the advantage is that impedance value test, and the suffered external world is done
Disturb smaller, but shortcoming is that occupied space is larger, and test analysis is increasingly complex.Fig. 5 is shown using differential impedance cable architecture
When SI8000 impedance computations software carry out analog result demonstration schematic diagram.
Present invention can apply to wiring board art.
Claims (8)
1. a kind of wiring board Dk test methods tested using wiring board Dk resolution charts, the wiring board Dk resolution charts
Graphic designs assist side in core plate（1）On, the figure is by via hole（2）And impedance line（3）Composition, the via hole
（2）With the impedance line（3）It is conducted, the impedance line（3）For not wide impedance line, it is characterised in that this method include with
Lower step：
（1）Based on wiring board Dk resolution charts, corresponding impedance is designed for the every kind of prepreg included in wiring board to be measured
Line, the impedance value of the impedance line are set as 50ohm；
（2）Design is made just like step（1）The wiring board of the impedance line, the wiring board pass through TDR Test, obtain wiring board
The impedance measured value of middle impedance line；
（3）The corresponding impedance line of all and prepreg on the wiring board is done into section test, obtain impedance line line width,
Thickness of dielectric layers and copper thickness parameter；
（4）Step（2）The impedance measured value and step of acquisition（3）The section test parameter of middle acquisition is updated to SI8000 impedances
Simulated in software for calculation, obtain the Dk values of wiring board medium to be measured.
2. wiring board Dk test methods according to claim 1, it is characterised in that：The step（2）In, the wiring board
If being made of the copper foil positioned at outer layer and dried layer prepreg and some core plates, between any two layers of core plate, copper foil and core plate it
Between by prepreg interval, impedance line reference layer is set in the one side of the core plate, impedance line is set on another side, online
When road flaggy is folded, if core plate described in dried layer is identical set-up mode, when core plate impedance line reference layer one side upward when, entirely
Upward, the one side with impedance line is downward for the one side with impedance line reference layer of portion's core plate；When the impedance line reference layer of core plate
One it is face-down when, downward, the one side with impedance line is upward for the one side with impedance line reference layer of whole core plates.
3. wiring board Dk test methods according to claim 1, it is characterised in that：The impedance line is single-ended stripline knot
Structure, can also be differential stripline structure.
4. wiring board Dk test methods according to claim 1, it is characterised in that：The impedance line（3）Upper tested section
The line width of impedance line is less than the line width in other regions.
5. wiring board Dk test methods according to claim 4, it is characterised in that：In the outer of the tested section impedance line
Enclose and be provided with some ground holes（4）, the ground hole（4）Aperture and the via hole（2）Aperture it is identical, be 1.0~
1.5mm。
6. wiring board Dk test methods according to claim 5, it is characterised in that：In the via hole（2）Periphery set
It is equipped with ground hole（4）, the ground hole（4）Aperture and the via hole（2）Aperture it is identical, be 1.0~1.5mm.
7. wiring board Dk test methods according to claim 6, it is characterised in that：Outside the tested section impedance line
The ground hole enclosed（4）The tested section impedance line edge spacing of aperture edge distance is 2mm, positioned at the via hole（2）Periphery
Ground hole（4）Via hole described in Edge Distance（2）Edge spacing be 3~5mm.
8. wiring board Dk test methods according to claim 7, it is characterised in that：The step（3）In, the position of section
Tested section on the impedance line in wiring board Dk resolution charts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510573318.3A CN105163483B (en) | 2015-09-10 | 2015-09-10 | A kind of wiring board Dk resolution charts and wiring board Dk test methods |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510573318.3A CN105163483B (en) | 2015-09-10 | 2015-09-10 | A kind of wiring board Dk resolution charts and wiring board Dk test methods |
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| Publication Number | Publication Date |
|---|---|
| CN105163483A CN105163483A (en) | 2015-12-16 |
| CN105163483B true CN105163483B (en) | 2018-04-20 |
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| CN201510573318.3A Expired - Fee Related CN105163483B (en) | 2015-09-10 | 2015-09-10 | A kind of wiring board Dk resolution charts and wiring board Dk test methods |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107328999A (en) * | 2017-07-31 | 2017-11-07 | 深圳崇达多层线路板有限公司 | A kind of method of parameter value needed for acquisition calculates sheet material dielectric constant |
| CN107872921B (en) * | 2017-08-30 | 2019-10-29 | 奥士康精密电路（惠州）有限公司 | A kind of design method of characteristic impedance |
| CN109275259A (en) * | 2018-09-20 | 2019-01-25 | 郑州云海信息技术有限公司 | A kind of production method of pcb board and a kind of pcb board |
| CN109188101A (en) * | 2018-09-25 | 2019-01-11 | 郑州云海信息技术有限公司 | Acquisition methods, system, device and the readable storage medium storing program for executing of medium electric parameter |
| CN109548268A (en) * | 2018-11-01 | 2019-03-29 | 郑州云海信息技术有限公司 | A kind of PCB impedance adjustment, control system and a kind of PCB layout plate |
| CN109581068B (en) * | 2018-11-27 | 2021-03-12 | 深圳崇达多层线路板有限公司 | Effective dielectric constant evaluation test method and system |
| CN109451656B (en) * | 2018-11-27 | 2021-04-23 | 深圳崇达多层线路板有限公司 | Impedance test board |
| CN210579428U (en) * | 2019-06-20 | 2020-05-19 | 深圳Tcl数字技术有限公司 | Circuit board and display device |
| US10674598B1 (en) | 2019-10-08 | 2020-06-02 | Cisco Technology, Inc. | Measuring effective dielectric constant using via-stub resonance |
| CN113079622B (en) * | 2021-03-29 | 2022-05-24 | 生益电子股份有限公司 | PCB manufacturing method and PCB, and floating monitoring method of copper foil at bottom of blind hole |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103913641A (en) * | 2014-03-28 | 2014-07-09 | 广州兴森快捷电路科技有限公司 | Method for obtaining dielectric constant of PCB materials |
| CN205179485U (en) * | 2015-09-10 | 2016-04-20 | 珠海城市职业技术学院 | Circuit board dk tests structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100348409B1 (en) * | 2000-12-29 | 2002-08-10 | 삼성전자 주식회사 | Test coupon having multiple pattern layers and method for measuring dielectric constant of a memory module board |
| US6922062B2 (en) * | 2003-01-02 | 2005-07-26 | Dell Products L.P. | Timing markers for the measurement and testing of the controlled impedance of a circuit board |
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2015
- 2015-09-10 CN CN201510573318.3A patent/CN105163483B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103913641A (en) * | 2014-03-28 | 2014-07-09 | 广州兴森快捷电路科技有限公司 | Method for obtaining dielectric constant of PCB materials |
| CN205179485U (en) * | 2015-09-10 | 2016-04-20 | 珠海城市职业技术学院 | Circuit board dk tests structure |
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