CN105163483A - Circuit board Dk testing pattern and circuit board Dk testing method - Google Patents
Circuit board Dk testing pattern and circuit board Dk testing method Download PDFInfo
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- CN105163483A CN105163483A CN201510573318.3A CN201510573318A CN105163483A CN 105163483 A CN105163483 A CN 105163483A CN 201510573318 A CN201510573318 A CN 201510573318A CN 105163483 A CN105163483 A CN 105163483A
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- wiring board
- impedance line
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- line
- testing
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2617—Measuring dielectric properties, e.g. constants
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention aims at providing a circuit board Dk testing method, which is low in cost and high in test accuracy and is capable of simultaneously obtaining Dk values of multi-layer cores and prepregs, and a circuit board Dk testing pattern employing the method. The pattern is designed on the cores in the circuit board; the pattern comprises a via hole and impedance lines; the via hole is communicated with the impedance lines; and the impedance lines are the impedance lines with different widths. The method provided by the invention comprises the following steps: (1) selecting materials; (2) selecting the prepregs and the cores (core); (3) designing a stack-up structure; (4) designing the pattern; (5) feeding the materials to fabricate the circuit board according to the conventional processes; (6) measuring the impedance by TDR; (7) testing slices in a testing region; (8) carrying out simulation by SI8000 software; and (9) exporting the corresponding Dk. The circuit board Dk testing method and the circuit board Dk testing pattern can be applied to the field of hole processing equipment.
Description
Technical field
The present invention relates to wiring board Dk field tests, particularly relate to a kind of wiring board Dk resolution chart and wiring board Dk method of testing.
Background technology
Along with the develop rapidly of high-speed line plate (being also high-speed line plate), the impedance Control problem in traditional circuit plate is outstanding all the more.In order to obtain lower loss, require that wiring board impedance Control is less than 10%, the deviation range even within 5%.In the anti-control of circuit plate resistance, Dk is a most important variable.Obtain dielectric layer Dk data accurately in wiring board processing, very important precondition can be provided for high-precision impedance allowance control.
Traditional Dk method of testing is mainly measured according to SPDR method in IPCTM650, and sample used is that wiring board copper-clad plate etches away the central layer after copper sheet or the prepreg before wiring board copper-clad plate pressing, and the Dk obtained is only the Dk of prefect dielectric.But in wiring board processing, introduce the techniques such as a large amount of copper foil surface alligatoring, baking, chemical medicinal liquid process, mechanical stress process, all can play the effect of change to the Dk of wiring board own.Therefore, itself true Dk of the Dk value that obtains of SPDR method and wiring board is far apart.When this just causes designing impedance, the deviation of Dk can make simulated impedance depart from actual value, thus also result in the impedance Control precision problem of actual wiring board finished product.
In addition, SPDR method need adopt resonant cavity and VNA, and involved equipment price is very expensive, and for wiring board factory, cost performance is very low, and therefore rare wiring board factory can buy.
Summary of the invention
Technical problem to be solved by this invention overcomes the deficiencies in the prior art, provides that a kind of cost is low, measuring accuracy is high and can obtain the wiring board Dk method of testing of multi-layer coreboard and prepreg Dk value simultaneously.
Present invention also offers the wiring board Dk resolution chart applied in above-mentioned wiring board Dk method of testing, this graphic structure is simple, can effectively improve impedance line antijamming capability.
The technical scheme that wiring board Dk resolution chart of the present invention adopts is: on the central layer of graphic designs of the present invention in wiring board, described figure is made up of via and impedance line, described via and described impedance line are conducted, and described impedance line is not wide impedance line.
Further, on described impedance line, the line width of tested interval impedance line is less than the line width in other region.
Further, the periphery of described tested interval impedance line is provided with some ground holes, and the aperture of described ground hole is identical with the aperture of described via, is 1.0 ~ 1.5mm.
Further, the periphery of described via is provided with ground hole, the aperture of described ground hole is identical with the aperture of described via, is 1.0 ~ 1.5mm.
Further, the ground hole aperture edge being positioned at described tested interval impedance line periphery is 2mm apart from tested interval impedance line Distances Between Neighboring Edge Points, and described in the ground hole Edge Distance being positioned at described via periphery, the Distances Between Neighboring Edge Points of via is 3 ~ 5mm.
The technical scheme that wiring board Dk method of testing of the present invention adopts is: the process employs wiring board Dk resolution chart as above, the method comprises the following steps:
(1) based on wiring board Dk resolution chart, for the impedance line that the often kind of prepreg design comprised in wiring board to be measured is corresponding, the resistance value of described impedance line is all set as 50ohm;
(2) make the wiring board being designed with impedance line as described in step (1), described wiring board, through TDR Test, obtains the impedance measured value of wiring board middle impedance line;
(3) all corresponding with the prepreg impedance line on described wiring board is done section test, obtain the thick parameter of the live width of impedance line, thickness of dielectric layers and copper;
(4) the section test parameter obtained in impedance measured value step (2) obtained and step (3) is updated in SI8000 impedance computation software simulates, and obtains the Dk value of wiring board medium to be measured.
Further, in described step (2), described wiring board forms by being positioned at outer field Copper Foil and some layers of prepreg and some central layers, by prepreg interval between any two-layer central layer, between Copper Foil and central layer, the one side of described central layer arranges impedance line reference layer, another side arranges impedance line, when pcb layer is folded, the described central layer of some layers is identical set-up mode, when central layer impedance line reference layer one face up time, all upward, the one side of band impedance line all down for the one side of the band impedance line reference layer of whole central layer; When central layer impedance line reference layer one face down time, the one side of the band impedance line reference layer of whole central layer all down, band impedance line one side all upward.
Further, in described step (3), the position of section is arranged in the tested interval on the impedance line of wiring board Dk resolution chart.
Further, described impedance line is single-ended stripline line structure, can also be the banded first structure of difference.
The invention has the beneficial effects as follows: the present invention is by the wiring board testing impedance figure of design uniqueness, adopt not wide impedance line design, thus accurately can locate impedance line particular location on the wiring board corresponding with TDR value, thus improve the precision of Dk test, in addition, the wiring board copper-clad plate central layer of more than four kinds and the Dk value of prepreg can be obtained simultaneously; The folded structure that the present invention is corresponding according to the prepreg kind design of required measurement, can increase with prepreg kind and increase level, reach the object covering the test of all prepregs; In addition, the present invention does not relate to resonant cavity required in SPDR method and VNA, therefore cost is low, all can accept general wiring board enterprise.
Accompanying drawing explanation
Fig. 1 is the easy structure schematic diagram of described wiring board Dk resolution chart;
Fig. 2 is the simple and easy cross-sectional structure schematic diagram that wiring board of the present invention is formed;
Fig. 3 is the TDR Test result corresponding diagram that impedance line figure is corresponding with it;
Fig. 4 is the schematic diagram that SI8000 impedance computation software carries out analog result demonstration;
Fig. 5 is that the SI8000 impedance computation software when adopting differential impedance line structure carries out the schematic diagram of analog result demonstration.
Embodiment
As shown in Figures 1 to 5, wiring board Dk resolution chart of the present invention, on the central layer 1 of this graphic designs in wiring board, described figure is made up of via 2 and impedance line 3, described via 2 is conducted with described impedance line 3, and described impedance line 3 is not wide impedance line.On described impedance line 3, the line width of tested interval impedance line is less than the line width in other region.The periphery of described tested interval impedance line is provided with some ground holes 4, and the aperture of described ground hole 4 is identical with the aperture of described via 2, is 1.0 ~ 1.5mm.The periphery of described via 2 is provided with ground hole 4, and the aperture of described ground hole 4 is identical with the aperture of described via 2, is 1.0 ~ 1.5mm.Ground hole 4 aperture edge being positioned at described tested interval impedance line periphery is 2mm apart from tested interval impedance line Distances Between Neighboring Edge Points, and described in ground hole 4 Edge Distance being positioned at described via 2 periphery, the Distances Between Neighboring Edge Points of via 2 is 3 ~ 5mm.
In the inventive method, the testing process of Dk is as follows: 1. selection material-2. select prepreg and central layer (core)-3. folded structure-4. design configuration of design-5. routinely flow process feed intake making wiring board-6. use TDR measurement impedance-7. to test zone section test-8. use SI8000 software simulation-9. derive corresponding Dk.
First the present invention designs the impedance line of single-ended stripline line structure, and for the impedance line that often kind of prepreg design is corresponding, the resistance value of described impedance line is 50ohm; Then the wiring board plate being designed with described impedance line is made; Described wiring board plate, through TDR Test, obtains the measured value of described impedance line, and generally, the design load of described impedance line and measured value have the deviation within 10%; And then all impedance lines corresponding with prepreg model on described wiring board are done to cut into slices test, obtain live width, thickness of dielectric layers, the thick parameter of copper; Finally, the parameter that the measured value of described each impedance line and section measurement obtain is updated in SI8000 software and simulates, obtain Dk value.In this course, have the anti-resolution chart design of circuit plate resistance and wiring board to fold structure structural design, graphic designs is wherein by the wiring board testing impedance figure of design uniqueness.This method adopts not wide impedance line design, thus accurately can locate impedance line particular location on the wiring board corresponding with TDR value, thus improves the precision of Dk test; The folded structure that the present invention is corresponding according to the prepreg kind design of required measurement, can increase with prepreg kind and increase level, reach the object covering the test of all prepregs.
The detailed process of above-mentioned steps is as follows:
1. selection material: determine the material category needing test;
2. select prepreg and central layer (core): comprise different prepreg option in commaterial, as the models such as 1080,2116,7628,3313, the thickness of each model is not identical with Dk; Central layer, is also core, is obtained by prepreg pressing solidification, can by one or more, identical or different prepreg pressing obtains.In the present invention, the prepreg of compacting central layer need be identical with the prepreg kind will testing Dk, number is identical, and (multilayer circuit board has central layer and prepreg compacting to form, central layer needs pressing one-time before using simultaneously, so prepreg when the present invention is minimizing factor of influence requirement central layer compacting is identical with the prepreg kind that the multilayer circuit board of the DK of test described in the invention uses and number.）
3. the folded structure of design: in the present invention, by impedance line design at odd-level, the reference layer design of described impedance line is at even level, and skin does not relate to impedance line; Need ensure that in the central layer on impedance line two sides, prepreg structure is identical; Can increase according to the prepreg kind that need test and increase the lamination number of plies, as shown in Figure 1;
4. graphic designs: impedance line graphic designs adopts the design not waiting width, TDR is easy to tell interval, thus determines the impedance actual value of described PCB;
In Fig. 3, the TDR Test result (curved portion) of the latter half is estimation situation, and actual waveform has a little bias, is mainly herein and one-to-one relationship between impedance line figure and the resistance value of TDR Test is described; Shown impedance line figure be present in design (wiring board finished product cross sectional representation as shown in Figure 2 on odd-level described in folded structure just like Fig. 2, institute's other impedance line of layer of indicating is not gone up at each self-corresponding layer, and do not interfere with each other with other layer impedance lines), and have different live widths, dielectric thickness, Dk due to the prepreg difference of correspondence, but design resistance value is 50ohm; Described impedance line is drawn out to skin by conducting via hole, described conducting via hole only for testing impedance with and use conventional bore mode to make, its boring aperture is 1.0 ~ 1.5mm; Except impedance line graphic designs, for increasing resistance value measuring accuracy, improving impedance line antijamming capability, also adding ground hole at impedance line interval; Described ground hole aperture is identical with described via aperture, and aperture edge is apart from tested interval impedance line Distances Between Neighboring Edge Points 2mm; Around described conducting via hole, 3 ~ 5mm place need arrange ground hole; Described ground hole aperture is identical with described conducting via hole, is 1mm ~ 1.5mm, and described ground hole belongs to PCB conventional design.
5. flow process feeds intake making wiring board routinely;
The PCB designing figure and folded structure is made by selected material, forms finished product wiring board.
6. TDR measurement impedance is used: to each impedance line measurement impedance value of design and numbering differentiation;
7. to test zone section test: to the impedance line indicated in Fig. 3 get section interval do section test, obtain the data that live width, thickness of dielectric layers and copper are thick, and with its resistance value one_to_one corresponding;
8. SI8000 software simulation is used: above-mentioned various parameters substituted in SI8000 software and simulate, Dk is set to variable, finally obtains simulation result, interface as shown in Figure 4;
9. derive corresponding Dk value: all prepreg model one_to_one corresponding that the Dk value emulated through SI8000 is used with Design PCB, form Dk tables of data.
When adopting differential impedance line structure, more stable when its advantage is that resistance value is tested, and suffered external interference is less, but shortcoming is to take up room comparatively large, and test analysis is more complicated.Fig. 5 shows the schematic diagram adopting SI8000 impedance computation software during differential impedance line structure to carry out analog result demonstration.
The present invention can be applicable to wiring board art.
Claims (9)
1. a wiring board Dk resolution chart, on the central layer of this graphic designs in wiring board (1), described figure is made up of via (2) and impedance line (3), and described via (2) and described impedance line (3) are conducted, and it is characterized in that: described impedance line (3) is not wide impedance line.
2. a kind of wiring board Dk resolution chart according to claim 1, is characterized in that: the line width of the upper tested interval impedance line of described impedance line (3) is less than the line width in other region.
3. a kind of wiring board Dk resolution chart according to claim 2, it is characterized in that: the periphery of described tested interval impedance line is provided with some ground holes (4), the aperture of described ground hole (4) is identical with the aperture of described via (2), is 1.0 ~ 1.5mm.
4. a kind of wiring board Dk resolution chart according to claim 3, it is characterized in that: the periphery of described via (2) is provided with ground hole (4), the aperture of described ground hole (4) is identical with the aperture of described via (2), is 1.0 ~ 1.5mm.
5. a kind of wiring board Dk resolution chart according to claim 4, it is characterized in that: ground hole (4) aperture edge being positioned at described tested interval impedance line periphery is 2mm apart from tested interval impedance line Distances Between Neighboring Edge Points, the Distances Between Neighboring Edge Points being positioned at via (2) described in peripheral ground hole (4) Edge Distance of described via (2) is 3 ~ 5mm.
6. adopt wiring board Dk resolution chart as claimed in claim 1 to carry out a wiring board Dk method of testing of testing, it is characterized in that: the method comprises the following steps:
(1) based on wiring board Dk resolution chart, for the impedance line that the often kind of prepreg design comprised in wiring board to be measured is corresponding, the resistance value of described impedance line is all set as 50ohm;
(2) make the wiring board being designed with impedance line as described in step (1), described wiring board, through TDR Test, obtains the impedance measured value of wiring board middle impedance line;
(3) all corresponding with the prepreg impedance line on described wiring board is done section test, obtain the thick parameter of the live width of impedance line, thickness of dielectric layers and copper;
(4) the section test parameter obtained in impedance measured value step (2) obtained and step (3) is updated in SI8000 impedance computation software simulates, and obtains the Dk value of wiring board medium to be measured.
7. wiring board Dk method of testing according to claim 6, it is characterized in that: in described step (2), described wiring board forms by being positioned at outer field Copper Foil and some layers of prepreg and some central layers, between any two-layer central layer, by prepreg interval between Copper Foil and central layer, the one side of described central layer arranges impedance line reference layer, another side arranges impedance line, when pcb layer is folded, the described central layer of some layers is identical set-up mode, when central layer impedance line reference layer one face up time, the one side of the band impedance line reference layer of whole central layer all upward, one side with impedance line all down, when central layer impedance line reference layer one face down time, the one side of the band impedance line reference layer of whole central layer all down, band impedance line one side all upward.
8. wiring board Dk method of testing according to claim 6, is characterized in that: in described step (3), the position of section is arranged in the tested interval on the impedance line of wiring board Dk resolution chart.
9. wiring board Dk method of testing according to claim 6, is characterized in that: described impedance line is single-ended stripline line structure, can also be the banded first structure of difference.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510573318.3A CN105163483B (en) | 2015-09-10 | 2015-09-10 | A kind of wiring board Dk resolution charts and wiring board Dk test methods |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510573318.3A CN105163483B (en) | 2015-09-10 | 2015-09-10 | A kind of wiring board Dk resolution charts and wiring board Dk test methods |
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| CN105163483A true CN105163483A (en) | 2015-12-16 |
| CN105163483B CN105163483B (en) | 2018-04-20 |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107328999A (en) * | 2017-07-31 | 2017-11-07 | 深圳崇达多层线路板有限公司 | A kind of method of parameter value needed for acquisition calculates sheet material dielectric constant |
| CN107872921A (en) * | 2017-08-30 | 2018-04-03 | 奥士康精密电路（惠州）有限公司 | A kind of design method of characteristic impedance |
| CN109188101A (en) * | 2018-09-25 | 2019-01-11 | 郑州云海信息技术有限公司 | Acquisition methods, system, device and the readable storage medium storing program for executing of medium electric parameter |
| CN109275259A (en) * | 2018-09-20 | 2019-01-25 | 郑州云海信息技术有限公司 | A kind of production method of pcb board and a kind of pcb board |
| CN109451656A (en) * | 2018-11-27 | 2019-03-08 | 深圳崇达多层线路板有限公司 | A kind of impedance test board |
| CN109548268A (en) * | 2018-11-01 | 2019-03-29 | 郑州云海信息技术有限公司 | A kind of PCB impedance adjustment, control system and a kind of PCB layout plate |
| CN109581068A (en) * | 2018-11-27 | 2019-04-05 | 深圳崇达多层线路板有限公司 | A kind of effective dielectric constant assessment test method and system |
| US10674598B1 (en) | 2019-10-08 | 2020-06-02 | Cisco Technology, Inc. | Measuring effective dielectric constant using via-stub resonance |
| WO2020253289A1 (en) * | 2019-06-20 | 2020-12-24 | 深圳Tcl数字技术有限公司 | Circuit board and display device |
| CN113079622A (en) * | 2021-03-29 | 2021-07-06 | 生益电子股份有限公司 | PCB manufacturing method and PCB, and floating monitoring method of copper foil at bottom of blind hole |
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| CN109581068A (en) * | 2018-11-27 | 2019-04-05 | 深圳崇达多层线路板有限公司 | A kind of effective dielectric constant assessment test method and system |
| WO2020253289A1 (en) * | 2019-06-20 | 2020-12-24 | 深圳Tcl数字技术有限公司 | Circuit board and display device |
| US10674598B1 (en) | 2019-10-08 | 2020-06-02 | Cisco Technology, Inc. | Measuring effective dielectric constant using via-stub resonance |
| CN113079622A (en) * | 2021-03-29 | 2021-07-06 | 生益电子股份有限公司 | PCB manufacturing method and PCB, and floating monitoring method of copper foil at bottom of blind hole |
| CN113079622B (en) * | 2021-03-29 | 2022-05-24 | 生益电子股份有限公司 | PCB manufacturing method and PCB, and floating monitoring method of copper foil at bottom of blind hole |
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