CN109581068A - A kind of effective dielectric constant assessment test method and system - Google Patents
A kind of effective dielectric constant assessment test method and system Download PDFInfo
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- CN109581068A CN109581068A CN201811426983.XA CN201811426983A CN109581068A CN 109581068 A CN109581068 A CN 109581068A CN 201811426983 A CN201811426983 A CN 201811426983A CN 109581068 A CN109581068 A CN 109581068A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2617—Measuring dielectric properties, e.g. constants
- G01R27/2623—Measuring-systems or electronic circuits
Abstract
The present invention relates to dielectric constant detection technique field, specially a kind of effective dielectric constant assessment test method and system.The present invention passes through the parameters such as the impedance value of each impedance in measured impedance test board and line width, line thickness and the adjacent dielectric thickness of combined impedance, utilize impedance simulation software retrospectively calculate effective dielectric constant corresponding with the impedance, the polynomial equation for being used to calculate effective dielectric constant is obtained by effective dielectric constant and line width, with parameters progress regression analyses such as the gel contents of impedance adjacent layer again, dielectric constant detector is not necessarily to realize, you can learn that the effective dielectric constant of plate, provides convenience for production design by way of calculating.Polynomial equation constructed by the method for the present invention can satisfy the required precision of production than the effective dielectric constant of accurate computing board material.
Description
Technical field
The present invention relates to dielectric constant detection technique field more particularly to a kind of effective dielectric constant assessment test method and
System.
Background technique
Dielectric constant (DK) is that the megohmite insulant of unit of measurement volume can store electrostatic energy under per unit electric potential gradient
The physical quantity of amount.Medium have the function of under extra electric field generate charge inducing and weaken electric field, and impedance be conductor resistance,
The vector sum of induction reactance and capacitive reactance, dielectric constant have significant impact to impedance, are important parameters during PCB impedance design
One of.The DK value of core plate involved in PCB production process and prepreg (PP) is provided by supplier, can not be confirmed actual
Effective DK value can not know effective DK value of combined material for combined material if without DK measuring instrument.It is such as raw in PCB
During production, it is often necessary to which combining the PP piece (such as PP of model 1080 and model 2116) of different size makes
With it is even more impossible to confirm effective DK value of the combined material in this case.I.e. the prior art is in addition to directly using DK measuring instrument to survey
Outside the DK value for measuring material, can not confirm different plates and different size, different gel contents plate effective DK value, production is set
Meter and immediately monitoring and adjusted design scheme are extremely inconvenient.
Summary of the invention
The present invention is directed to the prior art in addition to the effective dielectric constant for using the direct sheet material measurement of DK measuring instrument, Wu Fatong
The effective dielectric constant of the mode check and evaluation plate calculated is crossed, so that the problem of being not easy to production design, provides a kind of effective
Dielectric constant assesses test method, and the system of the effective dielectric constant for assessing test plate.
To achieve the above object, the present invention uses following technical scheme.
A kind of effective dielectric constant assessment test method, comprising the following steps:
The impedance value of impedance on S1, several identical impedance test boards of detection；The pressing structure of the impedance test board
Parameter is given value, and the parameter of the pressing structure includes the gel content of each layer of prepreg in pressing structure.
Preferably, the impedance test board is to be followed successively by six pieces of core plates of C1-C6 by numbering from top to bottom, from top to bottom compiled
Number it is followed successively by the Multilayer Structure that seven floor layer of prepreg, upper copper foil layer and the lower copper foil layer of P1-P7 are constituted；The upper copper foil layer
Outer layer impedance is respectively equipped with lower copper foil layer；The one side of described core plate C1, C2, C3, C5, C6 are signal face, on the signal face
It is equipped with interior layer impedance, another side is with reference to copper face；The one side of the core plate C4 is no copper face, and another side is with reference to copper face；
It include three classes core plate of the dielectric layer gel content less than 50%, 50-70%, greater than 70% in the core plate C1-C6；The semi-solid preparation
It include three classes layer of prepreg of the gel content less than 50%, 50-70%, greater than 70% in lamella P1-P7；The layer of prepreg
In include the layer of prepreg being made of individual prepreg and the layer of prepreg that is made of two prepregs.
S2, slice analysis is done to each impedance test board, measure respectively the upper line width of impedance on impedance test board, lower line width,
Line thickness, top dielectric thickness, layer dielectric thickness.
S3, resulting data are measured according to step S1 and step S2, is calculated using impedance simulation software corresponding with each impedance
Effective dielectric constant.
Preferably, the impedance simulation software is Polar SI8000 or Polar SI9000.
S4, contain glue to the line width of effective dielectric constant obtained by step S3 and counterpart impedance, with counterpart impedance adjacent layer
Amount carries out regression analysis to fit about Y, X1、X2、X1 2、X2 2、X1X2Polynomial equation F (X)；The Y is that effective dielectric is normal
Number, X2For line width, X1For gel content, X2 2It is then square of line width, X1 2It is then square of gel content, X1X2It is then gel content and line
The product of width.
Preferably, the index of correlation R that regression analysis carries out curve fitting2≥0.85。
S5, the route that will make/drawn up work on the gel content of plate and plate line width substitute into the polynomial equation F
(X) in, the effective dielectric constant of the plate is calculated.
Preferably, simplified polynomial equation is further included the steps that after step S4, i.e., by line width X2It is set to three definite values
And substitute into polynomial equation F (X) described in step S4 respectively, respectively obtain simplified three polynomial equation F1(X)、F2
(X) and F3(X)；The F1(X) corresponding line width X2Less than 4mil, the F2(X) corresponding line width X2Greater than 4mil and it is less than
6mil, the F3(X) corresponding line width X2Greater than 6mil.
Correspondingly, in the step S5, according to the line width for the route that work has been made/drawn up on plate from F1 (X)、F2(X)
And F3(X) polynomial equation is selected in, and the gel content of plate is substituted into selected polynomial equation, the plate is calculated
Effective dielectric constant.
For example, if the line width X of the route of work having been made/having drawn up on plate2< 4mil selects polynomial equation F1(X) it calculates
The effective dielectric constant of the plate；If the line width 4mil < X of the route of work has been made/drawn up on plate2< 6mil is selected multinomial
Formula equation F2(X) effective dielectric constant of the plate is calculated；If the line width X of the route of work has been made/drawn up on plate2> 6mil,
Select polynomial equation F3(X) effective dielectric constant of the plate is calculated.
Preferably, the F1(X) corresponding line width X2For 3mil, the F2(X) corresponding line width X2For 5mil, the F3
(X) corresponding line width X2For 7mil.
Preferably, the impedance test board is characteristic impedance test board or differential impedance test board, and the characteristic impedance is surveyed
Test plate (panel) is equipped with internal layer characteristic impedance and outer layer characteristic impedance, and the differential impedance test board is equipped with internal layer differential impedance and outside
Layer differential impedance.
Correspondingly, if impedance test board described in step S1 is differential impedance test board, slice analysis described in step S2
In, it further include the line bottom spacing for measuring two lines road in internal layer differential impedance and outer layer differential impedance respectively.
Preferably, in the step S4, line width, the correspondence of effective dielectric constant and counterpart impedance to same class impedance
The gel content of impedance adjacent layer carries out regression analysis to fit polynomial equation F (X).
Preferably, on impedance test board the internal layer difference/characteristic impedance by left end internal layer that is symmetrical and linking together
Difference/characteristic impedance and right end internal layer difference/characteristic impedance are constituted；Outer layer difference/the characteristic impedance is by symmetrical and be connected to
Left end outer layer difference/characteristic impedance and right end outer layer difference/characteristic impedance together is constituted.
Preferably, in the step S1, the impedance value of each its left and right ends of impedance on impedance test board is measured, if internal layer
The absolute value of the difference of the impedance value of characteristic impedance or outer layer characteristic impedance left and right ends is greater than 1.5 Ω, then rejects the internal layer characteristic
The impedance value measurement data of impedance or outer layer characteristic impedance；If the impedance of internal layer differential impedance or outer layer differential impedance left and right ends
The absolute value of the difference of value is greater than 3 Ω, then rejects the impedance value measurement data of the internal layer differential impedance or outer layer differential impedance.
Preferably, in the step S2, each impedance test board is fabricated to two slices and carries out slice analysis, and is compared
The slice analysis data of each impedance in this two pieces slices, if there are differences to be greater than ± 10 in two slice analysis data of same impedance
μm data, then reject the slice analysis data of the impedance.
A kind of effective dielectric constant assessment test macro, the polynomial equation F (X) established including the process described above.
Compared with prior art, the beneficial effects of the present invention are:
The present invention passes through the impedance value of each impedance in measured impedance test board and line width, line thickness and the adjacent Jie of combined impedance
The parameters such as matter thickness degree using impedance simulation software retrospectively calculate effective dielectric constant corresponding with the impedance, then will effectively be situated between
The parameters such as electric constant, line width, the gel content of impedance adjacent layer carry out regression analysis and obtain for calculating the more of effective dielectric constant
Formula equation is not necessarily to dielectric constant detector to realize, you can learn that the effective dielectric constant of plate by way of calculating,
Convenience is provided for production design.Effective dielectric of the polynomial equation constructed by the method for the present invention than accurate computing board material
Constant can satisfy the required precision of production.
Detailed description of the invention
Fig. 1 is the schematic elevation view of differential impedance test board described in embodiment；
Fig. 2 is the schematic elevation view of characteristic impedance test board described in embodiment；
Fig. 3 is the tendency chart of effective the DK value and RC% under different line widths；
Fig. 4 is Y match value and X1Scatter plot；
Fig. 5 is Y match value and X2Scatter plot.
Specific embodiment
In order to more fully understand technology contents of the invention, combined with specific embodiments below to technical solution of the present invention
It is described further and illustrates.
Embodiment
The present embodiment provides a kind of effective dielectric constants to assess test method, and for assessing test effective dielectric constant
System.First prepare the impedance test board for collecting related data, then by measurement impedance test board collect impedance value and
It is anti-by impedance simulation software will then to test the data obtained for the data such as line width, line thickness, the upper and lower medium thickness degree of counterpart impedance
To calculating corresponding effective dielectric constant, followed by using calculate resulting effective dielectric constant and with line width and gel content phase
The variable of pass carries out regression analysis and makes matched curve.The plate of known gel content can be calculated when production one using matched curve
Its effective dielectric constant when the wide route of alignment.Citing that detailed process is as follows.
One, the preparation of impedance test board
Impedance test board used in effective dielectric constant assessment test method of the invention, be by number from top to bottom according to
Secondary six pieces of core plates for C1-C6, number is followed successively by seven layers of layer of prepreg, upper copper foil layer and the lower copper foil of P1-P7 from top to bottom
The Multilayer Structure that layer is constituted, the pressing structure design of impedance test board as shown in table 1 below (includes that three pieces of differential impedances are surveyed in table
The pressing structure of test plate (panel) and three pieces of characteristic impedance test boards).Upper copper foil layer (L1) and lower copper foil layer (L14) are respectively equipped with outer layer spy
Property impedance or outer layer differential impedance；The one side (L3, L5, L7, L10, L12) of core plate C1, C2, C3, C5, C6 are signal face, described
Internal layer characteristic impedance or internal layer differential impedance are equipped on signal face, another side (L2, L4, L6, L11, L13) is with reference to copper
Face；The one side (L8) of core plate C4 is no copper face, and as empty space, another side (L9) is with reference to copper face.
Residual copper ratio with reference to copper face is 70%, and the residual copper ratio of signal face is 50%.(by PCB produce in exposure, aobvious
Shadow, etch process retain part copper face in reference copper face and signal face so that the layer not Shang copper face coverage rate reach design requirement,
Copper face coverage rate is residual copper ratio.)
Dielectric layer gel content in core plate C1 and C6 is 70%；Dielectric layer gel content in core plate C2 and C5 is
55%；Dielectric layer gel content in core plate C3 and C4 is 45%.(the other J1-J6 in 1 middle layer of table, which is respectively corresponded, indicates core plate C1-C6
In dielectric layer.)
The gel content of layer of prepreg P1 and P7 are 70%；The gel content of layer of prepreg P2 and P6 are 70%；Half
The gel content for solidifying lamella P3 and P5 is 55%；The gel content of layer of prepreg P4 is 45%.
Layer of prepreg P2 and P6 is made of two prepregs.
The line width of outer layer characteristic impedance and the internal layer characteristic impedance of characteristic impedance test board 1-3 is as shown in table 1；Difference resistance
The line width of the outer layer differential impedance of the anti-test board 1-3 and internal layer differential impedance (line of differential testing plate in table 1 as shown in table 1
Wide " 3/4/3 " refers to that the line width of two copper wire is 3mil, and the line bottom spacing of two copper wire is 4mil).
Differential impedance test board is (copper face for controlling residual copper ratio being not shown in Fig. 1, be commonly called as " false copper ") as shown in Figure 1,
The left and right ends of differential impedance test board are respectively equipped with two rows of telltale holes, and each telltale hole is hindered with the difference on a signal face respectively
Anti- copper wire connection (length of copper wire is greater than or equal to 6in), the differential impedance on each signal face include two copper wire, and every
The left and right ends of copper wire are connect with a telltale hole respectively, constitute left end differential impedance and right end difference symmetrical and link together
Impedance；It is located at the difference of outer layer and internal layer according to differential impedance, difference is known as respectively: outer layer differential impedance, left end outer layer difference
Impedance, right end outer layer differential impedance, internal layer differential impedance, left end internal layer differential impedance, right end internal layer differential impedance.Because internal layer is poor
The inside for dividing the copper wire of impedance to be located at pressing structure, therefore the front view of differential impedance test board shown in FIG. 1 can only see phase
The telltale hole for answering internal layer differential impedance can't see the copper wire of internal layer differential impedance.
Characteristic impedance test board is (copper face for controlling residual copper ratio being not shown in Fig. 2, be commonly called as " false copper ") as shown in Figure 2,
The left and right ends of characteristic impedance test board are respectively equipped with a row signal hole and a hole row GND.Every GND Kong Yuyi signal face phase
With reference to copper face connection, (hole GND " L2&4 ", the hole GND are connect adjacent two with reference to copper face L2 and L4 in such as Fig. 2, are located at L2 and L4
Between L3 layer be signal face, measure be located on L3 layer internal layer characteristic impedance impedance value when with indicate " L3 " telltale hole and mark
Show that the hole GND of " L2&4 " measures).Each telltale hole connect (copper wire with the copper wire of the characteristic impedance on a signal face respectively
Length be greater than or equal to 6in), the characteristic impedance on each signal face includes a copper wire, the left and right ends of copper wire respectively with
The connection of one telltale hole constitutes left end characteristic impedance and right end characteristic impedance symmetrical and link together；According to characteristic impedance position
In the difference of outer layer and internal layer, difference is known as respectively: outer layer characteristic impedance, left end outer layer characteristic impedance, the resistance of right end outer layer characteristic
Anti-, internal layer characteristic impedance, left end internal layer characteristic impedance, right end internal layer characteristic impedance.Because the copper wire of internal layer characteristic impedance is located at pressure
The inside of structure is closed, therefore the front view of characteristic impedance test board shown in Fig. 2 can only see the letter of corresponding internal layer characteristic impedance
Number hole and the corresponding hole GND, can't see the copper wire of internal layer characteristic impedance.
The pressing structure information of 1 impedance test board of table
In table 1,106,2166,7628 refer to the model of the dielectric layer of prepreg or core plate be respectively 106,2166,
7628；" 106 × 2 " refer to that this layer is not made of the prepreg of two models 106 or dielectric layer.
In addition to the impedance test board of the laminar structure shown in the upper table 1, by changing the layer structure of P1 and P7, it is changed to by 106 × 2
2116, the gel content of layer of prepreg P1 and P7 are 55%, make the impedance test board of other 6 kinds of laminar structures；Again by P1
7628 are changed to by 106 × 2 with the layer structure of P7, the gel content of layer of prepreg P1 and P7 are 45%, then make other 6 kinds of layers
The impedance test board of laminated structure.
It include three classes core plate of the dielectric layer gel content less than 50%, 50-70%, greater than 70% by setting pressing structure,
And three classes layer of prepreg of the gel content less than 50%, 50-70%, greater than 70%, and in layer of prepreg include individual half
The impedance test board of cured sheets and two prepregs, by measuring the impedance value of impedance thereon and doing slice analysis to it to receive
Collect the slice analysis data such as line width, line thickness, line-spacing, thickness of dielectric layers, then these data are handled in certain method, it can
The accurately relationship between reflection line width and plate gel content and effective dielectric constant is exploitation building for used in production PCB
The accurate feasible effective dielectric constant appraisal procedure and system of plate provide the accurate material conditions for collecting related data.Resistance
Inside/outside layer impedance is by the symmetrical and left end inside/outside layer impedance to link together and right end inside/outside layer impedance structure on anti-test board
At one piece of impedance test board can get two groups of measurement data, and the difference by comparing this two groups of measurement data can rejecting abnormalities resistance
The measurement data of anti-test board, so as to further ensure the accuracy of data acquisition.(interior layer impedance includes internal layer characteristic impedance
With internal layer differential impedance, outer layer impedance includes outer layer characteristic impedance and outer layer differential impedance, and layer impedance includes in left end in left end
Layer characteristic impedance and left end internal layer differential impedance, layer impedance includes the characteristic impedance of right end internal layer and the resistance of right end internal layer difference in right end
Anti-, layer impedance includes left end outer layer characteristic impedance and left end outer layer differential impedance outside left end, and the outer layer impedance of right end includes outside right end
Layer characteristic impedance and right end outer layer differential impedance.)
In the present embodiment, the impedance test board of each laminar structure makes 24 pieces respectively.
Impedance test board first makes resistance with negative film technique using existing conventional PCB production technology production on each core plate
Then anti-and false copper by corresponding prepreg, core plate lamination and is pressed into multilayer production plate according to the laminar structure of design, connects
Outer layer drilling, heavy copper, electric plating of whole board, positive blade technolgy are successively carried out to multilayer production plate copper foil production impedance add over/under
Work process completes the preparation of impedance test board followed by molding procedure is carried out.It can also continue after copper foil production impedance over/under
Solder mask is made on surface, carries out molding procedure again after completing the production of solder mask.
Two, the impedance value of impedance on impedance test board is measured
Use the resistance of each impedance in each impedance test board prepared in Agilent impedance analyzer measurement above-mentioned steps one
Anti- value, testing impedance need to be measured for the both ends of impedance, i.e., measure the left end differential impedance of differential impedance test board respectively
With right end differential impedance, the left end characteristic impedance and right end characteristic impedance of characteristic impedance test board are measured respectively, and record data,
Retain 2 significant digits.Calculate the average impedance values (impedance value of left end characteristic impedance and right end characteristic impedance of each impedance
Average value, the average value of the impedance value of left end differential impedance and right end differential impedance).
It needs first to do the calibration of air stick/standard component to Agilent impedance analyzer before measurement impedance.
If the absolute value of the difference of the impedance value of internal layer characteristic impedance or outer layer characteristic impedance left and right ends is greater than 1.5 Ω,
Reject the impedance value measurement data of the internal layer characteristic impedance or outer layer characteristic impedance；If internal layer differential impedance or outer layer differential impedance
The absolute value of the difference of the impedance value of left and right ends is greater than 3 Ω, then rejects the impedance of the internal layer differential impedance or outer layer differential impedance
It is worth measurement data.For example, the measurement situation of the impedance value of each impedance is such as in characteristic impedance test board 1 and differential impedance test board 2
Shown in the following table 2 and table 3, table 2 is the impedance value (measured value) of each impedance in characteristic impedance test board 1, and table 3 is differential impedance survey
The impedance value (measured value) of each impedance in test plate (panel) 2.
Table 2
Table 3
Three, slice analysis
Every piece of impedance test board is respectively that sampling is sliced at (from left to right) 1/3,2/3 in length, is sliced to two
Analysis, and compare the slice analysis data of each impedance in this two pieces slices, if existing in two slice analysis data of same impedance
Difference is greater than ± 10 μm of data, then rejects the slice analysis data of the impedance.
Characteristic impedance test board need to measure the copper wire of outer layer characteristic impedance and internal layer characteristic impedance upper line width/line top W2,
Lower line width/line bottom W1, line thickness/copper thickness T, layer dielectric are thick/lower thickness H1, the top dielectric of being situated between is thick/, and be above situated between thickness H2, totally 5 data；Difference
The upper line width for being divided to impedance test board that need to measure two copper wire of outer layer differential impedance and internal layer differential impedance/line top (W2, W4), under
Thick/upper thickness that is situated between of thick/lower Jie of line width/line bottom (W1, W3), line thickness/copper thick (T1, T2), layer dielectric thick (H1, H3), top dielectric
The line bottom interval S of (H2, H4) and two copper wire, totally 11 data.Gained slice analysis data and impedance value correspond, and keep away
Exempt from confusion.There are two slice, the corresponding data of two slices to be averaged for every piece of impedance test board.
For example, two pieces of differential impedance test boards 2 (the L3 layer of outer layer differential impedance and plate B-2 on the L1 layer of plate A-2
Internal layer differential impedance) measurement data it is as shown in table 4 below.
Table 4
Four, data preparation
Calculate and summarize the average impedance values and slice analysis number of each impedance in the impedance test board of each pressing structure
According to average value.Such as the average impedance values of the internal layer differential impedance in 11 pieces of differential impedance test boards 1 in third layer (L3) and
The average value of slice analysis data is as shown in table 5.
Table 5
Five, retrospectively calculate effective dielectric constant DK value
Using impedance simulation software (Polar SI8000 or Polar SI9000), the average value that step 4 is aggregated
Data substitute into the computation model of software, inversely calculate corresponding effective dielectric constant DK value.
For example, characteristic impedance test board 1, characteristic impedance test board 2, characteristic impedance test board 3, inversely calculate resulting each
The effective dielectric constant DK value of internal layer characteristic impedance and line thickness corresponding with impedance, line width, adjacent dielectric gel content data are such as
Shown in table 6.
Table 6
Six, linear regression analysis
To the line width of the resulting effective dielectric constant of step 5 retrospectively calculate and counterpart impedance, counterpart impedance adjacent layer
Gel content carries out regression analysis to fit about Y, X1、X2、X1 2、X2 2、X1X2Polynomial equation F (X)；The Y is effectively to be situated between
Electric constant, X2For line width, X1For gel content, X2 2It is then square of line width, X1 2It is then square of gel content, X1X2It is then gel content
With the product of line width.And by index of correlation R2>=0.85 is used as the believable criterion of fitting result.
By taking characteristic impedance test board 1, characteristic impedance test board 2, characteristic impedance test board 3 as an example, inversely calculate resulting
The effective dielectric constant DK value Y of each internal layer characteristic impedance and with corresponding X1、X2、 X1 2、X2 2、X1X2Data it is as shown in table 7 below.
Table 7
Data in table 7 are subjected to linear regression analysis, obtain (retaining about the polynomial equation F (X) of the effective DK value of plate
Three after decimal point):
Y=12.571-24.162X1-0.108X2+17.972X1 2+0.010X2 2-0.133X1*X2
The R that regression calculation obtains2=0.989, it is greater than 0.85, determines that the polynomial equation is credible.
Seven, the assessment test of plate effective dielectric constant
The line width for having made/having drawn up the route of work in the plate gel content and plate of quasi- test is collected, by gel content and line
Width substitutes into above-mentioned polynomial equation F (X), and Y value i.e. effective dielectric constant is calculated.
In other embodiments, also polynomial equation described in above-mentioned steps six can be carried out simplifying processing.At simplifying
Reason method is as follows:
By different gel content (RC%) X1With line width X2Tendency chart is substituted into above-mentioned polynomial equation and drawn, and is divided
It Hui Zhi not Y match value and X1、X2Scatterplot relational graph.It is respectively that 3mil, 4mil, 5mil, 6mil, 7mil, 8mil are with line width
Line width is substituted into above-mentioned polynomial equation according to 3mil, 4mil, 5mil, 6mil, 7mil, 8mil respectively, is obtained not collinear by example
The tendency chart of effective DK value and RC% under wide, as shown in figure 3, Y match value and X1Scatter plot as shown in figure 4, Y match value with
X2Scatter plot it is as shown in Figure 5.
From the tendency chart of effective DK value and RC% it is found that as line width increases, influence of the line width to effective DK value gradually subtracts
Small, the variation tendency of six curves is consistent.About 0.3-0.5 Ω is changed because DK value changes 0.1 respective impedance value, to the shadow of impedance value
Sound is small, so the factor in formula to DK value biggest impact no more than 0.1 is contemplated that classification merges, it, can be executed convenient for simplifying
Curve is drawn by line width range L T.LT.LT 4mil, 4-6mil, > 6mil.Divided according to line width range L T.LT.LT 4mil, 4-6mil, > 6mil
Class, respectively by X2=7mil, 5mil, 3mil substitutes into above-mentioned polynomial equation, is then combined with similar terms, the side after being simplified
Journey:
F1(X): line width < 4mil, X2=3mil, DK=12.337-24.561X1+17.972X1 2
F2(X): line width 4-6mil, X2=5mil, DK=12.281-24.827X1+17.972X1 2
F3(X): line width > 6mil, X2=7mil, DK=12.305-25.093X1+17.972X1 2
Different gel content RC% values is substituted into above-mentioned formula and calculates corresponding effective dielectric constant, can tentatively establish plate
Effective DK Value Data library of material.
For example, if the line width X of the route of work having been made/having drawn up on plate2< 4mil selects polynomial equation F1(X) it calculates
The effective dielectric constant of the plate；If the line width 4mil < X of the route of work has been made/drawn up on plate2< 6mil is selected multinomial
Formula equation F2(X) effective dielectric constant of the plate is calculated；If the line width X of the route of work has been made/drawn up on plate2> 6mil,
Select polynomial equation F3(X) effective dielectric constant of the plate is calculated.
As shown in table 8, be different gel contents plate it is (interior by the resulting effective dielectric constant DK value of above-mentioned equation calculation
Layer characteristic impedance).
Table 8
Construct respectively according to the method described above about internal layer differential impedance, outer layer characteristic impedance, outer layer differential impedance it is effective
Dielectric constant polynomial equation, it is resulting about the effective DK value of plate each polynomial equation (simplified polynomial equation,
Simplified way is identical as the mode of polynomial equation of above-mentioned simplified internal layer characteristic impedance) as follows:
Polynomial equation (the X of internal layer differential impedance1=RC):
Line width > 6mil, DK=6.316-6.678X1+3.930*X1 2
Line width 4-6mil, DK=5.986-6.242X1+3.930*X1 2
Line width < 4mil, DK=5.655-5.805X1+3.930*X1 2
Polynomial equation (the X of outer layer characteristic impedance1=RC):
Line width > 6mil, DK=13.068-25.540*X1+18.520*X1 2
Line width 4-6mil, DK=13.242-25.540*X1+18.520*X1 2
Line width 3 < 4mil, DK=13.416-25.540*X1+18.520*X1 2
Polynomial equation (the X of outer layer differential impedance1=RC):
Line width > 6mil, DK=4.76044-1.2942X1
Line width 4-6mil, DK=4.21-0.551X1
Line width < 4mil, DK=3.56404+0.1922X1
Using above-mentioned resulting each polynomial equation about the effective DK value of plate, by taking IT180ABS plate as an example, building
Effective DK Value Data library of IT180ABS plate, as shown in table 9 below.The DK value of plate supplier offer is be provided in table 9,
Resulting effective DK value is calculated by the polynomial equation about the effective DK value of plate of the method for the present invention building and supplier provides
DK value compare, it is seen that collecting related data using the impedance test board developed of the present invention can guarantee the accuracy and effectively of data
Property, then the polynomial equation about the effective DK value of plate of the data processing method building can accurately have through the invention again
Effective DK value of the calculating plate of effect, precision can meet the required precision of production design.
Table 9
The Polynomial equations about the effective DK value of plate constructed by the above method build up to be used for sheet material measurement effective
The system of dielectric constant can also substitute into different gel contents in each polynomial equation, be ready in advance with plate containing glue
Corresponding effective dielectric constant is measured, data as shown in table 9 are led in design process easy to produce as a part of the system
The gel content for crossing plate directly inquires corresponding effective dielectric constant.
It is described above that technology contents of the invention are only further illustrated with embodiment, in order to which reader is easier to understand,
But embodiments of the present invention are not represented and are only limitted to this, any technology done according to the present invention extends or recreation, is sent out by this
Bright protection.
Claims (10)
1. a kind of effective dielectric constant assesses test method, which comprises the following steps:
The impedance value of impedance on S1, several identical impedance test boards of detection；The parameter of the pressing structure of the impedance test board
It is given value, the parameter of the pressing structure includes the gel content of each layer of prepreg in pressing structure；
S2, slice analysis is done to each impedance test board, measure respectively the upper line width of impedance, lower line width, line on impedance test board it is thick,
Top dielectric thickness, layer dielectric thickness；
S3, resulting data are measured according to step S1 and step S2, had using the calculating of impedance simulation software is corresponding with each impedance
Imitate dielectric constant；
S4, the line width of effective dielectric constant obtained by step S3, counterpart impedance and the gel content of counterpart impedance adjacent layer are returned
Return analysis to fit about Y, X1、X2、X1 2、X2 2、X1X2Polynomial equation F (X)；The Y is effective dielectric constant, X2For
Line width, X1For gel content, X2 2It is then square of line width, X1 2It is then square of gel content, X1X2It is then the product of gel content and line width；
S5, the route that will make/drawn up work on the gel content of plate and plate line width substitute into the polynomial equation F (X)
In, the effective dielectric constant of the plate is calculated.
2. effective dielectric constant according to claim 1 assesses test method, which is characterized in that further include letter after step S4
The step of changing polynomial equation, i.e., by line width X2It is set to three definite values and substitutes into polynomial equation described in step S4 respectively
In F (X), simplified three polynomial equation F are respectively obtained1(X)、F2(X) and F3(X)；The F1(X) corresponding line width X2It is small
In 4mil, the F2(X) corresponding line width X2Greater than 4mil and it is less than 6mil, the F3(X) corresponding line width X1Greater than 6mil；
In the step S5, according to the line width for the route that work has been made/drawn up on plate from F1(X)、F2(X) and F3(X) selection in
Polynomial equation substitutes into the gel content of plate in selected polynomial equation, and effective dielectric that the plate is calculated is normal
Number.
3. effective dielectric constant according to claim 2 assesses test method, which is characterized in that the F1(X) corresponding line
Wide X2For 3mil, the F2(X) corresponding line width X2For 5mil, the F3(X) corresponding line width X1For 7mil.
4. effective dielectric constant according to claim 1 assesses test method, which is characterized in that in step S4, return and divide
Analyse the index of correlation R to carry out curve fitting2≥0.85。
5. effective dielectric constant according to claim 1 assesses test method, which is characterized in that the impedance simulation software
It is Polar SI8000 or Polar SI9000.
6. effective dielectric constant according to claim 1-5 assesses test method, which is characterized in that the impedance
Test board be characteristic impedance test board or differential impedance test board, the characteristic impedance test board be equipped with internal layer characteristic impedance and
Outer layer characteristic impedance, the differential impedance test board are equipped with internal layer differential impedance and outer layer differential impedance.
7. effective dielectric constant according to claim 6 assesses test method, which is characterized in that in step S1, the resistance
Anti- test board is differential impedance test board；In slice analysis described in step S2, further include respectively measurement internal layer differential impedance and
The line bottom spacing on two lines road in outer layer differential impedance.
8. effective dielectric constant according to claim 7 assesses test method, which is characterized in that right in the step S4
The effective dielectric constant of same class impedance and the line width of counterpart impedance and the gel content of counterpart impedance adjacent layer return and divide
Analysis is to fit polynomial equation F (X).
9. effective dielectric constant according to claim 6 assesses test method, which is characterized in that the internal layer difference/spy
Property impedance be made of left end internal layer difference/characteristic impedance and right end internal layer difference/characteristic impedance symmetrical and link together；Institute
Outer layer difference/characteristic impedance is stated by the symmetrical and left end outer layer difference/characteristic impedance to link together and right end outer layer difference/spy
Property impedance constitute；
In the step S1, measure impedance test board on each its left and right ends of impedance impedance value, if internal layer characteristic impedance or
The absolute value of the difference of the impedance value of outer layer characteristic impedance left and right ends is greater than 1.5 Ω, then rejects the internal layer characteristic impedance or outer layer
The impedance value measurement data of characteristic impedance；If the difference of internal layer differential impedance or the impedance value of outer layer differential impedance left and right ends is exhausted
3 Ω are greater than to value, then reject the impedance value measurement data of the internal layer differential impedance or outer layer differential impedance；
In the step S2, each impedance test board is fabricated to two slices and carries out slice analysis, and compares this two pieces slices
In each impedance slice analysis data, if there are differences to be greater than ± 10 μm of data in two slice analysis data of same impedance,
Then reject the slice analysis data of the impedance.
10. a kind of effective dielectric constant assesses test macro, which is characterized in that including described in any item by claim 1-9
The polynomial equation F (X) that method is established.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110516199A (en) * | 2019-08-26 | 2019-11-29 | 广州兴森快捷电路科技有限公司 | To the disturbance degree calculation method and wiring board of the influence factor of characteristic impedance |
| CN113033140A (en) * | 2021-03-02 | 2021-06-25 | 深圳市一博科技股份有限公司 | Simulation method for accurately obtaining difference of dielectric constants of upper layer and lower layer of PCB (printed Circuit Board) wiring |
| CN114076886A (en) * | 2020-08-20 | 2022-02-22 | 深南电路股份有限公司 | Establishing method for correcting PCB dielectric constant model, correcting method and correcting system |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050230619A1 (en) * | 2004-04-09 | 2005-10-20 | Talanov Vladimir V | Method and system for measurement of dielectric constant of thin films using a near field microwave probe |
| CN101634672A (en) * | 2009-07-10 | 2010-01-27 | 中国电子科技集团公司第五十五研究所 | Micro-wave on-wafer testing method based on unknown material substrate |
| CN102034724A (en) * | 2009-09-29 | 2011-04-27 | 中芯国际集成电路制造(上海)有限公司 | Method for determining dielectric constant value of fluoride silicon glass in actual process |
| CN105137199A (en) * | 2015-09-16 | 2015-12-09 | 北京工商大学 | Network analyzer-based dielectric constant measuring method |
| CN105163483A (en) * | 2015-09-10 | 2015-12-16 | 珠海城市职业技术学院 | Circuit board Dk testing pattern and circuit board Dk testing method |
| CN107328999A (en) * | 2017-07-31 | 2017-11-07 | 深圳崇达多层线路板有限公司 | A kind of method of parameter value needed for acquisition calculates sheet material dielectric constant |
-
2018
- 2018-11-27 CN CN201811426983.XA patent/CN109581068B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050230619A1 (en) * | 2004-04-09 | 2005-10-20 | Talanov Vladimir V | Method and system for measurement of dielectric constant of thin films using a near field microwave probe |
| CN101634672A (en) * | 2009-07-10 | 2010-01-27 | 中国电子科技集团公司第五十五研究所 | Micro-wave on-wafer testing method based on unknown material substrate |
| CN102034724A (en) * | 2009-09-29 | 2011-04-27 | 中芯国际集成电路制造(上海)有限公司 | Method for determining dielectric constant value of fluoride silicon glass in actual process |
| CN105163483A (en) * | 2015-09-10 | 2015-12-16 | 珠海城市职业技术学院 | Circuit board Dk testing pattern and circuit board Dk testing method |
| CN105137199A (en) * | 2015-09-16 | 2015-12-09 | 北京工商大学 | Network analyzer-based dielectric constant measuring method |
| CN107328999A (en) * | 2017-07-31 | 2017-11-07 | 深圳崇达多层线路板有限公司 | A kind of method of parameter value needed for acquisition calculates sheet material dielectric constant |
Non-Patent Citations (4)
| Title |
|---|
| YI-LUNG CHENG: "Comparison of O2 plasma treatment on porous low dielectric constant material at sidewall and bottom of trench structure", 《THIN SOLID FILMS》 * |
| 刘春乐: "磁化铁氧体电磁参数的测试", 《电子测量技术》 * |
| 王红飞: "含胶量对介质厚度均匀性及阻抗控制的影响", 《2012秋季国际PCB技术》 * |
| 范红: "PCB板材介电常数的测量方法及其应用", 《2014秋季国际PCB技术》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110516199A (en) * | 2019-08-26 | 2019-11-29 | 广州兴森快捷电路科技有限公司 | To the disturbance degree calculation method and wiring board of the influence factor of characteristic impedance |
| CN114076886A (en) * | 2020-08-20 | 2022-02-22 | 深南电路股份有限公司 | Establishing method for correcting PCB dielectric constant model, correcting method and correcting system |
| CN113033140A (en) * | 2021-03-02 | 2021-06-25 | 深圳市一博科技股份有限公司 | Simulation method for accurately obtaining difference of dielectric constants of upper layer and lower layer of PCB (printed Circuit Board) wiring |
| CN113033140B (en) * | 2021-03-02 | 2023-12-29 | 深圳市一博科技股份有限公司 | Simulation method for accurately obtaining dielectric constant difference of upper and lower layers of PCB wiring |
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