CN114501823B

CN114501823B - PCB lamination optimization method and PCB

Info

Publication number: CN114501823B
Application number: CN202210392266.XA
Authority: CN
Inventors: 任伟鹏; 魏波
Original assignee: Chengdu Wanchuang Technology Co ltd
Current assignee: Chengdu Wanchuang Technology Co ltd
Priority date: 2022-04-15
Filing date: 2022-04-15
Publication date: 2022-07-01
Anticipated expiration: 2042-04-15
Also published as: CN114501823A

Abstract

The invention relates to the technical field of PCBs, in particular to a PCB lamination optimization method and a PCB. The method provided by the invention is suitable for the resistance laminated design of all multilayer boards, and the method for reducing the residual copper rate of the signal reference layer by arranging the hollowed area on the reference layer is used for reducing the dielectric thickness between the signal layer and the reference layer, so that the aim of controlling the resistance and the resistance line width parameter is indirectly fulfilled. The problem that the thickness of a medium between a signal layer and a reference layer of the signal layer can not be reduced any more when the semi-curing type reaches the thinnest limit in the traditional PCB impedance lamination design is solved, the workload of PCB design is further reduced, the PCB design efficiency is finally improved, and the project period is shortened.

Description

PCB lamination optimization method and PCB

Technical Field

The invention relates to the technical field of Printed Circuit Boards (PCBs), in particular to a PCB lamination optimization method and a PCB.

Background

With the rapid development of the electronic industry, the chip package is smaller and smaller, the layout and wiring density of the PCB is higher and higher, and the problem and defect that the conventional method (such as directly using the lamination provided by the PCB manufacturer, or improving the relevant parameters on the basis of the lamination provided by the PCB manufacturer to obtain the lamination impedance suitable for the product requirement) exposes in the current high-speed PCB design are increasingly obvious.

Although the method reduces the thickness of the medium, the purpose of reducing the line width is finally realized under the condition that the impedance is qualified; however, if the dielectric thickness is reduced to the minimum, i.e. the PCB manufacturer has selected the thinnest type of prepreg that can be provided, the line width still needs to be reduced, and the copper thickness needs to be reduced continuously because the product needs no improvement space, and the conventional method cannot be used to solve this situation, which is a problem frequently occurring in practical applications.

The industry has two approaches to this problem, and neither approach is ideal.

The method comprises the following steps: accepting the condition that the line width can not be reduced, agreeing to the board factory to increase the originally designed line width to ensure that the impedance is qualified, because the impedance is up to the limit of the current process. Due to the processing mode, the line width is increased, so that the space between high-speed signals in the original design is reduced, the crosstalk between the signals is increased, the signal integrity problem is generated, and the risk is brought to the product. Meanwhile, the increase of the line width leads to the reduction of the line spacing and is closer to the process limit, thus leading to the increase of the manufacturing difficulty and the increase of the rejection rate of the PCB etching process.

The method II comprises the following steps: the line width of the original design is kept not to be increased, but the requirement of impedance relaxation is passively accepted, namely the accepted impedance is increased compared with the impedance of the design requirement, and the high-speed signal is reflected at the position with discontinuous impedance, so that the distortion of the signal in the transmission process can be caused, and the hidden danger and the risk are increased for the product performance.

Therefore, the invention provides a brand-new method for optimizing the PCB lamination of the existing design scheme and a corresponding optimized PCB.

Disclosure of Invention

The invention aims to solve the problem that the impedance line width parameter cannot be further controlled after a prepreg reaches the thinnest limit in the PCB design stage in the prior art, and provides a PCB lamination optimization method and a PCB.

In order to achieve the above purpose, the invention provides the following technical scheme:

a PCB lamination optimization method comprises the following steps:

s1: acquiring an impedance line width parameter of the ith layer of the PCB in the existing design scheme; i belongs to [1, n ], n is an even number more than 3;

s2: calculating the residual copper rate of a reference layer of the ith layer of the PCB according to the impedance line width parameters, calculating a hollowed area of the reference layer according to the residual copper rate, and outputting the hollowed area as an optimization scheme of the reference layer; the reference layer is a reference plane layer corresponding to a signal line which needs to control impedance when PCB impedance design is carried out, and the distance (namely medium thickness) between the impedance signal line and the reference plane is an important parameter which influences the impedance value of the signal;

s3: judging whether all the laminated layers of the PCB are calculated or not; if so, outputting the optimization scheme of the PCB lamination, otherwise, i = i +1, and proceeding to step S1. The method provided by the invention is suitable for the resistance laminated design of all multilayer boards (more than or equal to 4 layers), and the method for reducing the residual copper rate of the signal reference layer by arranging the hollowed area on the reference layer is utilized to reduce the thickness of the medium between the signal layer and the reference layer, so that the aim of controlling the resistance and the resistance line width parameters is indirectly realized. The problem that the thickness of a medium between a signal layer and a reference layer of the signal layer can not be reduced any more when the semi-curing type reaches the thinnest limit in the traditional PCB impedance lamination design is solved. Meanwhile, the optimization method of the invention can allow the influence of the residual copper rate on the impedance parameter to be considered in the design stage of the PCB, thereby carrying out related pre-planning or improvement in advance; on the other hand, the residual copper rate can be directly utilized to control impedance parameters, so that the workload of PCB design is reduced, the PCB design efficiency is finally improved, and the project period is shortened.

As a preferable embodiment of the present invention, the step S2 includes:

s21: acquiring the residual copper rate of a corresponding reference layer in a preset reference PCB, and marking as a; the preset reference PCB is a pre-selected PCB template;

s22: obtaining the residual copper rate of the reference layer of the PCB in the design scheme, and recording the residual copper rate as b;

s23: calculating a residual copper rate difference d, d = b-a;

if d is less than 0, the process is not performed, and the process proceeds to step S3;

and if d is larger than 0, calculating the hollowed area of the copper sheet of the reference layer according to the value of d.

As a preferable aspect of the present invention, the hollowed-out region needs to avoid the line position and the device position of the adjacent stacked layers.

As a preferable scheme of the invention, the hollowed thickness of the hollowed area is a preset value, wherein the preset value is greater than 0 and is less than or equal to the thickness of the copper sheet of the reference layer.

As a preferable aspect of the present invention, the area of the hollowed-out region = d × the area of the PCB.

A PCB is characterized in that the lamination of the PCB is optimized in layout by adopting the optimization method.

Compared with the prior art, the invention has the beneficial effects that:

the method provided by the invention is suitable for the resistance laminated design of all multilayer boards (more than or equal to 4 layers), and the method for reducing the residual copper rate of the signal reference layer by arranging the hollowed area on the reference layer is utilized to reduce the thickness of the medium between the signal layer and the reference layer, so that the aim of controlling the resistance and the resistance line width parameters is indirectly realized. The problem that the thickness of a medium between a signal layer and a reference layer of the signal layer can not be reduced any more when the semi-curing type reaches the thinnest limit in the traditional PCB impedance lamination design is solved. Meanwhile, by adopting the optimization method, on one hand, the influence of the residual copper rate on the impedance parameter can be considered in the design stage (namely the stage before the final design is finished, including the preliminary design scheme and the optimization method of the invention) of the PCB, so that the related plan is carried out or improved in advance; on the other hand, the residual copper rate can be directly utilized to control impedance parameters, so that the workload of PCB design is reduced, the PCB design efficiency is finally improved, and the project period is shortened.

Drawings

FIG. 1 is a schematic illustration of a single-sided underfill of the type described herein;

FIG. 2 is a schematic illustration of a double-sided underfill of the present invention;

fig. 3 is a schematic flow chart of a method for optimizing a PCB stack according to embodiment 1 of the present invention;

fig. 4 is a diagram of a 6-layer board lamination in the method for optimizing the lamination of the PCB board according to embodiment 2 of the present invention;

fig. 5 is a schematic flow chart of a method for reducing the residual copper rate in the PCB stack optimization method according to embodiment 2 of the present invention.

Detailed Description

The present invention will be described in further detail with reference to test examples and specific embodiments. It should be understood that the scope of the above-described subject matter is not limited to the following examples, and any techniques implemented based on the disclosure of the present invention are within the scope of the present invention.

In the process of designing the PCB, the PCB lamination needs to be designed firstly, and the result of the PCB lamination design directly determines the impedance line width in the PCB wiring stage.

1. PCB manufacturing process flow (taking 6 layers as an example):

(1) inner layer (L2, L3, L4, L5): cutting board → inner layer dry film (negative film) → inner layer etching → inner layer AOI → pressing board → X-RAY drilling. At this time, the inner layer circuit is completed, and then the outer layer circuit is manufactured.

(2) Outer layer (L1, L6): laser drilling (a special process in the case of HDI boards) → mechanical drilling → chemical copper deposition → whole board electroplating → outer layer dry film (positive sheet) → pattern electroplating → outer layer etching → outer layer AOI → green oil → silk screen printing → surface treatment → contour machining → electrical measurement → visual inspection → packaging → shipment.

The above (1) and (2) briefly describe the whole process for manufacturing the 6-layer PCB, and the PCB with other layers only reduces the processes (for example, the 2-layer PCB has no pressing process) or repeats the processes (for example, 8 layers, 10 layers and more, and the like, and only carries out multiple electroplating, etching and pressing in the inner layer process of the above processes).

2. In the above PCB production process, the processes mainly affecting the PCB impedance are:

(1) an etching process: line width and line spacing;

(2) a plate pressing procedure: the thickness of the medium and the dielectric constant of the used plate;

(3) electroplating process: copper thickness;

(4) a green oil procedure: green oil thickness;

at present, the characteristic impedance calculation method of the PCB signal line is mature, and the factors influencing the impedance mainly comprise 6:

line width; secondly, line spacing; ③ the thickness of the medium; dielectric constant; thick copper; sixthly, the thickness of the green oil.

Wherein, when the thickness of the medium and the line distance are increased, the impedance is increased; the line width, copper thickness, dielectric constant and green thickness increase, the impedance decreases (verified using impedance calculation software such as SI 9000).

3. At present, there are two methods for designing the laminated impedance of the PCB in the industry:

(1) the method comprises the following steps: the laminates provided by the PCB board factory are used directly.

PCB design engineer, with PCB file design completion back, can send PCB board factory to process, under this kind of condition, in order to improve design efficiency and avoid the file after PCB design completion to surpass the PCB preparation technological capability and cause the unable condition of processing of PCB, generally in PCB design process, the technological capability of PCB board factory needs to be known, let the board factory provide the impedance laminated structure that satisfies its technological capability that its conventional each layer board corresponds simultaneously, when doing PCB design like this, just can directly choose for use the laminated structure who accords with the design demand can.

(2) The second method comprises the following steps: related parameters are improved on the basis of the lamination provided by a PCB factory to obtain the lamination impedance suitable for the requirement of the product.

The method improves parameters which influence the impedance laminated structure, such as laminated line width, line distance, medium thickness, copper thickness and the like provided by a PCB factory, and finally obtains the PCB impedance laminated layer which is suitable for the requirement of the PCB product. The adjustment method of the dielectric thickness is currently generally implemented by selecting different types of semi-curing types and core boards. For example, in pcb design, the 50 ohm impedance line width at a single end of a surface layer in an existing lamination provided by a board factory needs to be thinned, a conventional method is realized by reducing the thickness of a medium between a signal layer and a reference layer (generally, the thickness of copper is relatively fixed corresponding to the requirement of a product, and therefore, the thickness of copper is not generally used as a factor for dynamically adjusting impedance), and the method for reducing the thickness of the medium is realized by selecting a thinner prepreg, namely, reducing the thickness of the medium to influence the impedance value to be increased, and at the moment, if the impedance is ensured to be qualified, the method is realized by reducing the line width, namely, the line width is reduced under the condition that the impedance is ensured to be qualified. The above is the principle and method for adjusting the line width of the impedance at present. Therefore, the invention provides a brand-new PCB lamination optimization method and a PCB.

4. Description of scheme-related concepts and existing calculation methods:

(1) definition of residual copper rate:

the residual copper rate is the ratio of the area of copper on the plane of the PCB to the area of the whole PCB. For example, the copper residue ratio of an unprocessed raw material is 100%, and the copper residue ratio of the unprocessed raw material is 0% when the raw material is etched into a light plate.

(2) Calculating the residual copper rate:

residual copper rate = copper area/whole board area; the formula is just a definition formula, so that the calculation principle of the formula is convenient to understand; when the residual copper rate is actually calculated, the residual copper rate of each layer can be automatically calculated by PCB design software. For example, taking cadence allegr software as an example, the calculation method is as follows:

the Tool bar is used to execute the Tool → Quick Reports → Film Area Report command, so that the residual Copper rate value (Estimated Copper to RKI Percentage) can be checked.

(3) Calculation of media thickness

The calculation of the media thickness first requires a distinction between theoretical and actual values. In the later impedance calculation, the actual value of the medium thickness is required as a standard.

a theoretical value of dielectric thickness:

the theoretical value of the media thickness refers to the actual thickness of each PP (prepreg) itself before use, for example, the theoretical thickness of a general 1080 type prepreg is 3.031mil (0.077 mm), and the media thickness corresponding to the use of such 1080 type PP is 0.077 mm.

b actual value of dielectric thickness:

the actual thickness of the PP after filling (i.e. the thickness of the PP after pressing) is calculated into two types, and a single-side filling type is shown in a figure 1 of a drawing page; FIG. 2 shows a double-sided adhesive filling type; the two types of corresponding media thickness actual value calculation methods are respectively as follows:

media thickness calculation of type one:

actual dielectric thickness = PP theoretical thickness-copper thickness (1-residual copper rate);

calculating the thickness of the medium of type two:

actual media thickness = PP theoretical thickness-underfill loss;

wherein, the glue filling loss = (the copper residue rate of the copper foil on the inner layer of the 1-A surface) x the thickness of the copper foil on the inner layer + (the copper residue rate of the copper foil on the inner layer of the 1-B surface) x the thickness of the copper foil on the inner layer.

(4) Calculation of PCB impedance

At present, the impedance calculation method is mature, so the difference of different software calculations is small, and Si9000 is adopted in the invention for carrying out relevant explanation on the impedance calculation.

(5) The specific method for adjusting the residual copper rate is as follows:

a description of the method for increasing the residual copper rate: under the circumstances, the method is not related to the method of the present invention, and therefore, the method is not described herein, but is used for improving some process problems, such as warpage of the PCB during the manufacturing process of the PCB, when the residual copper rate of the signal layer is too low, rather than adjusting the impedance.

b, reducing the residual copper rate: in consideration of the inverse thinking, the situation of solving the problem by reducing the residual copper rate has not found a relevant precedent at present, and particularly, the method for adjusting the impedance and the impedance related parameters by reducing the residual copper rate, which is mentioned in the invention, has not found a relevant precedent in the actual PCB design.

Example 1

As shown in fig. 3, a method for optimizing a PCB lamination includes the following steps:

s2: calculating the residual copper rate of a reference layer of the ith layer of the PCB according to the impedance line width parameters, calculating a hollowed area of the reference layer according to the residual copper rate, and outputting the hollowed area as an optimization scheme of the reference layer;

s23: calculating a residual copper rate difference d, d = b-a;

and if d is larger than 0, calculating a hollowed area of the copper sheet of the reference layer according to the value of d, wherein the area of the hollowed area = d multiplied by the area of the PCB. The hollowed-out regions need to avoid the line positions and the device positions of adjacent stacks, and the thickness between the hollowed-out regions is consistent.

S3: judging whether all the laminated layers of the PCB are calculated or not; if so, outputting the optimization scheme of the PCB lamination, otherwise, i = i +1, and proceeding to step S1.

Example 2

In this embodiment, the design of the line width of the 50 ohm single-ended impedance lamination on the surface layer (L1 layer) in the 6-layer board is taken as an example to describe the technical solution of embodiment 1 of the present invention in detail, and the same is true for other methods for optimizing the impedance value.

S1: acquiring impedance line width parameters of a 1 st layer (hereinafter, referred to as an L1 layer) of the PCB;

the present invention first provides a commonly used six-layer laminate with higher reliability as shown in fig. 4:

l1_ TOP (i.e., TOP signal layer) -L2 _ GND1 (i.e., ground layer 1) -L3 _ SIG (i.e., signal layer) -L4 _ Power (i.e., Power layer) -L5 _ GND2 (i.e., ground layer 2) -L6 _ BOTTOM (i.e., BOTTOM signal layer);

wherein the thicknesses of the L1 layer and the L6 layer are 1/3oz + Plating (1/3 oz + electroplating), and the thicknesses of the L2 layer and the L5 layer are all 1 oz; the medium thickness between the L1-L2 layers (L5-L6 layers) is 1080 (0.077 mm) 3.031mil initially, the actual thickness after glue flowing in the laminating process is 0.074mm)2.926mil, and the actual thickness value is used for calculation when the impedance value is calculated; the medium between L3-L4 is a combination of PP (Pre-pregnant prepreg) with core (copper-free light plate) as an inner layer, and the thickness of the medium can be adjusted according to the actual PCB plate thickness requirement (such as 1.0/1.2/1.6 mm).

In the stack of fig. 4, the single-ended 50 ohm impedance linewidth of the L1 layer is related to the following parameters:

the line width is 4.3 mil; the thickness of the interlayer medium from L1 to L2 is 2.93 mil; the dielectric constant of PP between L1 and L2 layers is 3.7; the copper thickness is 2.2mil (the current density on the circuit is larger than that on the large copper surface during pattern electroplating, so the copper thickness on the circuit is actually larger); the other parameters are the uniform values of the conventional process (the thickness of the green oil on the substrate is 1mil, the thickness of the green oil on the circuit is 0.6mil, and the dielectric constant of the green oil is 3.8). The impedance value was calculated to be 50.9 ohms using SI 9000.

S2: calculating the residual copper rate of a reference layer of the ith layer of the PCB according to the impedance line width parameter; calculating a hollowed area of the reference layer according to the residual copper rate;

in this case, the residual copper ratio of the L2 layer in the actual item is: 96 percent; the thinnest type of prepreg between the L1 and L2 layers that could be used in the board shop was used, and the method of the present invention was used if the 4.3mil line width for 50 ohm impedance was to be reduced. Namely, by using the thought and the method of the invention, in the stage of PCB design, the purpose of adjusting the impedance line width of the L1 line is realized by adjusting the residual copper rate of the L2 layer (the reference layer of the L1 layer signal), and simultaneously the impedance is ensured to be in the required range.

The flow of the method for reducing the residual copper rate is shown in fig. 5, and is specifically described as follows:

and (4) confirming the copper rate of a reference layer in the pre-reference project PCB.

Confirming the residual copper ratio of the L2 layer in the laminate of reference item A, which is marked as a;

and secondly, confirming the residual copper rate of the reference layer after the new project PCB is finished.

Confirming the residual copper rate of the L2 layer after the new project B finishes the PCB design, and marking as B;

and thirdly, calculating the difference value of the copper residue rate of the new project and the reference project.

Calculating the difference value of the residual copper rate, and recording as d, namely d = b-a;

fourthly, the residual copper rate on the new project reference layer is processed;

if d is less than 0, i.e. b is less than a, then no processing is required, which means that the line width is not increased, and is outside the processing range of the present invention.

If d > 0, i.e. b > a, the value of b is reduced by selectively hollowing out the L2 copper sheet to make the values of b and a as close as possible. Wherein "selectively hollowing" means: when the line is hollowed out on the L2 layer, the reference integrity of the lines of the L1 and L3 layers on the L2 layer is not affected. Since the L2 layer is used as a reference plane for the lines and devices on the L1 layer and the L3 layer, the distribution positions of the lines and devices on the L1 layer and the L3 layer are checked at the same time during the hollowing process, so that the hollowed positions are avoided from the positions of the lines and devices.

At this time, on the basis of the above lamination, after the residual copper rate is reduced to 90% by selectively hollowing out the copper sheet of the L2 layer (the reference layer of the L1 layer) by using the method of the present invention, the thickness of the dielectric between the L1 and L2 layers is reduced to 2.78mil (the data is obtained by calculation and feedback from the board manufacturer), the line width of the impedance is reduced to 4mil from the original 4.3mil, the other parameters are not changed, and the result of calculating the impedance value again in SI9000 is 50.99, which still meets the requirement.

After the line width is reduced by the method of reducing the residual copper rate, the method is very favorable in the current and future PCB project designs with higher and higher density, and on one hand, the reduction of the line width can increase the wiring space; on the other hand, the method provides more impedance parameter adjusting spaces, thereby reducing the PCB wiring difficulty of the project to a certain extent and indirectly improving the PCB design efficiency. Meanwhile, the method of the invention also improves the reliability of the product:

(1) when the thickness of the medium is reduced by reducing the residual copper rate, the loop area of the high-speed signal of the L1 layer and the reference layer of the L2 layer is reduced. According to the first analysis on page 2 3.1 of the reference (li yanqing, marjon, shogao PCB design, electromagnetic compatibility [ J ]. automotive practical technology, 2014(11): 1-3), "at present, high-speed digital circuits of high-density wiring and high-integration chips generally adopt four-layer or more than four-layer multilayer boards. To improve the electromagnetic compatibility of the PCB, the most effective method is to reduce the loop area of the critical signals, especially the power signals. The reduction of the loop area can effectively reduce the differential mode radiation and improve the anti-interference capability of the circuit board. Thereby improving the reliability of the PCB product.

(2) After the dielectric thickness is reduced by reducing the copper remaining rate, it is known from the analysis of paragraph 2 in page 36 of the reference (linkin plug. PCB characteristic impedance and electromagnetic interference (i) [ J ] printed circuit information, 2000(09): 32-36) that in high-density wiring, the thinner the dielectric layer from the L1 layer to the L2 layer of the reference layer, the smaller the crosstalk.

(3) By the method, when some new PCB project designs are started, the laminated line width in some reference designs or module lines which are successfully simulated and practically verified and are officially recommended by CPU chip manufacturers can be directly used, so that the product reliability is improved.

Example 3

A PCB is disclosed, and the lamination of the PCB is optimized in layout by adopting the optimization method of any embodiment.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. A PCB board lamination optimization method is characterized by comprising the following steps:

s3: judging whether all the laminated layers of the PCB are calculated or not; if yes, outputting the optimization scheme of the PCB lamination, if no, i is i +1, and entering step S1;

the step S2 includes:

s23: calculating the difference value d between the residual copper values b and a;

2. The method of claim 1, wherein the hollowed-out area is required to avoid the circuit location and the device location of the adjacent layer stack.

3. The method of claim 2, wherein the hollowed thickness of the hollowed area is a predetermined value.

4. The method as claimed in claim 2, wherein the area of the hollowed-out area is d × the area of the PCB.

5. A PCB board, wherein the lamination of the PCB board is optimized in layout by the optimization method of any one of claims 1 to 4.