CN116939961A - Slotting method without exposing copper and packaging circuit board - Google Patents
Slotting method without exposing copper and packaging circuit board Download PDFInfo
- Publication number
- CN116939961A CN116939961A CN202210348896.7A CN202210348896A CN116939961A CN 116939961 A CN116939961 A CN 116939961A CN 202210348896 A CN202210348896 A CN 202210348896A CN 116939961 A CN116939961 A CN 116939961A
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- Prior art keywords
- copper
- circuit board
- hole
- depth
- preset area
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 179
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 179
- 239000010949 copper Substances 0.000 title claims abstract description 179
- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 16
- 238000005553 drilling Methods 0.000 claims abstract description 71
- 239000011347 resin Substances 0.000 claims abstract description 46
- 229920005989 resin Polymers 0.000 claims abstract description 46
- 238000003801 milling Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims description 12
- 238000009713 electroplating Methods 0.000 claims description 9
- 238000007747 plating Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 description 17
- 229910000679 solder Inorganic materials 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- RYGMFSIKBFXOCR-IGMARMGPSA-N copper-64 Chemical compound [64Cu] RYGMFSIKBFXOCR-IGMARMGPSA-N 0.000 description 3
- 230000008719 thickening Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0047—Drilling of holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The application discloses a slotting method without exposing copper and a packaging circuit board, wherein the slotting method without exposing copper comprises the following steps: providing a circuit board with a via hole on the surface, wherein a preset area of the circuit board is subjected to copper-avoiding treatment; carrying out back drilling treatment on the via hole in the preset area by using a back drilling process to obtain a back drilling hole with a first depth; carrying out resin plugging on the back drilling hole and the via hole; milling grooves in a preset area of the circuit board after the resin is plugged so as to obtain grooves with a second depth; wherein the second depth is less than the first depth. By the method, the groove without exposing copper is obtained, so that the reliability of embedding the electronic element into the groove is improved.
Description
Technical Field
The application belongs to the technical field of packaging, and particularly relates to a slotting method without exposing copper and a packaging circuit board.
Background
Along with the development of electronic products to the direction of functional integration, the packaging substrate is developed to the trend of high density, so that the design of embedded capacitors and resistors of the original packaging substrate cannot meet the requirement of high density integration, and the space layout is obviously insufficient. In order to obtain a higher-density packaging substrate, the design of the embedded electronic element in the packaging substrate is optimized to be an external electronic element, so that the packaging substrate can be used for higher-density circuit design.
However, since the external electronic component is protruded compared with the plane of the package substrate, and the conventional BGA (ball grid array package technology) is packaged by horizontally welding the circuit board and the package substrate, the surface of the package substrate is protruded due to the external electronic component of the conventional package substrate, and the BGA package cannot be performed, so that a groove needs to be formed on the circuit board to accommodate the protruded component on the surface of the package substrate, thereby realizing the package with the package substrate.
Because the circuit board is provided with a via hole, the conventional milling and slotting can lead to copper exposure in a slotting area, and the insulating layer after the solder resist treatment can cause the problems of height difference and the like. Therefore, it is needed to develop a process of opening via holes without exposing copper to improve the reliability of the electronic component embedded in the recess on the surface of the package substrate.
Disclosure of Invention
The application provides a slotting method without exposing copper and a packaging circuit board, so as to obtain a groove without exposing copper, thereby improving the reliability of embedding an electronic element into the groove.
In order to solve the above problems, the present application provides a method for slotting copper, comprising: providing a circuit board with a via hole on the surface, wherein a preset area of the circuit board is subjected to copper-avoiding treatment; carrying out back drilling treatment on the via hole in the preset area by using a back drilling process to obtain a back drilling hole with a first depth; carrying out resin plugging on the back drilling hole and the via hole; milling grooves in a preset area of the circuit board after the resin is plugged so as to obtain grooves with a second depth; wherein the second depth is less than the first depth.
Wherein a difference between the first depth and the second depth is not less than 8 mils.
The step of providing a circuit board with a via hole on the surface comprises the following steps: providing a circuit board; drilling holes on the surface of the circuit board; carrying out desmutting and electroless copper plating treatment on the hole; and plating copper on the hole subjected to electroless copper deposition by using a full-plate electroplating process to obtain the via hole.
Wherein the diameter of the via hole is smaller than the diameter of the back drilling hole.
Wherein the difference between the diameter of the via and the diameter of the back-drilled hole is not less than 6mil.
The step of milling the groove in the preset area of the circuit board after the resin is plugged to obtain the groove with the second depth further comprises the steps of: and removing the surface copper of the preset area on the surface of the circuit board.
The step of removing the surface copper of the preset area on the surface of the circuit board comprises the following steps: manufacturing an etching-resistant film on the surface of the circuit board, and exposing the surface copper of the preset area; etching the surface copper on the surface of the circuit board by using an etching process to remove the surface copper in the preset area; and removing the etching-resistant film to obtain the surface copper hollowed out in the preset area.
Wherein a spacing between the face copper and the side wall of the groove is not less than 10mil to avoid contact of the face copper with the side wall of the groove.
The application also provides a packaging circuit board, wherein the packaging circuit board is provided with a via hole and a groove, and an insulating layer is arranged between the groove and the via hole so as to prevent the groove from contacting copper in the via hole.
The beneficial effects of the application are as follows: the back drilling process is adopted to carry out back drilling treatment on the via hole in the preset area, so that the copper layer of the via hole in the preset area is removed, then resin hole plugging is carried out on the back drilling hole, the preset area of the circuit board after the resin hole plugging is milled to obtain a groove, the depth of the groove is lower than that of the back drilling hole, resin is filled between the bottom of the groove and the via hole, the contact between the bottom of the groove and copper in the via hole is avoided, and copper avoiding treatment is carried out on the copper layer in the preset area of the circuit board, so that the contact between the side wall of the groove and the copper layer in the circuit board is avoided, and the reliability of embedding the electronic element into the groove is improved. In addition, the method of back drilling to remove the hole copper saves the technological process of performing solder resist treatment on the bottom of the groove after slotting.
Drawings
FIG. 1 is a schematic flow chart of a first embodiment of a method for copper-free slotting according to the present application;
FIG. 2a is a schematic side view of a first embodiment of a circuit board according to the present application;
fig. 2b is a schematic top view of a first embodiment of the circuit board according to the present application;
FIG. 3a is a schematic side view of a first embodiment of a back drilling circuit board according to the present application;
fig. 3b is a schematic top view of a first embodiment of the back drilling circuit board according to the present application;
FIG. 4a is a schematic side view of a first embodiment of a circuit board after plugging holes with resin according to the present application;
FIG. 4b is a schematic top view of a first embodiment of a circuit board with a resin plug hole according to the present application;
FIG. 5 is a schematic side view of a first embodiment of a circuit board with copper removed according to the present application;
fig. 6a is a schematic side view of a first embodiment of a circuit board with grooves according to the present application;
fig. 6b is a schematic top view of a first embodiment of a circuit board with grooves according to the present application;
FIG. 7 is a schematic flow chart of a second embodiment of a method for copper-free slotting according to the present application;
FIG. 8 is a schematic flow chart of a third embodiment of a method for copper-free slotting according to the present application;
FIG. 9 is a schematic diagram of an embodiment of a package circuit board according to the present application;
fig. 10 is a schematic structural diagram of an embodiment of a package.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to fall within the scope of the present application.
The application provides a first slotting method without exposing copper, so that an electronic element can be placed in an opened groove, and the groove is not in metal connection with the electronic element, thereby improving the reliability of the electronic element. Referring to fig. 1, fig. 1 is a schematic flow chart of a first embodiment of a method for forming a trench without exposing copper according to the present application. As shown in fig. 1, the processing method of the present embodiment includes the following steps:
step S11: a circuit board provided with a via hole is provided.
And performing copper-avoiding treatment on the preset area of the circuit board. The preset area is an area to be grooved, and the copper avoiding treatment specifically comprises removing the inner layer circuit copper layer of the preset area of the circuit board.
Wherein, be provided with a plurality of via holes on the circuit board. Vias, also known as metallized holes, are used in circuit boards to connect printed conductors between copper layers of the respective circuit, and a common hole, i.e., a via, is drilled at the intersection of the conductors of each layer that are to be connected.
When the through holes exist to cause slotting of the circuit board, hole copper in the through holes is exposed, so that hole copper is arranged at the bottom of the groove, and the reliability of the electronic element placed in the groove is affected. The copper layer in the circuit board has the functions of conducting electricity and transmitting signals, so that the original reliability of signal transmission of the electronic element can be affected.
The specific structure of the circuit board is shown in fig. 2a and 2b, and fig. 2a is a schematic side view of the first embodiment of the circuit board according to the present application. As shown in fig. 2a, a plurality of vias 21 are provided on the circuit board 20, and the circuit board 20 includes an inner circuit copper layer 22 and an outer circuit copper layer 23, the inner circuit copper layer 22 and the outer circuit copper layer 23 are disposed in parallel, the inner circuit copper layer 22 includes a plurality of layers, and each copper layer is filled with resin. The inner circuit copper layer 22 is a circuit copper layer disposed on the inner layer of the circuit board 20, and the outer circuit copper layer 23 is a circuit copper layer disposed on the surface of the circuit board 20, which is also called surface copper. The circuit board 20 is further provided with a preset area 24, as shown by a dashed box in fig. 2a, wherein the periphery of the preset area 24 is treated to avoid copper exposure caused by contact between the inner circuit copper layer 23 and the side wall of the groove to be formed. The copper-avoiding treatment includes removing the inner circuit copper layer 23 around the preset area 24, i.e. the circuit copper layer is not made around the preset area 24, so that the circuit copper layer avoids the preset area 24. Fig. 2b is a schematic top view of the first embodiment of the circuit board of the present application, i.e. the schematic top view of fig. 2 a. As shown in fig. 2b, the circuit board 20 is provided with a plurality of vias 21, including vias disposed in a preset area 24 and vias disposed at the periphery of the preset area 24, and the surface of the circuit board 20 is further provided with surface copper 23.
Step S12: and carrying out back drilling treatment on the via hole in the preset area by using a back drilling technology so as to obtain a back drilling hole with a first depth.
The preset area refers to a slotting area, namely an area which is arranged opposite to the electronic element on the packaging substrate. The first depth is designed according to the depth of the groove, and is larger than the depth of the groove. In this embodiment, the first depth is at least 8 mils greater than the depth of the recess, thereby preventing the slot from opening to the hole copper. The depth and the size of the groove are set according to the electronic component, and are known in advance.
In this embodiment, the back drilling is achieved by drilling to a first depth using a depth control technique in the back drilling, wherein the back drilling design meets the medium thickness requirements between the allowed and disallowed layers of conventional back drilling.
In this embodiment, the aperture of the back-drilled hole is larger than the aperture of the via hole to remove the hole copper on the via hole sidewall during back-drilling of the via hole. In one embodiment, the aperture of the back-drilled hole differs from the aperture of the via by no less than 6 mils, and in other embodiments, the aperture of the back-drilled hole can be adjusted based on the aperture of the via and the copper thickness of the via.
Fig. 3a and 3b show a schematic side view structure of a circuit board obtained after back drilling the circuit board of the first embodiment, fig. 3a is a schematic side view of the first embodiment of the back drilling circuit board of the present application, and as shown in fig. 3a, back drilling holes 32 are drilled on the via holes 31 in a preset area of the circuit board, the back drilling holes 32 cover part of the via holes 31, the side walls of the back drilling holes 32 are free of hole copper, and the side walls of the via holes 31 are provided with hole copper. Fig. 3b is a schematic top view of a first embodiment of the back drilling circuit board according to the present application, as shown in fig. 3b, the dashed box is a preset area, and the aperture of the back drilling hole 32 in the preset area is larger than that of the via hole 31.
Step S13: and plugging the back drilling holes and the through holes by resin.
The resin is insulating resin, and resin plugging is mainly carried out on back holes of a preset area in the step, so that the formed grooves are not contacted with hole copper of the through holes. In this embodiment, the process of plugging the back hole with resin may be performed simultaneously with the process of plugging the via hole with resin, so that the step of plugging the back hole with resin alone is omitted. The resin plugging of the via hole is a necessary flow for manufacturing the via hole.
Fig. 4a and 4b show schematic side views of a first embodiment of a circuit board after resin plugging according to the present application, wherein fig. 4a is a schematic side view of the circuit board after resin plugging. As shown in fig. 4a, both the back drilling 42 and the via 41 are filled with resin. Fig. 4b is a schematic top view of a first embodiment of a circuit board after plugging holes with resin according to the present application. As shown in fig. 4b, the back drilling 42 of the preset area is filled with resin, while the via 41 of the non-preset area is also filled with resin.
The method further comprises the step of removing the surface copper of the preset area of the surface of the circuit board. Specifically, the method includes removing the surface copper by chemical etching, mechanical stripping, etc., referring to fig. 5, fig. 5 is a schematic side view of a first embodiment of a circuit board after removing the surface copper according to the present application. As shown in fig. 5, the surface copper 51 on the surface of the circuit board is spaced from the preset area 52 to be grooved, and the distance between the surface copper 51 and the preset area 52 is not less than 10mil, so that the surface copper 51 is prevented from contacting the side wall of the groove.
Step S14: and milling grooves in a preset area of the circuit board after the resin is plugged so as to obtain grooves with a second depth.
Wherein the second depth is less than the first depth. The second depth is designed according to the size of the electronic component. In this embodiment, the difference between the first depth and the second depth is at least not less than 8 mils.
In this embodiment, in order to prevent the bottom of the groove from contacting the hole copper, the hole copper of the via hole in the groove area is removed by back drilling, so as to avoid exposing the hole copper in the groove.
Referring to fig. 6a and 6b, fig. 6a is a schematic side view of a first embodiment of a circuit board with a groove according to the present application, as shown in fig. 6a, a space is formed between a bottom of a groove 61 formed on the circuit board and a via hole 62 in the circuit board by a filled insulating layer, a sidewall of the groove 61 is spaced from an inner layer circuit copper layer 63 and a surface copper 64 of the circuit board, wherein the inner layer circuit copper layer 63 is spaced from the sidewall of the groove 61 by a resin layer, and the surface copper 64 is spaced from the groove 61, so that copper is not exposed on the sidewall and the bottom of the groove 61, thereby improving reliability of the electronic component. Fig. 6b is a schematic top view of an embodiment of a circuit board with grooves according to the present application, as shown in fig. 6b, the grooves 61 are spaced apart from the surface copper 64. In the drawing, the dashed frame is a preset area, and the groove 61 is slightly smaller than the preset area, so that the copper exposure in the groove 61 area is further avoided.
The beneficial effects of this embodiment are: and carrying out back drilling treatment on the via hole in the preset area through a back drilling process, so that a copper layer of the via hole in the preset area is removed, then carrying out resin hole plugging on the back drilling, milling a groove in the preset area of the circuit board after the resin hole plugging to obtain a groove, and enabling the depth of the groove to be lower than that of the back drilling hole, so that resin is filled between the bottom of the groove and the via hole, the contact between the bottom of the groove and copper in the via hole is avoided, and the reliability of embedding the electronic element into the groove is improved. In addition, the technological process of performing the solder resist treatment on the bottom of the groove after slotting is saved, and the resin is plugged into the back drilling hole while the resin is plugged into the through hole, so that the process of independently plugging the resin into the back drilling hole is saved.
The present application also provides a second method for forming a groove without exposing copper, referring to fig. 7, and fig. 7 is a schematic flow chart of a second embodiment of the method for forming a groove without exposing copper. As shown in fig. 7, the method includes:
step S21: a circuit board is provided.
The circuit board is a PCB board with laminated multilayer circuit copper layers, inner copper layers are arranged on the inner layers of the circuit board, and surface copper is arranged on the surface of the circuit board.
In this embodiment, the circuit board performs copper-avoiding treatment on the periphery of the slot milling blank, that is, performs copper-avoiding treatment on the edge of the preset area. Specifically, the distance between the copper layer of the inner layer circuit and the preset area of the groove to be milled is not less than 12mil, and the distance between the copper layer close to the surface of the circuit board and the preset area of the groove to be milled is not less than 10mil, so that the copper layer can not appear on the side wall of the obtained groove.
Step S22: holes are drilled in the surface of the circuit board.
Specifically, different copper layers to be connected are drilled to make vias to connect the different copper layers.
Step S23: and (5) carrying out desmutting and electroless copper plating treatment on the holes.
Thin copper is attached to the side wall of the hole through chemical copper deposition process treatment, so that subsequent copper plating is facilitated.
Step S24: and plating copper on the hole subjected to electroless copper deposition by using a full-plate electroplating process to obtain the via hole.
Specifically, copper electroplating is carried out on holes and surfaces of the circuit board by using a full-board electroplating process, so that thickening treatment is carried out on the hole copper and the surface copper, and a via hole with preset thickness is obtained. The hole copper of the via hole obtained by electroless copper deposition is thin, and cannot meet the specification of the hole copper, that is, the signal transmission of the via hole cannot be realized, so that the hole copper needs to be thickened by electroplating.
In this embodiment, the vias are distributed over the entire surface of the circuit board, including the vias disposed in the predetermined area and the vias disposed in the non-predetermined area. The position of the through hole is related to the connection relation of the circuit copper layer in the circuit board.
Step S25: and carrying out back drilling treatment on the via hole in the preset area by using a back drilling technology so as to obtain a back drilling hole with a first depth.
The preset area is a groove area to be milled, and is generally larger than the groove area, and errors exist in milling grooves due to the existence of milling groove tolerance. The preset area is slightly larger than the groove area, so that the fault tolerance of the milling groove is improved.
The back drilling process further comprises depth control, namely drilling to a preset depth. In this embodiment, a via hole is drilled to a first depth using a back drilling process to remove hole copper at the first depth of the via hole. The first depth is deeper than the second depth of the groove, so that the opened groove does not expose the hole copper. Wherein the difference between the first depth and the second depth is not less than 8mil, and in one embodiment, the first depth is 8mil deeper than the second depth in order to reduce back drilling depth as much as possible and increase the penetration rate of the via.
It should be noted that the design of the back drill depth needs to meet the medium thickness requirement between the back drill allowing and not allowing penetration of the layer. I.e. the first depth fulfils the intermediate thickness between the drill-through allowed layer and the drill-through not allowed layer.
Step S26: and plugging the back drilling holes and the through holes by resin.
The method specifically comprises the steps of carrying out resin hole plugging on back holes of a preset area and carrying out resin hole plugging on through holes of a non-preset area. And in addition, the method further comprises the step of plugging the via hole below the back drilling hole with resin, so that the back drilling hole and the via hole in the preset area are filled with insulating resin.
Step S27: and milling grooves in a preset area of the circuit board after the resin is plugged so as to obtain grooves with a second depth.
Wherein the second depth is at least 8 mils shallower than the first depth. Specifically, a preset area of the circuit board is opened to a second depth through a depth-control slot milling process, so that a groove is formed. In this embodiment, the controlled depth milling groove depth tolerance is controlled to be + -3 mils and the horizontal width tolerance is controlled to be + -4 mils.
Before this step, the method may further include performing a solder mask covering process on the preset area to ensure the size of the opening groove, or may not perform the solder mask covering process.
The beneficial effects of this embodiment are: through drilling the via hole on the circuit board to meet the design of connecting multiple layers of circuits in the circuit board, and forming a groove without exposing copper on the circuit board to meet the requirement of placing electronic elements. Therefore, the through hole is provided with the groove without exposing copper, thereby not only meeting the requirement of placing electronic elements, but also meeting the circuit connection requirement of the circuit board.
The present application also provides a third method for slotting copper without exposure, referring to fig. 8, and fig. 8 is a schematic flow chart of a third embodiment of the method for slotting copper without exposure. As shown in fig. 8, the method includes:
step S31: a circuit board is provided.
The circuit board is a multi-layer board, a circuit copper layer is arranged between each two layers, wherein the circuit copper layer is subjected to copper avoidance treatment in a preset area, and the preset area is a groove area to be milled. Specifically, the distance between the inner circuit copper layer of the circuit board and the side wall of the groove is not less than 12mil, and the distance between the outer circuit copper layer of the circuit board and the side wall of the groove is not less than 10mil, so that the circuit copper layer on the circuit board cannot be exposed under the condition that the groove side wall has a milling tolerance.
Step S32: holes are drilled in the surface of the circuit board.
Holes are drilled along the direction perpendicular to the circuit copper layers to make vias connecting each circuit copper layer on the circuit board.
The method also comprises the steps of removing the drilling pollution of the drilled hole and electroless copper deposition, so that a layer of thin copper is plated on the side wall of the hole, and the subsequent copper electroplating of the hole is facilitated.
Step S33: and carrying out copper plating on the holes of the circuit board to obtain the through holes.
And particularly, thickening copper plating is carried out on holes and surface copper on the circuit board by using a full-board electroplating process so as to obtain through holes, and meanwhile, the surface copper is thickened.
The via hole is a metallized hole, and the side wall of the via hole is provided with hole copper. And thickening the hole copper subjected to electroless copper deposition by a full-plate electroplating process to meet the specification of the requirement of the via hole so as to enable the via hole to reach the conducting capacity.
The plurality of through holes are distributed on the whole surface of the circuit board.
Step S34: and carrying out back drilling treatment on the via hole in the preset area by using a back drilling technology so as to obtain a back drilling hole with a first depth.
The via holes are divided into a preset area and a non-preset area, and back drilling treatment is carried out on the via holes in the preset area to obtain back drilling holes with a first depth. The aperture of the back drilling hole is larger than that of the through hole so as to remove hole copper in the through hole in the preset area. In one embodiment, the aperture of the back-drilled holes is greater than 6 mils larger than the aperture of the vias. Too large a difference in aperture ratio of the back-drilled holes to the apertures of the vias can affect adjacent vias, and too small a difference in aperture ratio of the back-drilled holes to the apertures of the vias can result in an unclean copper removal of the holes, thus a difference of 6mil is most suitable.
Step S35: and plugging the back drilling holes and the through holes by resin.
And (5) carrying out resin hole plugging on the back drilling hole of the area needing slotting and hole milling. Specifically, the resin is plugged into the via holes and the back holes are plugged together, so that the extra back hole plugging process is not added.
Step S36: and removing the surface copper of the preset area on the surface of the circuit board.
In this embodiment, the surface of the circuit board is provided with surface copper, and the surface copper in the preset area is removed between the slotting of the circuit board, so that the slotting of the circuit board is facilitated.
In one embodiment, the method comprises the following steps: manufacturing an etching-resistant film on the surface of the circuit board, and exposing surface copper of a preset area; etching the surface copper on the surface of the circuit board by using an etching process to remove the surface copper in a preset area; and removing the etching-resistant film to obtain the surface copper hollowed out in the preset area. In other embodiments the surface copper may also be removed by polishing, drilling, or the like.
In this embodiment, the distance between the surface copper remaining after the surface copper in the preset area is removed and the side wall of the groove is not less than 10mil, so that the surface copper is prevented from contacting the groove, the side wall of the groove is prevented from exposing copper, and the insulating groove is obtained, so that the reliability of placing the electronic element is improved, and the performance of the electronic element is not affected by interference and the like.
Step S37: and milling grooves in a preset area of the circuit board after the resin is plugged so as to obtain grooves with a second depth.
The second depth is shallower than the first depth, so that the depth of the groove is shallower than the back drilling hole, the groove cannot be opened to the hole copper area, and copper exposure at the bottom of the groove is avoided. In this embodiment, the controlled depth milling groove depth tolerance is controlled to be + -3 mils and the horizontal width tolerance is controlled to be + -4 mils. The difference between the second depth and the first depth is not less than 8mil to avoid copper leakage at the bottom of the groove due to the existence of depth control tolerance. Also, the distance between the side wall of the groove and the surface copper and inner layer circuit copper layer is not less than 10mil, so as to avoid exposing copper on the side wall of the groove due to the existence of the depth control tolerance.
The beneficial effects of this embodiment are: the bottom of the milled groove can be prevented from exposing copper by controlling the depth of the back drilling hole, copper avoiding treatment is carried out on the surface copper and the inner layer circuit copper layer, copper exposing on the side wall of the milled groove can be avoided, and the groove which is not exposed copper completely can be milled in the mode, so that the reliability of placing electronic elements is improved.
The application further provides a packaged circuit board, and particularly referring to fig. 9, fig. 9 is a schematic structural diagram of an embodiment of the packaged circuit board of the application. As shown in fig. 9, the package circuit board is provided with a groove 91, a via hole 92 and a circuit copper layer 93, and an insulating layer is provided between the bottom of the groove 91 and the via hole 92, so as to avoid contact between the groove 91 and copper in the via hole 92. An insulating layer is provided between the side walls of the recess 91 and the wiring copper layer 93 so as to avoid contact between the side walls of the recess 91 and the wiring copper layer 93.
In this embodiment, the distance between the via 92 and the recess 91 is at least 8 mils apart.
In the present embodiment, the wiring copper layer 93 includes a surface copper 931 and an inner wiring copper layer 932, the surface copper 931 being spaced apart from the side wall of the recess 91 by at least 10 mils.
In this embodiment, the distance between the inner wiring copper layer 932 and the sidewall of the recess 91 is at least 12mil. It should be noted that, the distance between the inner layer copper layer 932 and the sidewall of the groove 91 is greater than the distance between the surface copper layer 932 and the sidewall of the groove 91, so as to avoid the inner layer copper layer 932 from being displaced during lamination or manufacturing process to contact with the sidewall of the groove 91.
Referring to fig. 10, fig. 10 is a schematic structural diagram of an embodiment of a package. As shown in fig. 10, the package includes a package substrate 101 and a package circuit board 102. The package substrate 101 provides electrical connection, protection, support, heat dissipation, assembly, etc. for electronic components, so as to achieve the purposes of multi-pin, reduced package product volume, improved electrical performance and heat dissipation, ultra-high density, or multi-chip modularization.
The package substrate 101 is provided with an electronic element 1011 on a side surface thereof close to the package circuit board 102, wherein the electronic element 1011 includes a capacitive element, a resistive element, and the like. The package circuit board 102 is provided with a recess near the package substrate 101 at a position corresponding to the electronic component 1011, the recess being used for placing the electronic component 1011. The specific structure of the package circuit board 102 is shown in fig. 9.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.
Claims (10)
1. A method of grooving copper-free, comprising:
providing a circuit board provided with a via hole; wherein, the preset area of the circuit board is processed for avoiding copper;
carrying out back drilling treatment on the via hole in the preset area by using a back drilling process to obtain a back drilling hole with a first depth;
carrying out resin plugging on the back drilling hole and the via hole;
milling grooves in the preset area of the circuit board after the resin is plugged so as to obtain grooves with a second depth;
wherein the second depth is less than the first depth.
2. The method of claim 1, wherein the first depth and the second depth differ by no less than 8 mils.
3. The method of claim 1, wherein the step of providing a circuit board with vias comprises:
providing a circuit board;
drilling holes on the surface of the circuit board;
carrying out desmutting and electroless copper plating treatment on the hole;
and plating copper on the hole subjected to electroless copper deposition by using a full-plate electroplating process to obtain the via hole.
4. A method of copper-free grooving according to claim 3, wherein the diameter of said via is smaller than the diameter of said backdrilled hole.
5. The method of claim 4, wherein the difference between the diameter of the via and the diameter of the backdrilled hole is not less than 6mil.
6. The method for slotting without exposing copper according to claim 1, wherein before the step of slotting a predetermined area of the circuit board after the resin plug hole to obtain a groove with a second depth, the method further comprises:
and removing the surface copper of the preset area on the surface of the circuit board.
7. The method of claim 6, wherein the step of removing the copper from the predetermined area of the circuit board surface comprises:
manufacturing an etching-resistant film on the surface of the circuit board, and exposing the surface copper of the preset area;
etching the surface copper on the surface of the circuit board by using an etching process to remove the surface copper in the preset area;
and removing the etching-resistant film to obtain the surface copper hollowed out in the preset area.
8. The method of claim 6, wherein the surface copper is spaced from the sidewall of the recess by a distance of not less than 10 mils to avoid contact with the sidewall of the recess.
9. The method for copper-free slotting of claim 1, wherein the copper-free treatment of the predetermined area of the circuit board comprises: and removing the inner layer circuit copper layer of the preset area of the circuit board.
10. The utility model provides a packaging circuit board which characterized in that is provided with recess, via hole and circuit copper layer on the packaging circuit board, the bottom of recess with be provided with the insulating layer between the via hole, in order to avoid the bottom of recess with copper contact in the via hole, the lateral wall of recess with set up the insulating layer between the circuit copper layer, in order to avoid the lateral wall of recess with circuit copper layer contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210348896.7A CN116939961A (en) | 2022-04-01 | 2022-04-01 | Slotting method without exposing copper and packaging circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210348896.7A CN116939961A (en) | 2022-04-01 | 2022-04-01 | Slotting method without exposing copper and packaging circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116939961A true CN116939961A (en) | 2023-10-24 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210348896.7A Pending CN116939961A (en) | 2022-04-01 | 2022-04-01 | Slotting method without exposing copper and packaging circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116939961A (en) |
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2022
- 2022-04-01 CN CN202210348896.7A patent/CN116939961A/en active Pending
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