CN107093563A - 一种集成电路封装工艺 - Google Patents

一种集成电路封装工艺 Download PDF

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Publication number
CN107093563A
CN107093563A CN201710135993.7A CN201710135993A CN107093563A CN 107093563 A CN107093563 A CN 107093563A CN 201710135993 A CN201710135993 A CN 201710135993A CN 107093563 A CN107093563 A CN 107093563A
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integrated circuit
technique
bonding
scribing
circuit packaging
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孙明华
许方宏
王传玉
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ANHUI BRILLIANT LITTLE ELECTRONICS Co Ltd
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ANHUI BRILLIANT LITTLE ELECTRONICS Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737Organic materials with or without a thermoconductive filler
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92162Sequential connecting processes the first connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明涉及半导体集成电路制造领域,特别是指一种集成电路封装工艺,第一步,磨片;第二部,划片;第三部,装片;第四部,键合;第五步,塑封。本发明所述的集成电路封装工艺,具有制程简单易于操作适用于当前批量封装的需求,此外,在封装工艺中采用银粉和环氧树脂的混合物制成的导电胶具有是协助散热的重要作用,使用金丝或铜丝做为金属线进行键合具有速度快、质量良好,通过加热制品,同时施加超声功率和压力,能实现内外焊点的连接。

Description

一种集成电路封装工艺
技术领域
本发明涉及半导体集成电路制造领域,特别是指一种集成电路封装工艺。
背景技术
封装就是将一个具有一定功能的集成电路芯片,放置在一个与之相适应的外壳容器中,为芯片提供一个稳定、可靠的工作环境。封装的目的在于保护芯片不受外部环境的影响,并为之提供一个良好的工作条件,以使集成电路具有稳定、正常的功能。随着电子产品的突飞猛进的发展,对集成电路的需求量也与日俱增,必须研究一种适用于批量封装工艺,除此之外,电子产品使用的安全可靠性必须要求集成电路在封装工艺中加以控制。
发明内容
本发明的目的就是提供一种具有高质量批量生产集成电路的封装工艺。
为解决上述技术问题,本发明采取如下技术方案:
一种集成电路封装工艺,包括如下步骤:第一步,磨片:采用立式磨床原理,利用高速旋转的砂轮与设备卡盘的相对运动磨削圆片背面的硅层,使圆片厚度划片的要求;
第二部,划片:采用卧式磨床原理,利用高速旋转的划片刀切割圆片,按将磨片后的圆片切割成单一个体芯片;
第三部,装片:划片后的个体芯片通过导电胶固定在引线框架中岛的指定位置;
第四部,键合:通过精细焊接技术,用金属线连接芯片电极和引线框架的引脚,构成电回路;
第五步,塑封:将完成键合的 IC 放入模具中,以注塑的方式将预热后的环氧模塑料填入模具中,脱模后,再烘烤使胶体充分硬化。
优选地,所述的第三部装片使用的导电胶为具有导电性的银粉和环氧树脂的混合物。
优选地,所述的第四部键合的金属线为金丝或铜丝。
与现有技术相比,本发明的有益效果为:
本发明所述的集成电路封装工艺,具有制程简单易于操作适用于当前批量封装的需求,此外,在封装工艺中采用银粉和环氧树脂的混合物制成的导电胶具有是协助散热的重要作用,使用金丝或铜丝做为金属线进行键合具有速度快、质量好;通过加热制品,同时施加超声功率和压力,能实现内外焊点的连接。
附图说明
图1为本发明工艺流程示意图。
具体实施方式
参见附图1所示,一种集成电路封装工艺,包括如下步骤: 第一步,磨片:采用立式磨床原理,利用高速旋转的砂轮与设备卡盘的相对运动磨削圆片背面的硅层,使圆片厚度划片的要求;
第二部,划片:采用卧式磨床原理,利用高速旋转的划片刀切割圆片,按将磨片后的圆片切割成单一个体芯片;
第三部,装片:划片后的个体芯片通过导电胶固定在引线框架中岛的指定位置;
第四部,键合:通过精细焊接技术,用金属线连接芯片电极和引线框架的引脚,构成电回路;
第五步,塑封:将完成键合的 IC 放入模具中,以注塑的方式将预热后的环氧模塑料填入模具中,脱模后,再烘 烤 (后固化)使胶体充分硬化。
优选地,所述的第三部装片使用的导电胶为具有导电性的银粉和环氧树脂的混合物。
优选地,所述的第四部键合的金属线为金丝或铜丝。
本发明所述的集成电路封装工艺,具有制程简单易于操作适用于当前批量封装的需求,此外,在封装工艺中采用银粉和环氧树脂的混合物制成的导电胶具有是协助散热的重要作用,使用金丝或铜丝做为金属线进行键合具有速度快、质量好的优点;通过加热制品,同时施加超声功率和压力,能实现内外焊点的连接。
以上所述,仅是对本发明的较佳实施例而已,并非是对本发明做其他形式的限制,任何熟悉本专业的技术人员可能利用上述揭示的技术内容加以变更或改型为等同变化的等效实施例。但是,凡是未脱离本发明方案内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化与改型,仍属于本发明的保护范围。

Claims (3)

1.一种集成电路封装工艺,其特征在于:包括如下步骤:第一步,磨片:采用立式磨床原理,利用高速旋转的砂轮与设备卡盘的相对运动磨削圆片背面的硅层,使圆片厚度划片的要求;
第二部,划片:采用卧式磨床原理,利用高速旋转的划片刀切割圆片,按将磨片后的圆片切割成单一个体芯片;
第三部,装片:划片后的个体芯片通过导电胶固定在引线框架中岛的指定位置;
第四部,键合:通过精细焊接技术,用金属线连接芯片电极和引线框架的引脚,构成电回路;
第五步,塑封:将完成键合的 IC 放入模具中,以注塑的方式将预热后的环氧模塑料填入模具中,脱模后,再烘烤使胶体充分硬化。
2.根据权利要求1所述的一种集成电路封装工艺,其特征在于:所述的第三部装片使用的导电胶为具有导电性的银粉和环氧树脂的混合物。
3.根据权利要求1所述的一种集成电路封装工艺,其特征在于:所述的第四部键合的金属线为金丝或铜丝。
CN201710135993.7A 2017-03-08 2017-03-08 一种集成电路封装工艺 Pending CN107093563A (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6894382B1 (en) * 2004-01-08 2005-05-17 International Business Machines Corporation Optimized electronic package
CN1640618A (zh) * 2004-01-08 2005-07-20 财团法人工业技术研究院 晶片磨床构造
CN101442035A (zh) * 2008-12-14 2009-05-27 天水华天科技股份有限公司 一种扁平无引线封装件及其生产方法
CN102339809A (zh) * 2011-11-04 2012-02-01 北京工业大学 一种多圈引脚排列四边扁平无引脚封装及制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6894382B1 (en) * 2004-01-08 2005-05-17 International Business Machines Corporation Optimized electronic package
CN1640618A (zh) * 2004-01-08 2005-07-20 财团法人工业技术研究院 晶片磨床构造
CN101442035A (zh) * 2008-12-14 2009-05-27 天水华天科技股份有限公司 一种扁平无引线封装件及其生产方法
CN102339809A (zh) * 2011-11-04 2012-02-01 北京工业大学 一种多圈引脚排列四边扁平无引脚封装及制造方法

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Application publication date: 20170825