CN107026220A - Vertical LED chip structure and preparation method thereof - Google Patents
Vertical LED chip structure and preparation method thereof Download PDFInfo
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- CN107026220A CN107026220A CN201610068621.2A CN201610068621A CN107026220A CN 107026220 A CN107026220 A CN 107026220A CN 201610068621 A CN201610068621 A CN 201610068621A CN 107026220 A CN107026220 A CN 107026220A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 93
- 239000002184 metal Substances 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 238000005520 cutting process Methods 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 31
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 25
- 239000010980 sapphire Substances 0.000 claims abstract description 25
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 20
- 238000007788 roughening Methods 0.000 claims abstract description 16
- 230000008569 process Effects 0.000 claims abstract description 14
- 238000001039 wet etching Methods 0.000 claims abstract description 14
- 238000005516 engineering process Methods 0.000 claims abstract description 11
- 238000000576 coating method Methods 0.000 claims description 20
- 239000011248 coating agent Substances 0.000 claims description 19
- 239000000243 solution Substances 0.000 claims description 11
- 239000011259 mixed solution Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 238000005260 corrosion Methods 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- 229910015844 BCl3 Inorganic materials 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 3
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 241001062009 Indigofera Species 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000010437 gem Substances 0.000 description 1
- 229910001751 gemstone Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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Abstract
The present invention provides a kind of vertical LED chip structure and preparation method thereof, including：1）Sapphire Substrate is provided, UID-GaN layers, N-GaN layers, multiple quantum well layer and P-GaN layers are grown successively on a sapphire substrate；2）P electrode is formed on P-GaN layers；3）Bonded substrate is provided, by bonded substrate and step 2）Obtained structure bonding；4）Peel off Sapphire Substrate；5）Remove UID-GaN layers；6）In N-GaN layer surfaces formation mask layer, according to mask layer, the GaN that part is located at Cutting Road region is removed using ICP etching technics；7）Mask layer is removed, the GaN for remaining in Cutting Road region is removed using wet-etching technology, while forming ledge structure；8）Surface coarsening is carried out to N-GaN layer surfaces, roughening micro-structural is formed；9）N electrode is prepared in N-GaN layer surfaces.It is located at the GaN in Cutting Road region thoroughly due to not carved completely in ICP etching processes, Cutting Road region does not have the generation that metal splashes thing, and the side wall of ledge structure will not produce electric leakage or ESD punctures electric leakage.
Description
Technical field
The invention belongs to field of semiconductor illumination, more particularly to a kind of vertical LED chip structure and preparation method thereof.
Background technology
Compared to traditional positive assembling structures of GaN base LED, vertical stratification has good heat dissipation, can carry high current, lights strong
Degree is high, power consumption is small, long lifespan the advantages of, be widely used in general illumination, Landscape Lighting, special lighting, automotive lighting
Deng field, the solution as generation high-power GaN-based LED great potential, just more and more paid close attention to by industry and
Research.
Vertical LED chip structure is by bonding chip or galvanoplastic, with reference to techniques such as laser lift-offs, by GaN base epitaxial structure
It is transferred to from Sapphire Substrate on the good metal of thermal conductivity or bonding semiconductor substrate, the electrode knot being distributed above and below formation
Structure so that electric current flows vertically through whole device.It is deep using inductive coupling plasma (ICP) after bonding chip, laser lift-off
Etching technics etches the GaN in chip cutting road totally, while ledge structure is formed, then with KOH or NaOH solution pair
N-GaN layer surfaces are roughened, and in N-GaN layers of coarse surface formation N electrode.
However, in existing process, the GaN in chip cutting road is carved using inductive coupling plasma (ICP) deep etching process
Erosion is clean, while during forming ledge structure, because the GaN positioned at Cutting Road is completely removed, being easily etched to metal
Bonded layer and splash metal and splash thing, and due to this method etch the ledge structure to be formed side wall and bonded substrate angle it is smaller,
Only 35 °~45 ° or so, metal splashes thing and is easily deposited on the side wall of ledge structure, so that the side wall of ledge structure
Easily form electric leakage or ESD (static discharge) punctures electric leakage.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of vertical LED chip structure and its preparation
Method, for solving in the prior art because the easy deposited metal of side wall of ledge structure in vertical LED chip structure splashes thing
The side wall of caused ledge structure easily forms electric leakage or ESD the problem of puncture electric leakage.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation method of vertical LED chip structure, described
Preparation method comprises the following steps：
1) Sapphire Substrate is provided, UID-GaN layers, N-GaN layers, MQW is grown successively in the Sapphire Substrate
Layer and P-GaN layers；
2) P electrode is formed on described P-GaN layers；
3) bonded substrate being provided, by the bonded substrate and step 2) obtained structure is bonded together, and the P electrode
Surface and the surface of the bonded substrate are brought into close contact；
4) Sapphire Substrate is peeled off；
5) described UID-GaN layers is removed；
6) in the N-GaN layer surfaces formation mask layer corresponding to the region that subsequently form ledge structure, covered according to described in
Film layer, the GaN that part is located at Cutting Road region is removed using ICP etching technics；
7) mask layer is removed, and the GaN for remaining in Cutting Road region is removed using wet-etching technology, while forming step
Structure；
8) surface coarsening is carried out to the N-GaN layer surfaces, forms roughening micro-structural；
9) the N-GaN layer surfaces after surface coarsening prepare N electrode.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure of the present invention, step 2) in, including following step
Suddenly：
2-1) in the ITO nesa coating of P-GaN layer surfaces formation Ohmic contact；
2-2) reflecting layer, ITO nesa coating described in the reflecting layer covers are formed on the ITO nesa coating surface；
2-3) in the reflection layer surface formation metal bonding layer, the metal bonding layer coats the reflecting layer.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure of the present invention, step 2-3) in, the metal
The material of bonded layer is inert metal.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure of the present invention, step 3) in, the bonding lining
Bottom includes one kind in Si substrates, W/Cu substrates and Mo/Cu substrates.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure of the present invention, step 4) in, shelled using laser
Separating process peels off the Sapphire Substrate.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure of the present invention, step 5) in, carved using ICP
Etching technique removes described UID-GaN layers, and the etching gas that the ICP etching methods are used include Cl2And BCl3One kind or it is mixed
Close gas.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure of the present invention, step 6) in, the mask layer
For SiO2Mask layer.
Be used as the present invention vertical LED chip structure preparation method a kind of preferred scheme, step 7) in, formation it is described
Angle between the side wall and bonded substrate of ledge structure is 50 °~70 °.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure of the present invention, step 7) in, wet etching work
The etchant solution used in skill is H2SO4With H3PO4Mixed solution.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure of the present invention, step 8) use wet etching work
Skill carries out surface coarsening to the N-GaN layer surfaces, makes the N-GaN layer surfaces formation pyramid roughening micro-structural, institute
Stating the etchant solution of wet corrosion technique use includes KOH and H3PO4In one kind or its mixed solution.
The present invention also provides a kind of vertical LED chip structure, and the vertical LED chip structure includes：Bonded substrate, successively
P electrode on the bonded substrate, P-GaN layers, multiple quantum well layer and N-GaN layers are laminated in, and positioned at described
The N electrode of N-GaN layer surfaces；Described P-GaN layers, described multiple quantum well layer and the N-GaN layers of formation ledge structure,
Angle between the side wall and the bonded substrate of the ledge structure is 50 °~70 °；The N-GaN layer surfaces are formed with roughening
Micro-structural.
As a kind of preferred scheme of the vertical LED chip structure of the present invention, the bonded substrate includes Si substrates, W/Cu and served as a contrast
One kind in bottom and Mo/Cu substrates.
As a kind of preferred scheme of the vertical LED chip structure of the present invention, the P electrode includes ITO nesa coating, anti-
Layer and metal bonding layer are penetrated, the metal bonding layer is located at the bonded substrate surface, and the reflecting layer is located at the metal bonding
Layer surface, the ITO nesa coating is embedded in the reflecting layer, and surface and P-GaN layers of formation Ohmic contact.
As a kind of preferred scheme of the vertical LED chip structure of the present invention, the material of the metal bonding layer is inert metal.
As a kind of preferred scheme of the vertical LED chip structure of the present invention, the roughening micro-structural is that pyramid is roughened micro- knot
Structure.
As described above, vertical LED chip structure of the present invention and preparation method thereof, has the advantages that：The present invention is first
The GaN that part is located at Cutting Road region is removed using ICP etching technics according to mask layer, then gone again using wet-etching technology
Except the GaN for remaining in Cutting Road region, and ledge structure is formed simultaneously, be located at thoroughly due to not carved completely in ICP etching processes
The GaN in Cutting Road region, Cutting Road region does not have the generation that metal splashes thing, the side wall of ledge structure will not produce electric leakage or
ESD punctures electric leakage；Meanwhile, the side wall of ledge structure and the angle of bonded substrate prepared using the preparation method can reach
50 °~70 °, the ability that the anti-ESD of side wall of ledge structure punctures can be greatly increased.
Brief description of the drawings
Fig. 1 is shown as the schematic flow sheet of the preparation method of the vertical LED chip structure provided in the embodiment of the present invention one.
Each step of preparation method that Fig. 2 to Figure 11 is shown as the vertical LED chip structure provided in the embodiment of the present invention one is in
Existing structural representation.
Component label instructions
100 Sapphire Substrates
101 UID-GaN layers
102 N-GaN layers
103 multiple quantum well layers
104 P-GaN layers
105 ledge structures
106 P electrodes
1061 ITO nesa coatings
1062 reflecting layer
1063 metal bonding layers
107 bonded substrates
108 mask layers
109 roughening micro-structurals
110 N electrodes
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be as disclosed by this specification
Content understand easily the present invention other advantages and effect.The present invention can also add by way of a different and different embodiment
To implement or apply, the various details in this specification can also be based on different viewpoints and application, in the essence without departing from the present invention
God is lower to carry out various modifications or alterations.
Fig. 2 is referred to Figure 11.It should be noted that the diagram provided in the present embodiment only illustrates the present invention in a schematic way
Basic conception, though only display is with relevant component in the present invention rather than according to component count during actual implement, shape in diagram
And size is drawn, it is actual when implementing, and kenel, quantity and the ratio of each component can be a kind of random change, and its assembly layout
Kenel may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present invention provides a kind of preparation method of vertical LED chip structure, the preparation method at least include with
Lower step：
1) Sapphire Substrate is provided, UID-GaN layers, N-GaN layers, MQW is grown successively in the Sapphire Substrate
Layer and P-GaN layers；
2) P electrode is formed on described P-GaN layers；
3) bonded substrate being provided, by the bonded substrate and step 2) obtained structure is bonded together, and the P electrode
Surface and the surface of the bonded substrate are brought into close contact；
4) Sapphire Substrate is peeled off；
5) described UID-GaN layers is removed；
6) in the N-GaN layer surfaces formation mask layer corresponding to the region that subsequently form ledge structure, covered according to described in
Film layer, the GaN that part is located at Cutting Road region is removed using ICP etching technics；
7) mask layer is removed, and the GaN for remaining in Cutting Road region is removed using wet-etching technology, while forming step
Structure；
8) surface coarsening is carried out to the N-GaN layer surfaces, forms roughening micro-structural；
9) the N-GaN layer surfaces after surface coarsening prepare N electrode.
In step 1) in, the S1 steps and Fig. 2 to Fig. 3 in Fig. 1 are referred to there is provided Sapphire Substrate 100, in the indigo plant
UID-GaN layers 101, N-GaN layers 102, multiple quantum well layer 103 and P-GaN layers are grown on jewel substrate 100 successively
104。
As an example, preparing the UID-GaN layers 101, N-GaN layers 102, MQW using chemical vapor deposition method
103 and P-GaN of layer layers 104, the UID-GaN layers 101 are used as the cushion of the N-GaN layers 102, Ke Yi great
The big growth quality for improving GaN epitaxial light emission structures, so as to improve the luminous efficiency of light emitting diode.
As an example, grow the UID-GaN layers 101 successively on the surface of Sapphire Substrate 100, it is described N-GaN layers
102nd, before multiple quantum well layer 103 and the P-GaN layer 104, in addition to the Sapphire Substrate 100 is carried out
The step of cleaning, to remove the impurity on the surface of Sapphire Substrate 100, such as polymer, dust.
In step 2) in, S2 steps and Fig. 4 in Fig. 1 are referred to, P electrode 106 is formed on the P-GaN layers 104.
As an example, the step comprises the following steps：
2-1) ITO nesa coating 1061 for forming Ohmic contact on the surface of P-GaN layers 104 is used as ohmic contact layer；
Specifically, the specific method that the ITO nesa coating 1061 of Ohmic contact is formed on the surface of P-GaN layers 104 is：It is first
First, one layer of ITO layer is deposited on the surface of P-GaN layers 104 using evaporation process；Secondly, in ITO layer surface coating
Photoresist layer, using the graphical photoresist layer of photoetching process, to define the figure of the ITO nesa coating 1061；
Then, etch the ITO layer to form the ITO nesa coating 1061 according to the patterned photoresist layer；Finally,
Remove the photoresist layer；
Reflecting layer 1062 2-2) is formed on the surface of ITO nesa coating 1061, the reflecting layer 1062 coats the ITO
Nesa coating 1061；Specifically, depositing the reflecting layer on the surface of ITO nesa coating 1061 using evaporation process
1062, the reflecting layer 1062 can be but be not limited only to Ag reflecting layer；
2-3) metal bonding layer 1063 is formed on the surface of reflecting layer 1062；Specifically, using evaporation process in the reflection
1062 surface of layer form the metal bonding layer 1063, and the metal bonding layer 1063 is metal structure, the metal bonding layer
Material can be to include Cr, Pt inert metal.The material selection inert metal of the metal bonding layer 1063, follow-up
Wet-etching technology is removed when remaining in the GaN in Cutting Road region, the metal bonding layer 1063 not with hot acid solution's reaction or
Reaction it is very slow, can as wet etching etching stopping face.
In step 3) in, the S3 steps and Fig. 5 in Fig. 1 are referred to there is provided bonded substrate 107, by the bonded substrate 107
With step 2) obtained structure is bonded together, and the surface of the P electrode 106 and the surface of the bonded substrate 107 are tight
It is closely connected to close.
As an example, the bonded substrate 107 includes one kind in Si substrates, W/Cu substrates and Mo/Cu substrates.In this reality
Apply in example, the bonded substrate 107 is W/Cu substrates, can be with because W/Cu substrates have higher conduction and thermal conductivity
Greatly improve the radiating efficiency of LED chip.
As an example, the bonded substrate 107 and step 2) after obtained structure is bonded together, the metal bonding layer
1063 surface and the surface of the bonded substrate 107 are brought into close contact.
In step 4) in, S4 steps and Fig. 6 in Fig. 1 are referred to, the Sapphire Substrate 100 is peeled off.
The Sapphire Substrate 100 is peeled off as an example, can use but be not limited only to laser lift-off.
In step 5) in, S5 steps and Fig. 7 in Fig. 1 are referred to, the UID-GaN layers 101 are removed.
As an example, removing the UID-GaN layers 101, the etching gas that the ICP etching methods are used using ICP etching methods
Including Cl2And BCl3One kind or its mixed gas.
In step 6) in, S6 steps and Fig. 8 in Fig. 1 are referred to, corresponding to the region that subsequently form ledge structure
The surface of N-GaN layers 102 forms mask layer 108, and according to the mask layer 108, part is removed using ICP etching technics
GaN positioned at Cutting Road region.
As an example, forming the mask on the surface of N-GaN layers 102 corresponding to the region that subsequently form ledge structure
Layer 108 specific method be：First, SiO is deposited on the surface of N-GaN layers 1022Layer；Secondly, in the SiO2Layer
Surface coats photoresist layer；Again, using the graphical photoresist layer of photoetching process, to define the mask layer 108
Shape；Then, the SiO is etched using wet-etching technology according to the patterned photoresist layer2Layer is to form the mask
Layer 108；Finally, the photoresist layer is removed.
As an example, according to the mask layer 108, part is removed positioned at the GaN's in Cutting Road region using ICP etching technics
Specific method is：First, part is removed using ICP etching technics etching according to the mask layer 108 to be located in Cutting Road region
The N-GaN layers 102, the multiple quantum well layer 103 and P-GaN layers 104, do not cut through in etching process described
The GaN layer that N-GaN layers 102, the multiple quantum well layer 103 and P-GaN layers 104 are constituted, it is preferable that etching is completed
Afterwards, the part P-GaN layers 104 are remained with the Cutting Road region；Being located at for retaining is described outside the Cutting Road region
N-GaN layers 102, the multiple quantum well layer 103 and P-GaN layers 104 collectively form the blank of the ledge structure 105
Structure.According to SiO2The mask layer 108 of layer removes the GaN that part is located at Cutting Road region using ICP etching technics, should
The side wall of blank structure of the ledge structure 105 of step formation can reach 40 ° with the angle of the bonded substrate 107
~45 °.In the step, the GaN for being located at Cutting Road region thoroughly is not carved in ICP etching processes completely, Cutting Road region does not have
Metal splashes the generation of thing, thus metal will not will not be produced in the side wall of the ledge structure 105 splashes thing, the Step-edge Junction
Electric leakage will not occur for the side wall of structure 105 or ESD punctures electric leakage.
In step 7) in, S7 steps and Fig. 9 in Fig. 1 are referred to, the mask layer 108 is removed, and use wet etching
Technique removes the GaN for remaining in Cutting Road region, while forming ledge structure 105.
The GaN for remaining in Cutting Road region is removed as an example, being etched using hot acid solution, the hot acid solution can be heating
To the H of certain temperature2SO4With H3PO4Mixed solution；H can be adjusted according to different epitaxy techniques2SO4With H3PO4's
H in mixed solution2SO4With H3PO4With the when H2SO4With H3PO4Mixed solution temperature, to control GaN
The speed of sideetching.In one example, H2SO4With H3PO4Mol ratio be 3:1.Wet-etching technology is removed and remained in
After the GaN in Cutting Road region, the N-GaN layers 102, the multiple quantum well layer 103 and the P-GaN layers 104 of reservation
Collectively form the ledge structure 105.The side wall of the ledge structure 105 ultimately formed can with the angle of bonded substrate 107
To reach 50 °~70 °, the ability that the anti-ESD of side wall of the ledge structure 105 punctures can be greatly increased.
In step 8) in, S8 steps and Figure 10 in Fig. 1 are referred to, it is thick to carry out surface to the surface of N-GaN layers 102
Change, form roughening micro-structural 109.
As an example, carrying out surface coarsening to the surface of N-GaN layers 102 using wet corrosion technique, make N-GaN layers 102
Surface forms pyramid roughening micro-structural 109, and the etchant solution that the wet corrosion technique is used includes KOH and H3PO4
In one kind or its mixed solution.In the present embodiment, the etchant solution that the wet corrosion technique is used is H3PO4。
In step 9) in, S9 steps and Figure 11 in Fig. 1 are referred to, the table of N-GaN layers 102 after surface coarsening
Face prepares N electrode 110.
As an example, preparing the N electrode 110, the N electrode 110 on the surface of N-GaN layers 102 using vapour deposition method
Ni/Au layers, Al/Ti/Pt/Au layers, Ti/Al/Ni/Au layers, Cr/Al/Ti/Pt/Au layers or Cr/Pt/Au layers can be used.
Embodiment two
Please continue to refer to Figure 11, the present embodiment also provides a kind of vertical LED chip structure, and the vertical LED chip structure is adopted
It is prepared with the preparation method described in embodiment one, the vertical LED chip structure includes：Bonded substrate 107, according to
The secondary P electrode 106 being laminated on the bonded substrate 107, P-GaN layers 104, multiple quantum well layer 103 and N-GaN
Layer 102, and the N electrode 110 positioned at the surface of N-GaN layers 102；The P-GaN layers 104, the MQW
The 103 and N-GaN of layer layers 102 form ledge structure 105, the side wall of the ledge structure 105 and the bonded substrate 107
Between angle be 50 °~70 °；The surface of N-GaN layers 102 is formed with roughening micro-structural 109.
As an example, the bonded substrate 107 includes one kind in Si substrates, W/Cu substrates and Mo/Cu substrates.In this reality
Apply in example, the bonded substrate 107 is W/Cu substrates, can be with because W/Cu substrates have higher conduction and thermal conductivity
Greatly improve the radiating efficiency of LED chip.
As an example, the P electrode 106 includes ITO nesa coating 1061, reflecting layer 1062 and metal bonding layer 1063,
The metal bonding layer 1063 is located at the surface of bonded substrate 107, and the reflecting layer 1062 is located at the metal bonding layer 1063
Surface, the ITO nesa coating 1061 is embedded in the reflecting layer 1062, and surface and the formation ohm of P-GaN layers 104
Contact.
As an example, the material of the metal bonding layer 107 can be to include Cr and Pt inert metal.
As an example, it is described roughening micro-structural 109 can be but be not limited only to pyramid roughening micro-structural.
As an example, the N electrode 110 can using Ni/Au layers, Al/Ti/Pt/Au layers, Ti/Al/Ni/Au layers,
Cr/Al/Ti/Pt/Au layers or Cr/Pt/Au layers.
As described above, the present invention provides a kind of vertical LED chip structure and preparation method thereof, the preparation method includes following step
Suddenly：1) Sapphire Substrate is provided, UID-GaN layers, N-GaN layers, MQW is grown successively in the Sapphire Substrate
Layer and P-GaN layers；2) P electrode is formed on described P-GaN layers；3) provide bonded substrate, by the bonded substrate with
Step 2) obtained structure is bonded together, and the surface of the P electrode and the surface of the bonded substrate are brought into close contact；4)
Peel off the Sapphire Substrate；5) described UID-GaN layers is removed；6) corresponding to the region that subsequently form ledge structure
The N-GaN layer surfaces formation mask layer, according to the mask layer, removes part using ICP etching technics and is located at Cutting Road area
The GaN in domain；7) mask layer is removed, and the GaN for remaining in Cutting Road region is removed using wet-etching technology, simultaneously
Form ledge structure；8) surface coarsening is carried out to the N-GaN layer surfaces, forms roughening micro-structural；9) after surface coarsening
The N-GaN layer surfaces prepare N electrode.The present invention is first depending on mask layer and is located at using ICP etching technics removal part
The GaN in Cutting Road region, then removes the GaN for remaining in Cutting Road region, and form platform simultaneously using wet-etching technology again
Stage structure, the GaN in Cutting Road region is located at due to not carved completely in ICP etching processes, Cutting Road region does not have metal thoroughly
The generation of thing is splash, the side wall of ledge structure will not produce electric leakage or ESD punctures electric leakage；Meanwhile, prepared using the preparation method
The side wall of ledge structure and the angle of bonded substrate can reach 50 °~70 °, the anti-ESD of side wall of ledge structure can be greatly increased
The ability punctured.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any to be familiar with this skill
The personage of art all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Therefore, such as
Those of ordinary skill in the art without departing from disclosed spirit with completed under technological thought all etc.
Modifications and changes are imitated, should be covered by the claim of the present invention.
Claims (15)
1. a kind of preparation method of vertical LED chip structure, it is characterised in that the preparation method comprises the following steps：
1) Sapphire Substrate is provided, UID-GaN layers, N-GaN layers, volume is grown successively in the Sapphire Substrate
Sub- well layer and P-GaN layers；
2) P electrode is formed on described P-GaN layers；
3) bonded substrate being provided, by the bonded substrate and step 2) obtained structure is bonded together, and the P is electric
The surface of pole and the surface of the bonded substrate are brought into close contact；
4) Sapphire Substrate is peeled off；
5) described UID-GaN layers is removed；
6) in the N-GaN layer surfaces formation mask layer corresponding to the region that subsequently form ledge structure, according to institute
Mask layer is stated, the GaN that part is located at Cutting Road region is removed using ICP etching technics；
7) mask layer is removed, and the GaN for remaining in Cutting Road region is removed using wet-etching technology, is formed simultaneously
Ledge structure；
8) surface coarsening is carried out to the N-GaN layer surfaces, forms roughening micro-structural；
9) the N-GaN layer surfaces after surface coarsening prepare N electrode.
2. the preparation method of vertical LED chip structure according to claim 1, it is characterised in that：Step 2) in, including
Following steps：
2-1) in the ITO nesa coating of P-GaN layer surfaces formation Ohmic contact；
2-2) reflecting layer, ITO nesa coating described in the reflecting layer covers are formed on the ITO nesa coating surface；
2-3) in the reflection layer surface formation metal bonding layer, the metal bonding layer coats the reflecting layer.
3. the preparation method of vertical LED chip structure according to claim 2, it is characterised in that：Step 2-3) in, it is described
The material of metal bonding layer is inert metal.
4. the preparation method of vertical LED chip structure according to claim 1, it is characterised in that：Step 3) in, it is described
Bonded substrate includes one kind in Si substrates, W/Cu substrates and Mo/Cu substrates.
5. the preparation method of vertical LED chip structure according to claim 1, it is characterised in that：Step 4) in, use
Laser lift-off peels off the Sapphire Substrate.
6. the preparation method of vertical LED chip structure according to claim 1, it is characterised in that：Step 5) in, use
ICP etching technics removes described UID-GaN layers, and the etching gas that the ICP etching methods are used include Cl2And BCl3's
A kind of or its mixed gas.
7. the preparation method of vertical LED chip structure according to claim 1, it is characterised in that：Step 6) in, it is described
Mask layer is SiO2Mask layer.
8. the preparation method of vertical LED chip structure according to claim 1, it is characterised in that：Step 7) in, formed
The ledge structure side wall and bonded substrate between angle be 50 °~70 °.
9. the preparation method of vertical LED chip structure according to claim 1, it is characterised in that：Step 7) in, wet method
The etchant solution used in etching process is H2SO4With H3PO4Mixed solution.
10. the preparation method of vertical LED chip structure according to claim 1, it is characterised in that：Step 8) use
Wet corrosion technique carries out surface coarsening to the N-GaN layer surfaces, makes the N-GaN layer surfaces formation pyramid thick
Change micro-structural, the etchant solution that the wet corrosion technique is used includes KOH and H3PO4In one kind or its mixed solution.
11. a kind of vertical LED chip structure, it is characterised in that the vertical LED chip structure includes：Bonded substrate, according to
The secondary P electrode being laminated on the bonded substrate, P-GaN layers, multiple quantum well layer and N-GaN layers, and be located at
The N electrode of the N-GaN layer surfaces；Described P-GaN layers, described multiple quantum well layer and the N-GaN layers of formation platform
Stage structure, the angle between the side wall and the bonded substrate of the ledge structure is 50 °~70 °；The N-GaN layer surfaces
It is formed with roughening micro-structural.
12. vertical LED chip structure according to claim 11, it is characterised in that：The bonded substrate is served as a contrast including Si
One kind in bottom, W/Cu substrates and Mo/Cu substrates.
13. vertical LED chip structure according to claim 11, it is characterised in that：The P electrode includes transparent
Conducting film, reflecting layer and metal bonding layer, the metal bonding layer are located at the bonded substrate surface, and the reflecting layer is located at
The metal bonding layer surface, the ITO nesa coating is embedded in the reflecting layer, and surface and P-GaN layers of formation
Ohmic contact.
14. vertical LED chip structure according to claim 13, it is characterised in that：The material of the metal bonding layer is
Inert metal.
15. vertical LED chip structure according to claim 11, it is characterised in that：The roughening micro-structural is pyramid
Shape is roughened micro-structural.
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| CN114914310A (en) * | 2021-02-07 | 2022-08-16 | 中移(苏州)软件技术有限公司 | Gallium nitride device, manufacturing method thereof and underwater communication system |
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| CN105047777A (en) * | 2015-08-26 | 2015-11-11 | 映瑞光电科技(上海)有限公司 | Light-emitting diode (LED) vertical chip structure with coarsened side wall and fabrication method of LED vertical chip structure |
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Application publication date: 20170808 |