CN107026226A - Vertical LED chip structure with reflecting effect Cutting Road and preparation method thereof - Google Patents
Vertical LED chip structure with reflecting effect Cutting Road and preparation method thereof Download PDFInfo
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- CN107026226A CN107026226A CN201610066343.7A CN201610066343A CN107026226A CN 107026226 A CN107026226 A CN 107026226A CN 201610066343 A CN201610066343 A CN 201610066343A CN 107026226 A CN107026226 A CN 107026226A
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- 238000005530 etching Methods 0.000 claims abstract description 47
- 230000004888 barrier function Effects 0.000 claims abstract description 29
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 25
- 239000010980 sapphire Substances 0.000 claims abstract description 25
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
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Abstract
The present invention provides a kind of vertical LED chip structure with reflecting effect Cutting Road and preparation method thereof, including：1）Sapphire Substrate is provided, in growing UID-GaN layers, N-GaN layers, multiple quantum well layer and P-GaN layers in Sapphire Substrate successively；2）P-GaN layer surfaces formation etching barrier layer in corresponding to the edge and Cutting Road region that subsequently form ledge structure；3）In P-GaN layers and etch stopper layer surface formation P electrode；4）Bonded substrate is provided, by bonded substrate and step 3）Obtained structure is bonded together；5）Peel off Sapphire Substrate；6）Remove UID-GaN layers；7）Surface coarsening is carried out to N-GaN layer surfaces, roughening micro-structural is formed；8）The GaN in Cutting Road region is removed using ICP etching technics, while forming ledge structure；9）N electrode is prepared in the N-GaN layer surfaces after surface coarsening.Invention increases the reflecting effect in ledge structure edge and Cutting Road region in vertical LED chip structure, the light-out effect of vertical LED chip structure is considerably increased.
Description
Technical field
The invention belongs to field of semiconductor illumination, more particularly to a kind of vertical LED chip structure with reflecting effect Cutting Road
And preparation method thereof.
Background technology
Compared to traditional positive assembling structures of GaN base LED, vertical stratification has good heat dissipation, can carry high current, lights strong
Degree is high, power consumption is small, long lifespan the advantages of, be widely used in general illumination, Landscape Lighting, special lighting, automotive lighting
Deng field, the solution as generation high-power GaN-based LED great potential, just more and more paid close attention to by industry and
Research.
Vertical LED chip structure is by bonding chip or galvanoplastic, with reference to techniques such as laser lift-offs, by GaN base epitaxial structure
It is transferred to from Sapphire Substrate on the good metal of thermal conductivity or semiconductor substrate materials, the electrode knot being distributed above and below formation
Structure so that electric current flows vertically through whole device.After bonding chip, laser lift-off, utilize inductive coupling plasma (ICP)
Deep etching process etches the GaN in chip cutting road totally, while ledge structure is formed, then with KOH or NaOH solution
N-GaN layer surfaces are roughened, and in N-GaN layers of coarse surface formation N electrode.
However, in traditional vertical LED chip structure, reflecting layer is Ag speculums, because Ag speculums are asked in the presence of diffusion
Topic, can be by the size of Ag speculums in order to avoid the performance of the diffusion couple vertical LED chip of Ag speculums is impacted
In institute to ledge structure, i.e., the size of Ag speculums can be less than the size of ledge structure, so, will cause vertical LED core
The edge and Cutting Road areflexia effect of chip architecture so that the light extraction efficiency of vertical LED chip is substantially reduced.
The content of the invention
The shortcoming of prior art, has the vertical of reflecting effect Cutting Road it is an object of the invention to provide a kind of in view of the above
LED chip structure and preparation method thereof, for solve in the prior art due to reflecting layer size be less than ledge structure size and
The problem of light extraction efficiency of caused vertical LED chip structure is relatively low.
In order to achieve the above objects and other related objects, the present invention provides a kind of vertical LED chip with reflecting effect Cutting Road
The preparation method of structure, the preparation method comprises the following steps：
1) Sapphire Substrate is provided, in growing UID-GaN layers, N-GaN layers, MQW in the Sapphire Substrate successively
Layer and P-GaN layers；
2) the P-GaN layer surfaces formation etching in corresponding to the edge and Cutting Road region that subsequently form ledge structure
Barrier layer；
3) in described P-GaN layers and etch stopper layer surface formation P electrode；
4) bonded substrate being provided, by the bonded substrate and step 3) obtained structure is bonded together, and the P electrode
Surface and the surface of the bonded substrate are brought into close contact；
5) Sapphire Substrate is peeled off；
6) described UID-GaN layers is removed；
7) surface coarsening is carried out to the N-GaN layer surfaces, forms roughening micro-structural；
8) GaN in Cutting Road region is removed using ICP etching technics, while forming ledge structure；
9) N electrode is prepared in the N-GaN layer surfaces after surface coarsening.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure with reflecting effect Cutting Road of the present invention, step
It is rapid 2) in, the etching barrier layer be SiO2Layer.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure with reflecting effect Cutting Road of the present invention, step
It is rapid 3) to comprise the following steps：
3-1) in described P-GaN layers and the ITO nesa coating of etch stopper layer surface formation Ohmic contact；
3-2) reflecting layer, ITO nesa coating described in the reflecting layer covers are formed in the ITO nesa coating surface；
3-3) in the reflecting layer and etch stopper layer surface formation metal bonding layer.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure with reflecting effect Cutting Road of the present invention, step
Rapid 3-3) in, the metal bonding layer includes Cr layers and Al layers, wherein, Cr layers of thickness is 5 angstroms~50 angstroms, Al layers
Thickness is more than 2000 angstroms.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure with reflecting effect Cutting Road of the present invention, step
It is rapid 4) described in bonded substrate include Si substrates, W/Cu substrates and Mo/Cu substrates in one kind.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure with reflecting effect Cutting Road of the present invention, step
It is rapid that the Sapphire Substrate 5) is peeled off using laser lift-off.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure with reflecting effect Cutting Road of the present invention, step
It is rapid 6) in, remove described UID-GaN layer using ICP etching technics, the etching gas of ICP etching methods use include
Cl2And BCl3One kind or its mixed gas.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure with reflecting effect Cutting Road of the present invention, step
It is rapid that surface coarsening 7) is carried out to the N-GaN layer surfaces using wet corrosion technique, the N-GaN layer surfaces is formed golden word
Turriform is roughened micro-structural, and the etchant solution that the wet corrosion technique is used includes KOH and H3PO4In one kind or its mixing
Solution.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure with reflecting effect Cutting Road of the present invention, step
It is rapid 8) and step 9) between, be also included in the surface of the ledge structure and side wall and the exposed etch stopper layer surface shape
Into passivation layer, and the step of the passivation layer corresponds to the position formation opening that subsequently form N electrode, the opening exposure
Go out described N-GaN layers.
It is used as a kind of preferred scheme of the preparation method of the vertical LED chip structure with reflecting effect Cutting Road of the present invention, step
It is rapid 9) after, the surface and side wall and the exposed etch stopper layer surface for being also included in the exposed ledge structure are formed
The step of passivation layer.
The present invention also provides a kind of vertical LED chip structure with reflecting effect Cutting Road, described to have reflecting effect Cutting Road
Vertical LED chip structure include：Bonded substrate；Stack gradually P electrode on the bonded substrate, P-GaN layers,
Multiple quantum well layer and N-GaN layers, described P-GaN layers, described multiple quantum well layer and the N-GaN layers of formation ledge structure；
The etching barrier layer on P electrode surface in ledge structure edge and Cutting Road region；And positioned at the N-GaN layer surfaces
N electrode；The N-GaN layer surfaces are formed with roughening micro-structural.
It is used as a kind of preferred scheme of the vertical LED chip structure with reflecting effect Cutting Road of the present invention, the bonded substrate
Including one kind in Si substrates, W/Cu substrates and Mo/Cu substrates.
It is used as a kind of preferred scheme of the vertical LED chip structure with reflecting effect Cutting Road of the present invention, the P electrode bag
ITO nesa coating, reflecting layer and metal bonding layer are included, the metal bonding layer is located at the bonded substrate surface, described anti-
Layer is penetrated positioned at the metal bonding layer surface, the ITO nesa coating is embedded in the reflecting layer, and surface and P-GaN shapes
Into Ohmic contact.
It is used as a kind of preferred scheme of the vertical LED chip structure with reflecting effect Cutting Road of the present invention, the metal bonding
Layer includes Cr layers and Al layers, wherein, Cr layers of thickness is more than 2000 angstroms for 5 angstroms~50 angstroms, Al layers of thickness.
It is used as a kind of preferred scheme of the vertical LED chip structure with reflecting effect Cutting Road of the present invention, the micro- knot of the roughening
Structure is that pyramid is roughened micro-structural.
It is used as a kind of preferred scheme of the vertical LED chip structure with reflecting effect Cutting Road of the present invention, in addition to passivation
Layer, the passivation layer, which is located in the etch stopper layer surface and the side wall of the ledge structure and surface, the passivation layer, to be formed
There is opening, the opening exposes the N-GaN layers of roughening, and the N electrode is located at the N-GaN in the opening
Layer surface.
As described above, vertical LED chip structure with reflecting effect Cutting Road of the present invention and preparation method thereof, with following
Beneficial effect：The present invention is by forming etching resistance in the edge and Cutting Road region of the ledge structure in vertical LED chip structure
Barrier, adds the reflecting effect in ledge structure edge and Cutting Road region in vertical LED chip structure, considerably increases vertical
The light-out effect of LED chip structure.
Brief description of the drawings
Fig. 1 is shown as the preparation side of the vertical LED chip structure with reflecting effect Cutting Road provided in the embodiment of the present invention one
The schematic flow sheet of method.
Fig. 2 to Figure 14 is shown as the vertical LED chip structure with reflecting effect Cutting Road provided in the embodiment of the present invention one
The structural representation that is presented of each step of preparation method.
Component label instructions
100 Sapphire Substrates
101 UID-GaN layers
102 N-GaN layers
103 multiple quantum well layers
104 P-GaN layers
105 ledge structures
106 P electrodes
1061 ITO nesa coatings
1062 reflecting layer
1063 metal bonding layers
107 bonded substrates
108 etching barrier layers
109 roughening micro-structurals
110 N electrodes
111 passivation layers
112 openings
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be as disclosed by this specification
Content understand easily the present invention other advantages and effect.The present invention can also add by way of a different and different embodiment
To implement or apply, the various details in this specification can also be based on different viewpoints and application, in the essence without departing from the present invention
God is lower to carry out various modifications or alterations.
Fig. 2 is referred to Figure 14.It should be noted that the diagram provided in the present embodiment only illustrates the present invention in a schematic way
Basic conception, though only display is with relevant component in the present invention rather than according to component count during actual implement, shape in diagram
And size is drawn, it is actual when implementing, and kenel, quantity and the ratio of each component can be a kind of random change, and its assembly layout
Kenel may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present invention provides a kind of preparation method of the vertical LED chip structure with reflecting effect Cutting Road, institute
Preparation method is stated at least to comprise the following steps：
1) Sapphire Substrate is provided, in growing UID-GaN layers, N-GaN layers, MQW in the Sapphire Substrate successively
Layer and P-GaN layers；
2) the P-GaN layer surfaces formation etching in corresponding to the edge and Cutting Road region that subsequently form ledge structure
Barrier layer；
3) in described P-GaN layers and etch stopper layer surface formation P electrode；
4) bonded substrate being provided, by the bonded substrate and step 3) obtained structure is bonded together, and the P electrode
Surface and the surface of the bonded substrate are brought into close contact；
5) Sapphire Substrate is peeled off；
6) described UID-GaN layers is removed；
7) surface coarsening is carried out to the N-GaN layer surfaces, forms roughening micro-structural；
8) GaN in Cutting Road region is removed using ICP etching technics, while forming ledge structure；
9) N electrode is prepared in the N-GaN layer surfaces after surface coarsening.
In step 1) in, the S1 steps and Fig. 2 to Fig. 3 in Fig. 1 are referred to there is provided Sapphire Substrate 100, in the indigo plant
UID-GaN layers 101, N-GaN layers 102, multiple quantum well layer 103 and P-GaN layers are grown on jewel substrate 100 successively
104。
As an example, preparing the UID-GaN layers 101, N-GaN layers 102, MQW using chemical vapor deposition method
103 and P-GaN of layer layers 104, the UID-GaN layers 101 are used as the cushion of the N-GaN layers 102, Ke Yi great
The big growth quality for improving GaN epitaxial light emission structures, so as to improve the luminous efficiency of light emitting diode.
As an example, grow the UID-GaN layers 101 successively in the surface of Sapphire Substrate 100, it is described N-GaN layers
102nd, before multiple quantum well layer 103 and the P-GaN layer 104, in addition to the Sapphire Substrate 100 is carried out
The step of cleaning, to remove the impurity on the surface of Sapphire Substrate 100, such as polymer, dust.
In step 2) in, refer to S2 steps and Fig. 4 in Fig. 1, in corresponding to the edge that subsequently form ledge structure and
The surface of P-GaN layers 104 in Cutting Road region forms etching barrier layer 108.
As an example, the table of P-GaN layers 104 in corresponding to the edge and Cutting Road region that subsequently form ledge structure
The specific method that face forms the etching barrier layer 108 is：First, SiO is deposited in the surface of N-GaN layers 1022Layer；
Secondly, in the SiO2Layer surface coats photoresist layer；Again, using the graphical photoresist layer of photoetching process, to define
Go out the shape of the etching barrier layer 108；Then, institute is etched using wet-etching technology according to the patterned photoresist layer
State SiO2Layer is to form the etching barrier layer 108；Finally, the photoresist layer is removed.
In step 3) in, S3 steps and Fig. 5 in Fig. 1 are referred to, in the P-GaN layers 104 and the etching barrier layer
108 surfaces form P electrode 106.
As an example, the step comprises the following steps：
The ITO nesa coating of Ohmic contact 3-1) is formed in the P-GaN layers 104 and the surface of the etching barrier layer 108
1061 are used as ohmic contact layer；Specifically, forming ohm in the P-GaN layers 104 and the surface of the etching barrier layer 108 and connecing
The specific method of the tactile ITO nesa coating 1061 is：First, using evaporation process in the P-GaN layers 104 and
The surface of etching barrier layer 108 deposits one layer of ITO layer；Secondly, photoresist layer is coated in the ITO layer surface, using light
The graphical photoresist layer of carving technology, to define the figure of the ITO nesa coating 1061；Then, according to described
Patterned photoresist layer etches the ITO layer to form the ITO nesa coating 1061；Finally, the photoresist is removed
Layer；
Reflecting layer 1062 3-2) is formed in the surface of ITO nesa coating 1061, the reflecting layer 1062 coats the ITO
Nesa coating 1061；Specifically, depositing the reflecting layer in the surface of ITO nesa coating 1061 using evaporation process
1062, the reflecting layer 1062 can be Ag reflecting layer, Ag/TiW/Pt reflecting layer or Ag/TiW reflecting layer, it is preferable that
In the present embodiment, the reflecting layer 1062 is Ag reflecting layer；The outside in the reflecting layer 1062 and the etching barrier layer 108
It is in contact；
3-3) metal bonding layer 1063 is formed in the reflecting layer 1062 and the surface of the etching barrier layer 108；Specifically, adopting
The metal bonding layer 1063 is formed in the reflecting layer 1062 and the surface of the etching barrier layer 108 with evaporation process, it is described
Metal bonding layer 1063 be metal structure, the metal bonding layer 1063 can for Cr/Al/Ti/Pt/Ti/Pt/Ti/Pt/Ni/Au layers,
Cr/Al/Ti/Pt/Ti/Pt/Ti/Pt/Ni layers or Cr/Al layers, it is preferable that in the present embodiment, the metal bonding layer 1063 is Cr/Al
Layer, wherein, Cr layers of thickness is more than 2000 angstroms for 5 angstroms~50 angstroms, Al layers of thickness.Metal bonding is used as using Cr/Al layers
Layer 1063, the metal bonding layer 1063 is P reflecting electrodes, and Al layers of thickness is far longer than Cr layers of thickness, it is ensured that
Al layers of reflecting effect, can greatly increase its reflection efficiency.
In step 4) in, the S4 steps and Fig. 6 in Fig. 1 are referred to there is provided bonded substrate 107, by the bonded substrate 107
With step 3) obtained structure is bonded together, and the surface of the P electrode 106 and the surface of the bonded substrate 107 are tight
It is closely connected to close.
As an example, the bonded substrate 107 includes one kind in Si substrates, W/Cu substrates and Mo/Cu substrates.In this reality
Apply in example, the bonded substrate 107 is W/Cu substrates, can be with because W/Cu substrates have higher conduction and thermal conductivity
Greatly improve the radiating efficiency of LED chip.
As an example, the bonded substrate 107 and step 3) after obtained structure is bonded together, the metal bonding layer
1063 surface and the surface of the bonded substrate 107 are brought into close contact.
In step 5) in, S5 steps and Fig. 7 in Fig. 1 are referred to, the Sapphire Substrate 100 is peeled off.
The Sapphire Substrate 100 is peeled off as an example, can use but be not limited only to laser lift-off.
In step 6) in, S6 steps and Fig. 8 in Fig. 1 are referred to, the UID-GaN layers 101 are removed.
As an example, removing the UID-GaN layers 101, the etching gas that the ICP etching methods are used using ICP etching methods
Including Cl2And BCl3One kind or its mixed gas.
In step 7) in, S7 steps and Fig. 9 in Fig. 1 are referred to, surface coarsening is carried out to the surface of N-GaN layers 102,
Form roughening micro-structural 109.
As an example, carrying out surface coarsening to the surface of N-GaN layers 102 using wet corrosion technique, make N-GaN layers 102
Surface forms pyramid roughening micro-structural 109, the etchant solution that the wet corrosion technique is used include KOH, NaOH and
H3PO4In one kind or its mixed solution.In the present embodiment, the etchant solution that the wet corrosion technique is used is H3PO4。
In step 8) in, S8 steps and Figure 10 in Fig. 1 are referred to, Cutting Road region is removed using ICP etching technics
GaN, while forming ledge structure 105.
As an example, the GaN for removing Cutting Road region using ICP etching technics is to remove Cutting Road using ICP etching technics
The N-GaN layers 102, the multiple quantum well layer 103 and the P-GaN layers 104 in region.
As an example, the Cutting Road region is the region of the both sides of ledge structure 105 described in Figure 10.
As an example, the GaN in Cutting Road region is removed using ICP etching methods, while forming the specific of the ledge structure 105
Method is：First, photoresist layer is coated in the surface of N-GaN layers 102, the thickness of the photoresist layer is about 8 μm；
Secondly, using the graphical photoresist layer of photoetching process, to define the shape at the top of ledge structure 105；Then,
Etched according to patterned photoresist layer and remove the N-GaN layers 102 being located in Cutting Road region, the multiple quantum well layer 103
And the P-GaN layers 104, the N-GaN layers 102, the multiple quantum well layer 103 and the P-GaN layers 104 of reservation
Collectively form the ledge structure 105；Finally, the photoresist layer is removed.
In step 9) in, S9 steps and Figure 11 in Fig. 1 are referred to, in the table of N-GaN layers 102 after surface coarsening
Face prepares N electrode 110.
As an example, preparing the N electrode 110, the N electrode 110 in the surface of N-GaN layers 102 using vapour deposition method
Ni/Au layers, Al/Ti/Pt/Au layers, Ti/Al/Ni/Au layers, Cr/Al/Ti/Pt/Au layers or Cr/Pt/Au layers can be used.
As an example, referring to Figure 12, step 9) after, also it is included in the surface and side of the exposed ledge structure 105
The step of wall and the exposed surface of the etching barrier layer 108 form passivation layer 111, the material of the passivation layer 111 can be
But it is not limited only to SiO2。
In another example, Figure 13 to Figure 14 is referred to, step 8 is performed) after, the table first in the ledge structure 105
Face forms passivation layer 111 with side wall and the exposed surface of the etching barrier layer 108, and corresponds to subsequently in the passivation layer 111
The position for forming N electrode 110 forms opening 112, and the opening 112 exposes the N-GaN layers 102, such as Figure 13
It is shown；Step 8 is then performed again), the N electrode 110 is prepared in the surface of N-GaN layers 102 in the opening 112,
As shown in figure 14.
Embodiment two
Please continue to refer to Figure 11, the present embodiment also provides a kind of vertical LED chip structure with reflecting effect Cutting Road, institute
State the vertical LED chip structure with reflecting effect Cutting Road to be prepared using the preparation method described in embodiment one, institute
Stating the vertical LED chip structure with reflecting effect Cutting Road includes：Bonded substrate 107；Stack gradually in the bonded substrate
P electrode 106, P-GaN layers 104, multiple quantum well layer 103 and N-GaN layers 102 on 107, the P-GaN layers 104,
The formation of multiple quantum well layer 103 and the N-GaN layer 102 ledge structure 105；Positioned at the edge of ledge structure 105 and cutting
The etching barrier layer 108 on the surface of P electrode 106 in road region；And the N electrode 110 positioned at the surface of N-GaN layers 102；
The surface of N-GaN layers 102 is formed with roughening micro-structural 109.
As an example, the bonded substrate 107 includes one kind in Si substrates, W/Cu substrates and Mo/Cu substrates.In this reality
Apply in example, the bonded substrate 107 is W/Cu substrates, can be with because W/Cu substrates have higher conduction and thermal conductivity
Greatly improve the radiating efficiency of LED chip.
As an example, the P electrode 106 includes ITO nesa coating 1061, reflecting layer 1062 and metal bonding layer 1063,
The metal bonding layer 1063 is located at the surface of bonded substrate 107, and the reflecting layer 1062 is located at the metal bonding layer 1063
Surface, the ITO nesa coating 1061 is embedded in the reflecting layer 1062, and surface and the formation ohm of P-GaN layers 104
Contact.
As an example, the metal bonding layer 1063 is metal structure, the metal bonding layer 1063 can be
Cr/Al/Ti/Pt/Ti/Pt/Ti/Pt/Ni/Au layers, Cr/Al/Ti/Pt/Ti/Pt/Ti/Pt/Ni layers or Cr/Al layers, it is preferable that in the present embodiment,
The metal bonding layer 1063 is Cr/Al layers, wherein, Cr layers of thickness is more than 2000 for 5 angstroms~50 angstroms, Al layers of thickness
Angstrom.Using Cr/Al layers as metal bonding layer 1063, the metal bonding layer 1063 is P reflecting electrodes, and Al layers of thickness
Degree is far longer than Cr layers of thickness, it is ensured that Al layers of reflecting effect, can greatly increase its reflection efficiency.
As an example, it is described roughening micro-structural 109 can be but be not limited only to pyramid roughening micro-structural.
As an example, the N electrode 110 can use Ti/Al/Ni/Au layers, Cr/Al/Ti/Pt/Au layers or Cr/Pt/Au layers.
As an example, please continue to refer to Figure 12, the vertical LED chip structure with reflecting effect Cutting Road also includes blunt
Change layer 111, the passivation layer 111 is located at the surface of etching barrier layer 108 and the side wall of the ledge structure 105 and surface,
Opening is formed with the passivation layer 111, described be open exposes the N-GaN layers 102 of roughening, the N electrode 110
The surface of N-GaN layers 102 in the opening.
As described above, the present invention provides a kind of vertical LED chip structure with reflecting effect Cutting Road and preparation method thereof, institute
Preparation method is stated to comprise the following steps：1) provide Sapphire Substrate, in grown successively in the Sapphire Substrate UID-GaN layers,
N-GaN layers, multiple quantum well layer and P-GaN layers；2) in corresponding to the edge and Cutting Road area that subsequently form ledge structure
P-GaN layer surfaces formation etching barrier layer in domain；3) formed in described P-GaN layers and the etch stopper layer surface
P electrode；4) bonded substrate being provided, by the bonded substrate and step 3) obtained structure is bonded together, and the P is electric
The surface of pole and the surface of the bonded substrate are brought into close contact；5) Sapphire Substrate is peeled off；6) UID-GaN is removed
Layer；7) surface coarsening is carried out to the N-GaN layer surfaces, forms roughening micro-structural；8) removed and cut using ICP etching technics
The GaN in region is cut, while forming ledge structure；9) N electrode is prepared in the N-GaN layer surfaces after surface coarsening.
The present invention is increased by forming etching barrier layer in the edge and Cutting Road region of the ledge structure in vertical LED chip structure
The reflecting effect in ledge structure edge and Cutting Road region, considerably increases vertical LED chip in vertical LED chip structure
The light-out effect of structure.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any to be familiar with this skill
The personage of art all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Therefore, such as
Those of ordinary skill in the art without departing from disclosed spirit with completed under technological thought all etc.
Modifications and changes are imitated, should be covered by the claim of the present invention.
Claims (16)
1. a kind of preparation method of the vertical LED chip structure with reflecting effect Cutting Road, it is characterised in that the preparation method
Comprise the following steps：
1) Sapphire Substrate is provided, in growing UID-GaN layers, N-GaN layers, volume in the Sapphire Substrate successively
Sub- well layer and P-GaN layers；
2) the P-GaN layer surfaces formation in corresponding to the edge and Cutting Road region that subsequently form ledge structure is carved
Lose barrier layer；
3) in described P-GaN layers and etch stopper layer surface formation P electrode；
4) bonded substrate being provided, by the bonded substrate and step 3) obtained structure is bonded together, and the P is electric
The surface of pole and the surface of the bonded substrate are brought into close contact；
5) Sapphire Substrate is peeled off；
6) described UID-GaN layers is removed；
7) surface coarsening is carried out to the N-GaN layer surfaces, forms roughening micro-structural；
8) GaN in Cutting Road region is removed using ICP etching technics, while forming ledge structure；
9) N electrode is prepared in the N-GaN layer surfaces after surface coarsening.
2. the preparation method of the vertical LED chip structure according to claim 1 with reflecting effect Cutting Road, its feature exists
In：Step 2) in, the etching barrier layer is SiO2Layer.
3. the preparation method of the vertical LED chip structure according to claim 1 with reflecting effect Cutting Road, its feature exists
In：Step 3) comprise the following steps：
3-1) in described P-GaN layers and the ITO nesa coating of etch stopper layer surface formation Ohmic contact；
3-2) reflecting layer, ITO nesa coating described in the reflecting layer covers are formed in the ITO nesa coating surface；
3-3) in the reflecting layer and etch stopper layer surface formation metal bonding layer.
4. the preparation method of vertical LED chip structure according to claim 3, it is characterised in that：Step 3-3) in, it is described
Metal bonding layer includes Cr layers and Al layers, wherein, Cr layers of thickness is more than 2000 for 5 angstroms~50 angstroms, Al layers of thickness
Angstrom.
5. the preparation method of the vertical LED chip structure according to claim 1 with reflecting effect Cutting Road, its feature exists
In：Step 4) described in bonded substrate include Si substrates, W/Cu substrates and Mo/Cu substrates in one kind.
6. the preparation method of the vertical LED chip structure according to claim 1 with reflecting effect Cutting Road, its feature exists
In：Step 5) Sapphire Substrate is peeled off using laser lift-off.
7. the preparation method of vertical LED chip structure according to claim 1, it is characterised in that：Step 6) in, use
ICP etching technics removes described UID-GaN layers, and the etching gas that the ICP etching methods are used include Cl2And BCl3's
A kind of or its mixed gas.
8. the preparation method of the vertical LED chip structure according to claim 1 with reflecting effect Cutting Road, its feature exists
In：Step 7) surface coarsening is carried out to the N-GaN layer surfaces using wet corrosion technique, make the N-GaN layers of table
Face forms pyramid roughening micro-structural, and the etchant solution that the wet corrosion technique is used includes KOH and H3PO4In
A kind of or its mixed solution.
9. the preparation method of the vertical LED chip structure according to claim 1 with reflecting effect Cutting Road, its feature exists
In：Step 8) and step 9) between, the surface and side wall and the exposed etching for being also included in the ledge structure hinder
Barrier surface forms passivation layer, and the step of the passivation layer corresponds to the position formation opening that subsequently form N electrode,
The opening exposes described N-GaN layers.
10. the preparation method of the vertical LED chip structure according to claim 1 with reflecting effect Cutting Road, it is special
Levy and be：Step 9) after, the surface and side wall and the exposed etching for being also included in the exposed ledge structure hinder
The step of barrier surface forms passivation layer.
11. a kind of vertical LED chip structure with reflecting effect Cutting Road, it is characterised in that described to be cut with reflecting effect
The vertical LED chip structure cut includes：Bonded substrate；Stack gradually P electrode on the bonded substrate, P-GaN
Layer, multiple quantum well layer and N-GaN layers, described P-GaN layers, described multiple quantum well layer and the N-GaN layers of formation platform
Stage structure；The etching barrier layer on P electrode surface in ledge structure edge and Cutting Road region；And positioned at described
The N electrode of N-GaN layer surfaces；The N-GaN layer surfaces are formed with roughening micro-structural.
12. the vertical LED chip structure according to claim 11 with reflecting effect Cutting Road, it is characterised in that：Institute
Stating bonded substrate includes one kind in Si substrates, W/Cu substrates and Mo/Cu substrates.
13. the vertical LED chip structure according to claim 11 with reflecting effect Cutting Road, it is characterised in that：Institute
Stating P electrode includes ITO nesa coating, reflecting layer and metal bonding layer, and the metal bonding layer is located at the bonding lining
Basal surface, the reflecting layer is located at the metal bonding layer surface, and the ITO nesa coating is embedded in the reflecting layer,
And surface and P-GaN formation Ohmic contacts.
14. the vertical LED chip structure according to claim 11 with reflecting effect Cutting Road, it is characterised in that：Institute
Metal bonding layer is stated including Cr layers and Al layers, wherein, Cr layers of thickness is more than 2000 for 5 angstroms~50 angstroms, Al layers of thickness
Angstrom.
15. the vertical LED chip structure according to claim 11 with reflecting effect Cutting Road, it is characterised in that：It is described
It is that pyramid is roughened micro-structural to be roughened micro-structural.
16. the vertical LED chip structure according to claim 11 with reflecting effect Cutting Road, it is characterised in that：Also wrap
Passivation layer is included, the passivation layer is located at the etch stopper layer surface and the side wall of the ledge structure and surface, the passivation
Opening is formed with layer, described be open exposes the N-GaN layers of roughening, and the N electrode is located in the opening
The N-GaN layer surfaces.
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| CN113130718A (en) * | 2021-02-24 | 2021-07-16 | 华灿光电（浙江）有限公司 | Flip light-emitting diode chip and manufacturing method thereof |
| CN114188453A (en) * | 2021-11-30 | 2022-03-15 | 重庆康佳光电技术研究院有限公司 | Vertical LED chip, preparation method thereof, LED array and display panel |
| CN116759513A (en) * | 2023-08-14 | 2023-09-15 | 南昌凯捷半导体科技有限公司 | Mirror surface cladding structure reverse polarity red light LED chip and manufacturing method thereof |
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| CN116759513A (en) * | 2023-08-14 | 2023-09-15 | 南昌凯捷半导体科技有限公司 | Mirror surface cladding structure reverse polarity red light LED chip and manufacturing method thereof |
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