CN108365078A - A kind of 3D through-holes superstructure LED chip and preparation method thereof - Google Patents

A kind of 3D through-holes superstructure LED chip and preparation method thereof Download PDF

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Publication number
CN108365078A
CN108365078A CN201810027470.5A CN201810027470A CN108365078A CN 108365078 A CN108365078 A CN 108365078A CN 201810027470 A CN201810027470 A CN 201810027470A CN 108365078 A CN108365078 A CN 108365078A
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trepanning
layer
gan
insulating layer
electrode metal
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CN201810027470.5A
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CN108365078B (en
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李国强
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河源市众拓光电科技有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0095Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58Optical field-shaping elements
    • H01L33/60Reflective elements

Abstract

The invention discloses a kind of silicon substrate 3D through-holes superstructure LED chips and preparation method thereof; including growing n GaN layers, InGaN/GaN multiple quantum well layers and p GaN layers successively in epitaxial substrate; then mirror layer and reflector protective layer are prepared; and carry out trepanning; then insulating layer is prepared, then prepares the N metal electrodes and bonding layer metals in filling hole;Then growth substrates are removed, MESA raceway grooves and PA layers of preparation are carried out;Thereafter P electrode metal is prepared, the preparation of the vertical 3D perforation structures LED chip of complete silicon substrate is ultimately formed.The 3D through-holes superstructure also converts the 2D current expansion abilities of linear structure to 3D current expansion abilities, so that its current distribution uniformity is increased dramatically, light efficiency is substantially improved other than the advantages of veritcal linearity structure is inherited in perfection.

Description

A kind of 3D through-holes superstructure LED chip and preparation method thereof

Technical field

The present invention relates to LED manufacture technology field more particularly to a kind of 3D through-holes superstructure LED chip and its preparation sides Method.

Background technology

As LED is in the gradually application of lighting area, the requirement that white light LED light is imitated in market is higher and higher, at present the cities LED The GaN base veritcal linearity structure LED chip that emerges in large numbers of field, because it is with single side light extraction, good heat-sinking capability can bear big electricity Stream injection, cost are a series of advantages such as the part of positive assembling structure, gradually substitute process for sapphire-based horizontal structure LED core Piece becomes the preferred product in great power LED market.But veritcal linearity structure LED equally has the shortcomings that it, first, due to its N electrode It is placed in light-emitting surface, there are problems that serious electrode is in the light;Second, the electricity of current extending (CBL) manufacture under electrode wires Stream extended capability belongs to 2D levels, fails to form good uniform current expansion ability, secondly, adjacent C BL in entire epitaxial layer Line spacing is more than 200um, and the current expansion width of 2D levels also falls short of;Third, current expansion scarce capacity it is impossible to meet Its condition driven under supercurrent.And 3D through-hole superstructure chips are to coordinate the method for dry etching in epitaxial wafer using photoetching P-GaN is punched on surface, and hole extends to n-GaN, and metal electrode is accumulated in inner hole deposition.Therefore, around hole it is one 3D layers The current expansion in face is much better than the 2D current expansions of veritcal linearity structure;Secondly, the diameter in hole is about 10~60um, is much smaller than The width of about 200um between the adjacent electrode line of the surfaces linear structure n-GaN, the hole being evenly distributed can promote the surfaces n-GaN 2D current expansion abilities;So 3D through-holes superstructure in addition to perfection inherit veritcal linearity structure the advantages of other than, will also be linear The 2D current expansion abilities of structure are converted into 3D current expansion abilities, so that its current distribution uniformity is increased dramatically, light efficiency It is substantially improved.Second, excellent current expansion ability can carry out outstanding supercurrent driving capability to through-hole structure chip belt, surpass Electric current driving LED illumination has become development trend, and future will have more areas that will apply high-power LED illumination, such as automobile-used photograph It is bright, commercialization illumination, street lighting, Intelligent House Light etc..Therefore, surpass driving illumination have powerful market development foreground and Potentiality.

Although 3D through-hole superstructure LED chips are possessing so many advantage, still remain following defect:P-electrode Metal and n-electrode metal-insulator sex chromosome mosaicism;The pattern alignment problem of photoetching process in the processing procedure of hole;Protective layer metal real protection Effect and stress regulation and control problem;Hole side wall proof and electric leakage-proof safety problem;The problems such as aperture, hole shape, pitch of holes and distribution design.Cause It is the only way realized 3D through-hole superstructure LED chips and prepared that this, which solves above-mentioned problem, and realizes high-power, super driving The only way of LED lighting technology.

Invention content

For overcome the deficiencies in the prior art, one of the objects of the present invention is to provide a kind of 3D through-holes superstructure LED cores Piece, the advantages of veritcal linearity structure can not only be inherited, moreover it is possible to convert the 2D current expansion abilities of linear structure to 3D electric currents Extended capability, is substantially improved the current expansion ability of veritcal linearity structure, and then light extraction efficiency and supercurrent driving is substantially improved Ability.

The second object of the present invention is to provide a kind of preparation method of 3D through-holes superstructure LED chip, and flow is simple, at Product rate is high, is suitble to industrialized production, has good application prospect.

An object of the present invention adopts the following technical scheme that realization:

A kind of 3D through-holes superstructure LED chip, including stack gradually second insulating layer, n-GaN layers, InGaN/GaN it is more Quantum well layer, p-GaN layer, mirror layer, reflector protective layer, the first insulating layer, the first bonded layer, the second bonded layer, bonding Substrate and back of the body layer gold;

The first trepanning and the second trepanning are provided on the mirror layer, second trepanning is located at the mirror layer Edge;

The reflector protective layer is arranged on the mirror layer and covers the bottom and side wall of first trepanning, with And the bottom and side wall of covering second trepanning;It is provided with third trepanning and aisle in the reflector protective layer, described Up and down, the aisle circumferential direction ring is located in the reflector protective layer and across described for three trepannings and first trepanning Two trepannings;

The 4th trepanning is extended downward with along the third trepanning and the first trepanning, the 4th trepanning runs through the p- GaN layer and the InGaN/GaN multiple quantum well layers, the bottom of the 4th trepanning are set in n-GaN layers described;

First insulating layer is arranged in the reflector protective layer, and fills the third trepanning, the first trepanning, the Four trepannings and aisle;It is provided with the 5th trepanning on first insulating layer;5th trepanning and the third trepanning, first Trepanning and the 4th trepanning form fill area up and down, and the side wall of the fill area is coated with first insulating layer;Described N electrode metal is set in fill area;The bottom of the N electrode metal is in direct contact with described n-GaN layers;The N electrode metal It is inserted upwardly into first bonded layer;

Be provided with the 6th trepanning in the second insulating layer, the 6th trepanning extend radially through the second insulating layer, N-GaN layers, InGaN/GaN multiple quantum well layers and p-GaN layer;The upright projection area of 6th trepanning and second trepanning Upright projection area overlapping;P electrode metal is filled in the 6th trepanning;The P electrode metal is pierced by described second absolutely upwards Edge layer.

Further, first trepanning and second trepanning run through the mirror layer up and down;The third trepanning Aperture be less than first trepanning aperture.

Further, the mirror layer be nanometer Ag base reflecting mirror layer, nanometer Ag base reflecting layer include successively and If X layers, nanometer Ag layer and Y layers;Described X layers be ohmic contact layer, forming material Ni, Pt, Pd, Au, Pt, ITO, ZnO, AZO, GZO or graphene;Described Y layers is antioxidation coating, forming material Ni, Ti, Mg, Al, W, TiW, Au or Pt;The reflection The thickness of mirror layer is 25-500nm.

Further, the material of the reflector protective layer is one kind in TiW, Au, Cr, Mo, Al, Cu or arbitrary group It closes;The thickness of the reflector protective layer is 100-5000nm.

Further, the material of first insulating layer is titanium dioxide, silica or silicon nitride, first insulation The thickness of layer is 200-2000nm.

Further, first bonded layer and second bonded layer are Sn-Ni alloy-layers;First bonded layer Thickness be 500-9000nm, the thickness of second bonded layer is 300-50000nm.

Further, the bonded substrate is silicon substrate, Cu substrates, W substrates or flexible substrate.

Further, the N electrode metal is one or any group in Al, Ti, W, Au, Cr, Mo, Pt, Ag and ZnO It closes, the thickness of the N electrode metal is 200-10000nm.

Further, the P electrode metal is the one or any combination in Cr, Ni, Ti, TiW and Pt, the P electricity The thickness of pole metal is 200-8000nm.

The second object of the present invention adopts the following technical scheme that realization:

A kind of preparation method of 3D through-holes superstructure LED chip, including:

Epitaxial growth steps:Epitaxial substrate is taken, grows n-GaN layers, InGaN/GaN volumes successively in the epitaxial substrate Sub- well layer and p-GaN layer;

Opening step is deposited:Mirror layer is deposited in the p-GaN layer, after high annealing, on the mirror layer The first trepanning and the second trepanning are opened up, second trepanning is located at the edge of the mirror layer;

Prepare reflector protective layer step:Reflector protective layer is prepared on the mirror layer, and the speculum is protected Sheath covers the bottom and side wall of first trepanning, and the bottom and side wall of covering second trepanning;Then, described Third trepanning and aisle be set in reflector protective layer, the third trepanning with first trepanning up and down, the aisle Circumferential ring is located in the reflector protective layer and passes through second trepanning;

Prepare the 4th opening step:The 4th trepanning of setting is extended downwardly along the third trepanning and the first trepanning, described the Four trepannings run through the p-GaN layer and the InGaN/GaN multiple quantum well layers, and the bottom of the 4th trepanning is set to the n- In GaN layer;

Prepare the first insulating layer step:In the reflector protective layer and the third trepanning, the first trepanning, the 4th In trepanning and aisle be arranged the first insulating layer, on first insulating layer be arranged the 5th trepanning, the 5th trepanning with it is described Third trepanning, the first trepanning and the 4th trepanning form fill area up and down;

Prepare N electrode metal step:N electrode metal is set in the fill area, and the N electrode metal is pierced by institute upwards State the first insulating layer;

Prepare bonded layer, bonded substrate and back of the body layer gold step:The first bonded layer is formed on first insulating layer;Take key Substrate is closed, the second bonded layer is formed in the front of the bonded substrate, back of the body layer gold is formed at the back side of the bonded substrate;It connects It, first bonded layer and second bonded layer are mutually bonded fixation;

Remove epitaxial substrate step:The epitaxial substrate is removed;

Prepare second insulating layer step:Second insulating layer is prepared on n-GaN layers described, then in the second insulating layer The 6th trepanning of upper setting, the 6th trepanning extend radially through the second insulating layer, n-GaN layers, InGaN/GaN multiple quantum well layers And p-GaN layer;The upright projection area overlapping in the upright projection area and second trepanning of the 6th trepanning;

Prepare P electrode metal step:P electrode metal is filled in the 6th trepanning, the P electrode metal is pierced by upwards The second insulating layer.

Further, described outer using (111) face of the epitaxial substrate as epitaxial surface in the epitaxial growth steps It is silicon substrate, GaN substrate, Sapphire Substrate, tantalum strontium aluminate lanthanum substrate or lithium gallium oxide substrate to prolong substrate.

Further, in the vapor deposition step, the speculum is deposited using magnetron sputtering or electron beam evaporation process Layer;First trepanning and second trepanning are obtained using photoetching and wet etching method, when carrying out wet etching, the corruption of use Erosion liquid is ammonium hydroxide-dioxygen water mixed liquid or hydrochloric acid solution;The condition of high annealing is as follows:Annealing atmosphere is N2And O2Mixing Gas, N2With O2Volume ratio be 50:(1-50), temperature are 300-700 DEG C, time 10-600s.

Further, in the preparation reflector protective layer step, using magnetron sputtering technique or electron beam evaporation Technique obtains the mirror layer protective layer, and the third trepanning and the aisle are obtained using photoetching and lift-off techniques.

Further, in the 4th opening step of the preparation, using photoetching process and inductively coupled plasma etching Technique obtains the 4th trepanning, and when carrying out inductively coupled plasma etching technique, the power of top electrode is 200-900W, under The power of electrode is 80-500W, and etch rate is 15-100 angstroms per seconds.

Further, in the first insulating layer step of the preparation, first insulating layer is obtained using pecvd process, 5th trepanning is arranged on first insulating layer using etching process, corrosive liquid is BOE liquid.

Further, it in the preparation N electrode metal step, is filled out described using sputtering or electron beam evaporation process Fill filling N electrode metal in area.

Further, in the stripping epitaxial substrate step, institute is removed using the method for mechanical lapping and chemical attack State epitaxial substrate;When carrying out chemical attack, the corrosive liquid used is hydrofluoric acid, nitric acid, one kind of glacial acetic acid or arbitrary combination.

Further, in the preparation P electrode metal step, using sputtering or electron beam evaporation process described the P electrode metal is filled in six trepannings.

Further, further include roughening treatment step:After the epitaxial substrate is removed, dry etching processing is carried out, is made N-GaN layers of the back side is fully exposed;Then to the mixing hot solution using KOH and NaOH, or using KOH and The fusant of NaOH is to described n-GaN layers progress roughening treatment.

Compared with prior art, the beneficial effects of the present invention are:

(1) 3D through-holes superstructure LED chip provided by the present invention, in addition to perfection inherit veritcal linearity structure the advantages of it Outside, also the 2D current expansion abilities of linear structure are converted to 3D current expansion abilities, its current distribution uniformity is made to obtain greatly Width is promoted, and light efficiency is substantially improved.

(2) 3D through-holes superstructure LED chip provided by the present invention, excellent current expansion ability can give punching knot Structure chip belt carrys out outstanding supercurrent driving capability, and supercurrent driving LED illumination has become development trend, and future will have more necks Domain will apply high-power LED illumination, such as automobile lighting, commercialization illumination, street lighting, Intelligent House Light etc..

(3) 3D through-holes superstructure LED chip provided by the present invention, the first insulating layer can perfectly completely cut off the 5th and open N electrode metal and the reflector protective layer metal in hole and p-electrode metal, prevent short circuit;The first insulating layer can simultaneously The epitaxial layer side wall exposed in the 4th trepanning of perfect protection.

(4) 3D through-holes superstructure LED chip provided by the present invention, the first trepanning is can be perfect for subsequent reflection mirror It is coated among the reflector protective layer, reduces the electrical leakage problems caused by the diffusion of Ag.

(5) preparation method of 3D through-holes superstructure LED chip provided by the present invention, flow is simple, high yield rate, is suitble to Industrialized production has good application prospect.

Description of the drawings

The preparation flow figure for the 3D through-hole superstructure LED chips that Fig. 1 is provided by the embodiment of the present invention;

Structural representation after the 3D through-hole superstructure LED chip epitaxial growth steps that Fig. 2 is provided by the embodiment of the present invention Figure;

Structural representation after the 3D through-hole superstructure LED chips vapor deposition opening step that Fig. 3 is provided by the embodiment of the present invention Figure;

The 3D through-hole superstructure LED chips that Fig. 4 is provided by the embodiment of the present invention are tied after preparing reflector protective layer step Structure schematic diagram;

Fig. 5 is prepared the structure after the 4th opening step by the 3D through-hole superstructure LED chips that the embodiment of the present invention provides Schematic diagram;

Structure after 3D through-hole superstructure LED chips the first insulating layer step of preparation that Fig. 6 is provided by the embodiment of the present invention Schematic diagram;

Fig. 7 is prepared the structural representation after the 5th trepanning by the 3D through-hole superstructure LED chips that the embodiment of the present invention provides Figure;

Fig. 8 is prepared the structure after N electrode metal step by the 3D through-hole superstructure LED chips that the embodiment of the present invention provides Schematic diagram;

The 3D through-hole superstructure LED chips that Fig. 9 is provided by the embodiment of the present invention prepare bonded layer, bonded substrate and back of the body gold Structural schematic diagram after layer step;

The 3D through-hole superstructure LED chips stripping epitaxial substrate and prepare second absolutely that Figure 10 is provided by the embodiment of the present invention Structural schematic diagram after edge layer step;

The finished product schematic diagram for the 3D through-hole superstructure LED chips that Figure 11 is provided by the embodiment of the present invention;

Figure 12 is the optical output power mapping figures of conventional linear vertical structure;

Optical output power of the 3D through-hole superstructure LED chips that Figure 13 is provided by the embodiment of the present invention under same size Mapping schemes.

In figure:100, growth substrates;101, n-GaN layers;102, InGaN/GaN multiple quantum well layers;103, p-GaN layer; 104, mirror layer;105, the first trepanning;106, the second trepanning;107, reflector protective layer;108, third trepanning;109, it walks Road;110, the 4th trepanning;111, the first insulating layer;112, the 5th trepanning;113, N electrode metal;114, the first bonded layer;115、 Second insulating layer;116, the 6th trepanning;117, P electrode metal;200, bonded substrate;201, the second bonded layer;202, layer gold is carried on the back.

Specific implementation mode

In the following, in conjunction with attached drawing and specific implementation mode, the present invention is described further, it should be noted that not Under the premise of conflicting, new implementation can be formed between various embodiments described below or between each technical characteristic in any combination Example.

The embodiment of the invention discloses a kind of 3D through-holes superstructure LED chip and preparation method thereof, it is included in and is served as a contrast in extension N-shaped doping GaN film, InGaN/GaN multiple quantum wells are sequentially prepared on bottom, p-type adulterates GaN film.Then, in LED epitaxial wafer Surface uses magnetron sputtering or electron beam evaporation process, and prepared by matching standard photoetching process and standard lift-off processing procedures have hole The nanometer Ag base reflecting mirror of figure, reflector protective layer 107.It is prepared by standard photolithography process and dry method wet-etching technology MESA trepannings prepare insulating layer using pecvd process;Recycle standard photolithography process and magnetron sputtering or electron beam evaporation process Prepare the N metal electrodes and bonding layer metals in filling hole;LED epitaxial layers are transferred to the life of highly doped conduction using bonder On long substrate 100, and the machine of being thinned, chemical corrosion method is combined to remove old growth substrates 100;Followed by PECVD, ICP etc. Equipment carries out MESA raceway grooves and PA layers of preparation;Thereafter P is prepared again by standard photolithography process and dry method wet-etching technology Electrode pattern prepares P electrode metal 117 using magnetron sputtering or electron beam evaporation and lift-off techniques, ultimately forms complete The vertical 3D perforation structures LED chip of silicon substrate preparation.

The 3D through-holes superstructure that the embodiment of the present invention is provided is other than the advantages of veritcal linearity structure is inherited in perfection, also It converts the 2D current expansion abilities of linear structure to 3D current expansion abilities, its current distribution uniformity is made substantially to be carried It rises, light efficiency is substantially improved.Also, its excellent current expansion ability can carry out outstanding supercurrent to perforation structure chip belt and drive Kinetic force, supercurrent driving LED illumination have become development trend, and future will have more areas that will apply high-power LED illumination, Such as automobile lighting, commercial illumination, street lighting, Intelligent House Light.

More specifically, the 3D through-hole superstructure LED chips and preparation method thereof will be carried out below further detailed Description.Used raw material, equipment etc. can be obtained in addition to particular determination by buying pattern in the following embodiments.

Embodiment 1

As shown in figure 11, a kind of 3D through-holes superstructure LED chip, including stack gradually second insulating layer 115, n-GaN 101 (N-shaped doping GaN film) of layer, InGaN/GaN multiple quantum well layers 102, p-GaN layer 103 (p-type doping GaN film), reflection Mirror layer 104, reflector protective layer 107, the first insulating layer 111, the first bonded layer 114, the second bonded layer 201, bonded substrate 200 With back of the body layer gold 202;The first trepanning 105 and the second trepanning 106 are provided on mirror layer 104, the second trepanning 106 is located at speculum The edge of layer 104;Reflector protective layer 107 is arranged on mirror layer 104 and covers the bottom and side wall of the first trepanning 105, And the bottom and side wall of the second trepanning 106 of covering;Third trepanning 108 and aisle 109 are provided in reflector protective layer 107, Up and down, the circumferential ring in aisle 109 is located in reflector protective layer 107 and passes through second for third trepanning 108 and the first trepanning 105 Trepanning 106;The 4th trepanning 110 is extended downward with along third trepanning 108 and the first trepanning 105, the 4th trepanning 110 runs through p- The bottom of GaN layer 103 and InGaN/GaN multiple quantum well layers 102, the 4th trepanning 110 is set in n-GaN layers 101;First insulation Layer 111 is arranged in reflector protective layer 107, and fills third trepanning 108, the first trepanning 105, the 4th trepanning 110 and aisle 109;It is provided with the 5th trepanning 112 on the first insulating layer 111;5th trepanning 112 and third trepanning 108, the first trepanning 105 and 4th trepanning 110 forms fill area up and down, and the side wall of fill area is coated with the first insulating layer 111;N is set in fill area Electrode metal 113;The bottom of N electrode metal 113 is in direct contact with n-GaN layers 101;N electrode metal 113 is inserted upwardly into the first key Close layer 114;Be provided with the 6th trepanning 116 in second insulating layer 115, the 6th trepanning 116 extend radially through second insulating layer 115, N-GaN layers 101, InGaN/GaN multiple quantum well layers 102 and p-GaN layer 103;It is opened with second in the upright projection area of 6th trepanning 116 The upright projection area overlapping in hole 106;The filling P electrode metal 117 in the 6th trepanning 116;P electrode metal 117 is pierced by the upwards Two insulating layers 115.

Further, mirror layer 104 is nanometer Ag base reflecting mirror layer 104, and nanometer Ag base reflecting layer includes setting successively X layers, nanometer Ag layer and Y layers;X layers be ohmic contact layer, the high-work-function metals such as forming material Ni, Pt, Pd, Au, Pt or The high-permeabilities material such as TO, ZnO, AZO, GZO, graphene;Y layers are antioxidation coating, the oxyphies such as forming material Ni, Ti, Mg, Al The property lower metal of the lively types such as metal or W, TiW, Au, Pt;The thickness of mirror layer 104 is 25-500nm.

As further embodiment, the material of reflector protective layer 107 is one in TiW, Au, Cr, Mo, Al, Cu Kind or arbitrary combination;The thickness of reflector protective layer 107 is 100-5000nm.

As further embodiment, the material of the first insulating layer 111 is titanium dioxide, silica or silicon nitride, The thickness of first insulating layer 111 is 200-2000nm.

As further embodiment, the first bonded layer 114 and the second bonded layer 201 are Sn-Ni alloy-layers, instead of It is Sn-Au layers existing, bonding cost can be greatly reduced under the premise of ensureing bonding quality;The thickness of first bonded layer 114 is The thickness of 500-9000nm, the second bonded layer 201 are 300-50000nm.

As further embodiment, bonded substrate 200 is silicon substrate, Cu substrates, W substrates or flexible substrate.

As further embodiment, N electrode metal 113 is one in Al, Ti, W, Au, Cr, Mo, Pt, Ag and ZnO The thickness of kind or arbitrary combination, N electrode metal 113 is 200-10000nm.

As further embodiment, P electrode metal 117 is one or any group in Cr, Ni, Ti, TiW and Pt It closes, the thickness of P electrode metal 117 is 200-8000nm.

The 3D through-hole superstructure LED chips that the embodiment of the present invention is provided, the advantages of veritcal linearity structure is inherited in perfection Meanwhile also converting the 2D current expansion abilities of linear structure to 3D current expansion abilities, veritcal linearity structure is substantially improved Current expansion ability, and then light extraction efficiency and supercurrent driving capability is substantially improved.

Embodiment 2

As shown in figs. 1-11, a kind of preparation method of 3D through-holes superstructure LED chip, including:

Epitaxial growth steps:Epitaxial substrate is taken, grows n-GaN layers 101, InGaN/GaN volumes successively in epitaxial substrate Sub- well layer 102 and p-GaN layer 103;

Opening step is deposited:Mirror layer 104 is deposited in p-GaN layer 103, after high annealing, on mirror layer 104 The first trepanning 105 and the second trepanning 106 are opened up, the second trepanning 106 is located at the edge of mirror layer 104;

Prepare 107 step of reflector protective layer:Reflector protective layer 107 is prepared on mirror layer 104, and speculum is protected Sheath 107 covers the bottom and side wall of the first trepanning 105, and the bottom and side wall of the second trepanning 106 of covering;Then, anti- Penetrate and third trepanning 108 and aisle 109 be set on mirror protective layer 107, third trepanning 108 and the first trepanning 105 up and down, aisle 109 circumferential rings are located in reflector protective layer 107 and (i.e. reflector protective layer 107 coats mirror layer across the second trepanning 106 104, third trepanning 108 is located in the first trepanning 105, and the aperture of third trepanning 108 is less than the aperture of the first trepanning 105;It walks Road 109 was located at the edge of current structure, and circumferentially around one week;Aisle 109 is located inside the second trepanning 106);

Prepare 110 step of the 4th trepanning:The 4th trepanning of setting is extended downwardly along third trepanning 108 and the first trepanning 105 110, the 4th trepanning 110 runs through p-GaN layer 103 and InGaN/GaN multiple quantum well layers 102, and the bottom of the 4th trepanning 110 is set to (i.e. the 4th trepanning 110 forms in third trepanning 108 and the first trepanning 105 and continues to extend downwardly, the 4th in n-GaN layers 101 101) trepanning 110 does not run through n-GaN layers;

Prepare 111 step of the first insulating layer:In reflector protective layer 107 and third trepanning 108, the first trepanning 105, First insulating layer 111 is set in the 4th trepanning 110 and aisle 109, the 5th trepanning 112 of setting on the first insulating layer 111, the 5th Trepanning 112 and third trepanning 108, the first trepanning 105 and the 4th trepanning 110 formed up and down fill area (third trepanning 108, The first insulating layer 111 filled in first trepanning 105 and the 4th trepanning 110 can be denoted as aperture area, radially be set in this aperture area Set the 5th trepanning 112, the side wall of the 5th trepanning 112 still remains with the first insulating layer 111, and its bottom directly with n-GaN layers 101 connect);

Prepare 113 step of N electrode metal:N electrode metal 113 is set in fill area, and N electrode metal 113 is pierced by upwards First insulating layer 111;

Prepare bonded layer, bonded substrate 200 and the back of the body 202 step of layer gold:The first bonded layer is formed on the first insulating layer 111 114;Bonded substrate 200 is taken, the second bonded layer 201 is formed in the front of bonded substrate 200, in the back side shape of bonded substrate 200 At back of the body layer gold 202;Then, the first bonded layer 114 and the second bonded layer 201 are mutually bonded that fixed (i.e. bonded substrate 200 is by the One bonded layer 114 and the second metal bonding layer are bonded on the first insulating layer 111);

Remove epitaxial substrate step:Epitaxial substrate is removed;

Prepare 115 step of second insulating layer:Second insulating layer 115 is prepared on n-GaN layers 101, then in the second insulation 6th trepanning 116 is set on layer 115, and the 6th trepanning 116 extends radially through second insulating layer 115, n-GaN layers 101, InGaN/GaN Multiple quantum well layer 102 and p-GaN layer 103;The upright projection area weight in the upright projection area of the 6th trepanning 116 and the second trepanning 106 It is folded;

Prepare 117 step of P electrode metal:The filling P electrode metal 117 in the 6th trepanning 116, P electrode metal 117 is upward It is pierced by second insulating layer 115.

As further embodiment, in epitaxial growth steps, using (111) face of epitaxial substrate as epitaxial surface, outside It is silicon substrate, GaN substrate, Sapphire Substrate, tantalum strontium aluminate lanthanum substrate or lithium gallium oxide substrate to prolong substrate;N-GaN layers of epitaxial growth 101, the technique of InGaN/GaN multiple quantum well layers 102 and p-GaN layer 103 is MOCVD techniques.

As further embodiment, in step is deposited, it is deposited using magnetron sputtering or electron beam evaporation process anti- Penetrate mirror layer 104;First trepanning 105 and the second trepanning 106 are obtained using photoetching and wet etching method, are subsequent reflection mirror layer 104 Can perfection be coated among reflector protective layer 107, reduce the electrical leakage problems caused by the diffusion of Ag, and rotten carrying out wet method When erosion, the corrosive liquid used greatly reduces process costs, reduces work for ammonium hydroxide-dioxygen water mixed liquid or hydrochloric acid solution Skill duration;The condition of high annealing is as follows:It is carried out in quick anneal oven, annealing atmosphere is N2And O2Gaseous mixture, N2With O2's Volume ratio is 50:(1-50), temperature are 300-700 DEG C, time 10-600s.

As further embodiment, in preparing 107 step of reflector protective layer, using magnetron sputtering technique or Electron beam evaporation process obtains 104 protective layer of mirror layer, and reflector protective layer 107 covers the first trepanning 105, the second trepanning 106 bottom and side wall;Third trepanning 108 and aisle 109 are obtained using photoetching and lift-off techniques.

As further embodiment, in preparing 110 step of the 4th trepanning, using standard photolithography process and inductance coupling It closes plasma etch process (dry etch process) and obtains the 4th trepanning 110, carry out inductively coupled plasma etching technique When, the power of top electrode is 200-900W, and the power of lower electrode is 80-500W, and etch rate is 15-100 angstroms per seconds.

As further embodiment first is obtained using pecvd process in preparing 111 step of the first insulating layer Insulating layer 111, the first insulating layer 111 cover bottom and the side wall in the 5th trepanning 112 and aisle 109, being capable of perfect cladding the 5th The side wall of the GaN and MQWS (InGaN/GaN multiple quantum wells) of the etching exposure of 112 internal cause of trepanning;First insulating layer 111 covering simultaneously The surface of reflector protective layer 107 in addition to the 5th trepanning 112 and aisle 109 can protect N electrode metal 113 and speculum 107 metal perfection of sheath is kept apart, and P, N electrode short circuit are prevented;The 5th is arranged on the first insulating layer 111 using etching process Trepanning 112, corrosive liquid are BOE liquid;Alternatively, forming the 5th trepanning 112, the first insulation using standard photolithography process and etching technics Layer 111 still coats the side wall of the 5th trepanning 112, and the side wall of the 5th trepanning 112 directly connects with the bottom surface of n-GaN layers 101, Without the isolation of the first insulating layer 111.

As further embodiment, in preparing 113 step of N electrode metal, using sputtering or electron beam evaporation Technique fills N electrode metal 113 in fill area.

As further embodiment, in removing epitaxial substrate step, using the side of mechanical lapping and chemical attack Method removes epitaxial substrate;When carrying out chemical attack, the corrosive liquid used is hydrofluoric acid, nitric acid, one kind of glacial acetic acid or arbitrary group It closes.After epitaxial substrate is removed, remaining epitaxial substrate is removed using dry etching to the chip surface after stripping, makes n-GaN The back side of layer 101 is fully exposed;Then to the mixing hot solution using KOH and NaOH, or using the molten of KOH and NaOH Melt object and roughening treatment is carried out to n-GaN layers 101, to reduce the total reflection effect of GaN- Air Interfaces.

As further embodiment, in preparing 115 step of second insulating layer, using pecvd process after roughening The backside deposition second insulating layer 115 of n-GaN layers 101;Use standard photolithography process and etching technics in n-GaN layers 101 again Back side upright projection region corresponding with the second trepanning 106 forms the 6th trepanning 116, and the 6th trepanning 116 is located at current structure Edge, belongs to opening half bore, side wall at only two, is in addition exposed among air at two.

As further embodiment, in preparing 117 step of P electrode metal, using sputtering or electron beam evaporation Technique filling P electrode metal 117 in the 6th trepanning 116, and using the removal of lift-off techniques in addition to the 6th trepanning 116 The P electrode metal 117 on 115 surface of second insulating layer.

Effect assessment and performance detection

Figure 12 is the optical output power Mapping figure of conventional linear light emitting diode (LED) chip with vertical structure, and Figure 13 is with lower of size The optical output power Mapping figures for the 3D through-hole superstructure LED chips that inventive embodiments are provided, as seen from the figure, the present invention is real It applies the LOP values of the 3D through-hole superstructure LED chips that example is provided and range to 540-560mW is promoted by 420-440mW, improve About 25%, the basic reason that optical output power improves is current expansion, current expansion it is more uniform, shine evenly, light Output power is also higher.

The above embodiment is only the preferred embodiment of the present invention, and the scope of protection of the present invention is not limited thereto, The variation and replacement for any unsubstantiality that those skilled in the art is done on the basis of the present invention belong to institute of the present invention Claimed range.

Claims (10)

1. a kind of 3D through-holes superstructure LED chip, which is characterized in that including stack gradually second insulating layer, n-GaN layers, InGaN/GaN multiple quantum well layers, p-GaN layer, mirror layer, reflector protective layer, the first insulating layer, the first bonded layer, second Bonded layer, bonded substrate and back of the body layer gold;
The first trepanning and the second trepanning are provided on the mirror layer, second trepanning is located at the side of the mirror layer Edge;
The reflector protective layer is arranged on the mirror layer and covers the bottom and side wall of first trepanning, and covers Cover the bottom and side wall of second trepanning;Third trepanning and aisle are provided in the reflector protective layer, the third is opened Up and down with first trepanning, the aisle circumferential direction ring is located in the reflector protective layer and is opened across described second in hole Hole;
The 4th trepanning is extended downward with along the third trepanning and the first trepanning, the 4th trepanning runs through the p-GaN Layer and the InGaN/GaN multiple quantum well layers, the bottom of the 4th trepanning is set in n-GaN layers described;
First insulating layer is arranged in the reflector protective layer, and fills the third trepanning, the first trepanning, the 4th opens Hole and aisle;It is provided with the 5th trepanning on first insulating layer;5th trepanning and the third trepanning, the first trepanning Fill area is formed up and down with the 4th trepanning, and the side wall of the fill area is coated with first insulating layer;In the filling N electrode metal is set in area;The bottom of the N electrode metal is in direct contact with described n-GaN layers;The N electrode metal is upward It is inserted into first bonded layer;
The 6th trepanning is provided in the second insulating layer, the 6th trepanning extends radially through the second insulating layer, n-GaN Layer, InGaN/GaN multiple quantum well layers and p-GaN layer;The upright projection area of 6th trepanning is vertical with second trepanning Project area overlapping;P electrode metal is filled in the 6th trepanning;The P electrode metal is pierced by the second insulating layer upwards.
2. 3D through-holes superstructure LED chip as described in claim 1, which is characterized in that first trepanning and described second Trepanning runs through the mirror layer up and down;The aperture of the third trepanning is less than the aperture of first trepanning.
3. 3D through-holes superstructure LED chip as described in claim 1, which is characterized in that the mirror layer is nanometer Ag base Mirror layer, nanometer Ag base reflecting layer include successively and the X layers, nanometer Ag layer and Y layers that set;Described X layers is Ohmic contact Layer, forming material Ni, Pt, Pd, Au, Pt, ITO, ZnO, AZO, GZO or graphene;Described Y layers is antioxidation coating, forms material Material is Ni, Ti, Mg, Al, W, TiW, Au or Pt;The thickness of the mirror layer is 25-500nm;
The material of the reflector protective layer is one kind or arbitrary combination in TiW, Au, Cr, Mo, Al, Cu;The speculum is protected The thickness of sheath is 100-5000nm.
4. 3D through-holes superstructure LED chip as described in claim 1, which is characterized in that the material of first insulating layer is The thickness of titanium dioxide, silica or silicon nitride, first insulating layer is 200-2000nm;
First bonded layer and second bonded layer are Sn-Ni alloy-layers;The thickness of first bonded layer is 500- The thickness of 9000nm, second bonded layer are 300-50000nm;
The bonded substrate is silicon substrate, Cu substrates, W substrates or flexible substrate.
5. 3D through-holes superstructure LED chip as described in claim 1, which is characterized in that the N electrode metal be Al, Ti, W, The thickness of one or any combination in Au, Cr, Mo, Pt, Ag and ZnO, the N electrode metal is 200-10000nm;
The P electrode metal is the one or any combination in Cr, Ni, Ti, TiW and Pt, and the thickness of the P electrode metal is 200-8000nm。
6. a kind of preparation method of 3D through-hole superstructure LED chips as described in claim 1-5 any one, feature exist In, including:
Epitaxial growth steps:Epitaxial substrate is taken, grows n-GaN layers, InGaN/GaN multiple quantum wells successively in the epitaxial substrate Layer and p-GaN layer;
Opening step is deposited:It is deposited mirror layer in the p-GaN layer, after high annealing, is opened up on the mirror layer First trepanning and the second trepanning, second trepanning are located at the edge of the mirror layer;
Prepare reflector protective layer step:Reflector protective layer, and the reflector protective layer are prepared on the mirror layer Cover the bottom and side wall of first trepanning, and the bottom and side wall of covering second trepanning;Then, in the reflection Third trepanning and aisle are set on mirror protective layer, and up and down with first trepanning, the aisle is circumferential for the third trepanning Ring is located in the reflector protective layer and passes through second trepanning;
Prepare the 4th opening step:The 4th trepanning of setting is extended downwardly along the third trepanning and the first trepanning, the described 4th opens The p-GaN layer and the InGaN/GaN multiple quantum well layers are run through in hole, and the bottom of the 4th trepanning is set to the n-GaN In layer;
Prepare the first insulating layer step:In the reflector protective layer and the third trepanning, the first trepanning, the 4th trepanning With the first insulating layer is set in aisle, the 5th trepanning, the 5th trepanning and the third are set on first insulating layer Trepanning, the first trepanning and the 4th trepanning form fill area up and down;
Prepare N electrode metal step:N electrode metal is set in the fill area, and the N electrode metal is pierced by described the upwards One insulating layer;
Prepare bonded layer, bonded substrate and back of the body layer gold step:The first bonded layer is formed on first insulating layer;Bonding is taken to serve as a contrast Bottom, the second bonded layer is formed in the front of the bonded substrate, and back of the body layer gold is formed at the back side of the bonded substrate;Then, institute It states the first bonded layer and second bonded layer is mutually bonded fixation;
Remove epitaxial substrate step:The epitaxial substrate is removed;
Prepare second insulating layer step:Second insulating layer is prepared on n-GaN layers described, is then set in the second insulating layer Set the 6th trepanning, the 6th trepanning extends radially through the second insulating layer, n-GaN layers, InGaN/GaN multiple quantum well layers and p- GaN layer;The upright projection area overlapping in the upright projection area and second trepanning of the 6th trepanning;
Prepare P electrode metal step:P electrode metal is filled in the 6th trepanning, the P electrode metal is pierced by described upwards Second insulating layer.
7. the preparation method of 3D through-holes superstructure LED chip as claimed in claim 6, which is characterized in that
In the epitaxial growth steps, using (111) face of the epitaxial substrate as epitaxial surface, the epitaxial substrate serves as a contrast for silicon Bottom, GaN substrate, Sapphire Substrate, tantalum strontium aluminate lanthanum substrate or lithium gallium oxide substrate;
In the vapor deposition step, the mirror layer is deposited using magnetron sputtering or electron beam evaporation process;Using photoetching and Wet etching method obtains first trepanning and second trepanning, and when carrying out wet etching, the corrosive liquid used is bis- for ammonium hydroxide- Oxygen water mixed liquid or hydrochloric acid solution;The condition of high annealing is as follows:Annealing atmosphere is N2And O2Gaseous mixture, N2With O2Body Product is than being 50:(1-50), temperature are 300-700 DEG C, time 10-600s;
In the preparation reflector protective layer step, obtained using magnetron sputtering technique or electron beam evaporation process described anti- Mirror layer protective layer is penetrated, the third trepanning and the aisle are obtained using photoetching and lift-off techniques.
8. the preparation method of 3D through-holes superstructure LED chip as claimed in claim 6, which is characterized in that
In the 4th opening step of the preparation, described is obtained using photoetching process and inductively coupled plasma etching technique Four trepannings, when carrying out inductively coupled plasma etching technique, the power of top electrode is 200-900W, and the power of lower electrode is 80-500W, etch rate are 15-100 angstroms per seconds;
In the first insulating layer step of the preparation, first insulating layer is obtained using pecvd process, is existed using etching process 5th trepanning is set on first insulating layer, and corrosive liquid is BOE liquid;
In the preparation N electrode metal step, N electricity is filled in the fill area using sputtering or electron beam evaporation process Pole metal.
9. the preparation method of 3D through-holes superstructure LED chip as claimed in claim 6, which is characterized in that
In the stripping epitaxial substrate step, the epitaxial substrate is removed using the method for mechanical lapping and chemical attack;Into When row chemical attack, the corrosive liquid used is hydrofluoric acid, nitric acid, one kind of glacial acetic acid or arbitrary combination;
In the preparation P electrode metal step, P is filled in the 6th trepanning using sputtering or electron beam evaporation process Electrode metal.
10. the preparation method of 3D through-holes superstructure LED chip as claimed in claim 6, which is characterized in that further include at roughening Manage step:After the epitaxial substrate is removed, dry etching processing is carried out, n-GaN layers of the back side is made to be fully exposed; Then to the mixing hot solution using KOH and NaOH, or it is thick to described n-GaN layers progress using the fusant of KOH and NaOH Change is handled.
CN201810027470.5A 2018-01-11 2018-01-11 A kind of 3D through-hole superstructure LED chip and preparation method thereof CN108365078B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103700734A (en) * 2012-09-28 2014-04-02 上海蓝光科技有限公司 Manufacturing method of light-emitting diode
CN104638086A (en) * 2015-03-09 2015-05-20 武汉大学 LED (light-emitting diode) chip of three-dimensional electrode structure with high current density
CN104952993A (en) * 2014-03-24 2015-09-30 山东华光光电子有限公司 Reversed polarity AlGaInP light emitting diode whose current spreading layer has two-dimensional optical structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103700734A (en) * 2012-09-28 2014-04-02 上海蓝光科技有限公司 Manufacturing method of light-emitting diode
CN104952993A (en) * 2014-03-24 2015-09-30 山东华光光电子有限公司 Reversed polarity AlGaInP light emitting diode whose current spreading layer has two-dimensional optical structure
CN104638086A (en) * 2015-03-09 2015-05-20 武汉大学 LED (light-emitting diode) chip of three-dimensional electrode structure with high current density

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