CN112968095A - Light emitting diode chip and preparation method thereof - Google Patents
Light emitting diode chip and preparation method thereof Download PDFInfo
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- CN112968095A CN112968095A CN202011304966.6A CN202011304966A CN112968095A CN 112968095 A CN112968095 A CN 112968095A CN 202011304966 A CN202011304966 A CN 202011304966A CN 112968095 A CN112968095 A CN 112968095A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention relates to a light-emitting diode chip and a preparation method thereof. The chip comprises a first semiconductor layer, a light emitting layer, a second semiconductor layer, a first insulating layer and a bonding layer which are sequentially stacked; and, a first electrode and a second electrode; the first electrode penetrates through the first insulating layer, the second semiconductor layer and the light-emitting layer and is electrically connected with the first semiconductor layer and the bonding layer; the second electrode penetrates through the bonding layer and the first insulating layer and is electrically connected with the second semiconductor layer. The LED lamp has the effects of reducing welding wires and improving the luminous efficiency on the basis of meeting the requirements of high-power LED products.
Description
Technical Field
The invention relates to the field of LED chips, in particular to a light-emitting diode chip and a preparation method thereof.
Background
With the gradual application of the LED in the illumination field, the market has higher and higher requirements on the luminous efficiency of the white LED.
At present, the LED chip structure mainly comprises three structures, namely a forward mounting structure, an inverted mounting structure and a vertical structure.
The forward mounting structure is easy to have current crowding phenomenon because the p electrode and the n electrode are arranged on the same side of the LED, and is high in thermal resistance and not suitable for being applied in a high-power scene.
The flip-chip structure is further developed on the front-mounted structure because it does not need to dissipate heat through the substrate, can be used with large current, and can be made smaller in size, so it can operate with higher power than the front-mounted structure. However, because the structure is basically a transverse structure, the defects of current crowding and poor thermal resistance still exist, and the trend that the current market has an increasing demand on the power of the light source cannot be completely met.
The vertical structure can achieve high current density and uniformity, and can meet the market demand on ultra-high power LED products. However, in practical applications, the LED chip with vertical structure has a big disadvantage that the LED chip with vertical structure needs bonding wires.
Therefore, the reduction of bonding wires on the basis of meeting the requirement of high-power LED products is a problem to be solved at present.
Disclosure of Invention
In view of the foregoing deficiencies of the prior art, the present application provides a light emitting diode chip and a method for manufacturing the same, which aims to solve the problem of reducing bonding wires on the basis of meeting the requirement of a high power LED product.
A light emitting diode chip comprising:
the LED comprises a first semiconductor layer, a light emitting layer, a second semiconductor layer, a first insulating layer and a bonding layer which are sequentially stacked; and the number of the first and second groups,
a first electrode and a second electrode;
the first electrode penetrates through the first insulating layer, the second semiconductor layer and the light emitting layer and is electrically connected with the first semiconductor layer and the bonding layer;
the second electrode penetrates through the bonding layer and the first insulating layer and is electrically connected with the second semiconductor layer.
The first electrode and the second electrode are both positioned on one side of the light-emitting layer, so that welding lines or welding spots do not need to be arranged on the surface of the light-emitting layer for emitting light, and the light-emitting area of the light-emitting layer is increased.
Optionally, the second semiconductor layer comprises:
the light-emitting diode comprises an inner film layer, reflectors and reflector protection layers which are sequentially stacked, wherein the reflectors are arranged on a first surface of the inner film layer at preset intervals, the first surface of the inner film layer is far away from a light-emitting layer, and the reflector protection layers and the reflectors are arranged in a one-to-one correspondence mode and wrap the reflectors;
a first preset number of first mesa holes penetrating into the first semiconductor layer are formed between the reflector protection layers, and the first insulating layer wraps the reflector protection layers and fills the first mesa holes;
a first through hole is formed in the first insulating layer filling the first mesa hole, the first electrode is filled in the first through hole, a first portion of the first electrode penetrates out of the first surface of the first insulating layer along the first through hole, and the first surface of the first insulating layer is far away from the reflector protective layer.
The first electrode is positioned in the first through hole of the first insulating layer, so that the first insulating layer can isolate the first electrode from other structures, and interference among different electrodes is reduced.
Optionally, the bonding layer includes:
the first bonding layer and the second bonding layer are sequentially stacked, wherein the first bonding layer covers a first surface of the first insulating layer and a first portion of the first electrode, and the first surface of the first insulating layer is far away from the light emitting layer.
Optionally, the method further includes:
the second insulating layer is arranged on one side, far away from the light emitting layer, of the first semiconductor layer.
The second insulating layer protects the epitaxial wafer, so that the service life of the epitaxial wafer is prolonged.
Optionally, the method further includes:
a second substrate, wherein the second substrate is arranged on the first surface of the bonding layer, and the first surface of the bonding layer is far away from the first insulating layer; second mesa holes with a second preset number are formed in the second substrate, penetrate through the second substrate and reach the inside of the first insulating layer, the hole bottoms of the second mesa holes are overlapped with the first surface of the second semiconductor layer, and the first surface of the second semiconductor layer is close to the first insulating layer;
a third insulating layer filling the second mesa hole;
a second through hole is formed in a third insulating layer filling the second mesa hole, the second electrode is filled in the second through hole, a first portion of the second electrode penetrates through the first surface of the second substrate along the second through hole, and the first surface of the second substrate is far away from the first insulating layer.
Based on the same inventive concept, the application also provides a light emitting diode chip preparation method, which comprises the following steps:
preparing an epitaxial layer on a first substrate, wherein the epitaxial layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked;
depositing a first insulating layer on the epitaxial layer;
preparing a first electrode which penetrates through the first insulating layer, the first semiconductor layer and the light emitting layer and is electrically connected with the first semiconductor layer;
depositing a bonding layer on the first insulating layer, the bonding layer being electrically connected to the first electrode;
preparing a second electrode penetrating the bonding layer and the first insulating layer and electrically connected to the second semiconductor layer.
The first electrode and the second electrode are both positioned on one side of the epitaxial layer, so that welding wires or welding spots do not need to be arranged on the surface of the epitaxial layer for emitting light, and the light emitting area of the epitaxial layer is increased.
Optionally, the preparing an epitaxial layer on the first substrate includes:
sequentially laminating the first semiconductor layer, the light emitting layer and the second semiconductor layer on the first surface of the first substrate;
wherein laminating the second semiconductor layer on the first surface of the light emitting layer includes:
sequentially laminating an inner film layer, a reflector and a reflector protection layer on the first surface of the light-emitting layer, wherein the first surface of the light-emitting layer is far away from the first substrate; the reflecting mirrors are arranged on the first surface of the inner film layer at preset intervals, the first surface of the inner film layer is far away from the light emitting layer, and the reflecting mirror protective layers are arranged in one-to-one correspondence with the reflecting mirrors and wrap the reflecting mirrors.
The reflector protective layer protects the reflector, so that the corrosion to the reflector can be reduced, and the service life of the reflector is prolonged.
Optionally, the depositing a first insulating layer on the epitaxial layer includes:
and arranging a first preset number of first mesa holes penetrating into the first semiconductor layer between the reflector protective layers, and filling first insulating layers in the first mesa holes, wherein the reflector protective layers are wrapped by the first insulating layers.
Optionally, the preparing the first electrode includes:
forming a first through hole penetrating into the first semiconductor layer on the first insulating layer, and filling a first metal in the first through hole to form the first electrode, wherein a first part of the first electrode penetrates out of the first surface of the first insulating layer along the first through hole, and the first surface of the first insulating layer is far away from the mirror protection layer; the first through hole is located in the first table-board hole, and the bottom of the first through hole is overlapped with part of the bottom of the first table-board hole.
Optionally, the preparing the second electrode includes:
forming a second mesa hole penetrating to the first insulating layer on the second surface of the bonding layer;
filling a third insulating layer in the second mesa hole, wherein the third insulating layer covers the first surface of the bonding layer, and the first surface of the bonding layer is far away from the first insulating layer;
and opening a second through hole penetrating through the third insulating layer to the second semiconductor, and filling a second metal in the second through hole to form a second electrode, wherein the second through hole is located in the second mesa hole, and a pore channel of the second through hole is overlapped with a partial pore channel of the second mesa hole.
Drawings
FIG. 1 is a first structural diagram of an LED chip according to the present invention;
FIG. 2 is a second structural diagram of an LED chip according to the present invention;
FIG. 3 is a block diagram of a process for manufacturing a light emitting diode chip according to the present invention;
FIG. 4 is a block diagram showing the structure of an epitaxial wafer according to the present invention;
FIG. 5 is a block diagram showing the structure of an epitaxial wafer provided with a mirror according to the present invention;
FIG. 6 is a block diagram showing a structure provided with a mirror protective layer according to the present invention;
FIG. 7 is a block diagram illustrating a first mesa opening formation in accordance with the present invention;
FIG. 8 is a block diagram showing a structure of preparing a first insulating layer according to the present invention;
FIG. 9 is a block diagram illustrating a first through-hole according to the present invention;
FIG. 10 is a block diagram showing a structure of filling a first metal in the present invention;
FIG. 11 is a block diagram showing the structure of a chip after bonding in the present invention;
FIG. 12 is a block diagram showing the structure of a chip after the first substrate has been peeled off in the present invention;
FIG. 13 is a block diagram showing a structure of preparing a second mesa hole in the present invention;
FIG. 14 is a block diagram showing a structure of preparing a third insulating layer in the present invention;
FIG. 15 is a block diagram showing a structure of filling a second metal in the present invention;
FIG. 16 is a block flow diagram of an embodiment of the present invention.
Description of reference numerals:
20-a first substrate; 22-a first semiconductor layer; 24-a light emitting layer; 26-a second semiconductor layer; 262-intima layer; 264-mirror; 266-a mirror protective layer; 2662-a first mesa aperture; 28-a first insulating layer; 282-a first through hole; 30-a first electrode; 32-a second electrode; 34-a bonding layer; 342-a first bonding layer; 344-a second bonding layer; 36-a second insulating layer; 38-a second substrate; 382-a second mesa aperture; 40-a third insulating layer; 402-second through hole.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
The forward mounting structure in the current LED chip structure is not suitable for being applied in a high-power scene, and the inverted mounting structure has the defects of current crowding and poor thermal resistance, and still cannot completely meet the trend that the current market has increasingly larger requirements on the power of a light source. The vertical structure can achieve high current density and uniformity, and can meet the market demand on ultra-high power LED products. But requires wire bonding. Therefore, the reduction of bonding wires on the basis of meeting the requirement of high-power LED products is a problem to be solved at present. Based on this, the present application intends to provide a solution to the above technical problem, the details of which will be explained in the following embodiments.
According to an embodiment of the present invention, there is provided a light emitting diode chip, as shown in fig. 1, including:
a first semiconductor layer 22, a light emitting layer 24, a second semiconductor layer 26, a first insulating layer 28, and a bonding layer 34, which are sequentially stacked; and, a first electrode 30 and a second electrode 32; wherein the first electrode 30 sequentially penetrates through the first insulating layer 28, the second semiconductor layer 26 and the light emitting layer 24, and is electrically connected to the first semiconductor layer 22 and the bonding layer 34; the second electrode 32 sequentially penetrates the bonding layer 34 and the first insulating layer 28, and is electrically connected to the second semiconductor layer 26.
In the present embodiment, since the first electrode 30 and the second electrode 32 are both located on the same side of the light-emitting layer 24, there is no need to provide a solder joint or a solder joint on the surface of the light-emitting layer 24 for emitting light, and the light-emitting area of the light-emitting layer 24 is increased.
The first semiconductor layer 22 may be an n-GaN layer (n-type doped GaN (gallium nitride) thin film), the light-emitting layer 24 may be a light-emitting multi-quantum well layer (InGaNorAlGaN/GaN multi-quantum well), the first insulating layer 28 may be made of TiO2 (titanium oxide), SiO2 (silicon oxide) or SiNx (silicon nitride), and the thickness of the first insulating layer 28 is 100-2000 nm; the material of the first electrode 30 may be one or more combinations of Cr (chromium), Al, Ti, Pt (platinum), Au, Ti, Mo (molybdenum), and the thickness of the metal as the first electrode 30 is 200nm to 10000 nm; the material of the second electrode 32 can be one or a combination of several of Cr, Ni, Ti, TiW, Pt and Au, and the thickness of the metal used as the second electrode 32 is 200nm-8000 nm.
In an alternative embodiment, as shown in fig. 2, bonding layer 34 includes:
a first bonding layer 342 and a second bonding layer 344 are sequentially stacked, wherein the first bonding layer 342 covers a first surface of the first insulating layer 28 and a first portion of the first electrode 30, and the first surface of the first insulating layer 28 is away from the light emitting layer 24.
In the present embodiment, the material of the first bonding layer 342 may be Sn — Ni (tin-nickel), and the thickness of the first bonding layer 342 is 200nm to 9000 nm; the material of the second bonding layer 344 may be Sn-Ni, and the thickness of the second bonding layer 344 is 300nm-5000 nm.
In an alternative embodiment, as shown in fig. 2, the second semiconductor layer 26 includes:
the light-emitting layer 24 is arranged on the first surface of the inner film layer 262, and the reflector protective layer 266 is arranged on the second surface of the inner film layer 262;
a first predetermined number of first mesa holes 2662 penetrating into the first semiconductor layer 22 are formed between the mirror protection layers 266, and the first insulating layer 28 wraps the mirror protection layers 266 and fills the first mesa holes 2662;
the first insulating layer 28 filling the first mesa hole 2662 has a first through hole 282 formed therein, the first electrode 30 is filled in the first through hole 282, a first portion of the first electrode 30 penetrates through the first surface of the first insulating layer 28 along the first through hole 282, and the first surface of the first insulating layer 28 is far away from the mirror protection layer 266.
In the present embodiment, since the first electrode 30 is located in the first through hole 282 of the first insulating layer 28, the first insulating layer 28 can isolate the first electrode 30 from other structures, thereby reducing interference between different electrodes.
The inner film layer 262 may be a p-GaN layer (p-type doped GaN thin film), the reflector 264 may be prepared by magnetron sputtering or electron beam evaporation, and the reflector 264 includes a stacked a layer, a nano Ag layer, and a B layer; the layer A is an ohmic contact layer and is made of Ni, Pt, Pd, Au, Pt or ZnO; the layer B is an anti-oxidation layer and is made of Ni, Ti, Mg, Al, W, TiW, Au or Pt; the thickness of mirror 264 is 25-500 nm.
The mirror protection layer 266 may be prepared by using a magnetron sputtering or electron beam evaporation process on the surface of the mirror 264; the material of the mirror protection layer 266 is one or a combination of several of TiW, Au, Cr, Mo, Ti, and Pt, and the thickness of the mirror protection layer 266 is 100nm to 5000nm.
In an alternative embodiment, as shown in fig. 2, the chip further comprises:
and a second insulating layer 36, wherein the second insulating layer 36 is arranged on the side of the first semiconductor layer 22 far away from the light-emitting layer 24.
The second insulating layer 36 protects the first semiconductor layer 22, thereby extending the lifetime of the first semiconductor layer 22.
The second insulating layer 36 is formed by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, the material of the second insulating layer 36 may be silicon dioxide, and the thickness of the second insulating layer 36 is 200nm to 2000 nm.
In an alternative embodiment, as shown in fig. 2, the chip further comprises:
a second substrate 38, wherein a second surface of the second substrate 38 is in contact with a first surface of the bonding layer 34, the first surface of the bonding layer 34 being away from the first insulating layer 28, and the second surface of the second substrate 38 being close to the first insulating layer 28; a second predetermined number of second mesa holes 382 are formed in the second substrate 38, the second mesa holes 382 penetrate the second substrate 38 into the first insulating layer 28, and the hole bottoms of the second mesa holes 382 coincide with the first surface of the mirror protection layer 266 in the second semiconductor layer 26, and the first surface of the second semiconductor layer 26 is close to the first insulating layer 28.
A third insulating layer 40, the third insulating layer 40 filling the second mesa holes 382;
a second through hole 402 is opened in the third insulating layer 40 filling the second mesa hole 382, the second electrode 30 is filled in the second through hole 402, a first portion of the second electrode 30 penetrates the first surface of the second substrate 38 along the second through hole 402, and the first surface of the second substrate 38 is far away from the first insulating layer 28.
In the present embodiment, the material of the third insulating layer 40 may be TiO2, SiO2, or SiN, wherein the thickness of the third insulating layer 40 may be 100-2000 nm.
As shown in fig. 2 and fig. 3, the present invention further provides a method for manufacturing a light emitting diode chip, including:
step S102, preparing an epitaxial layer on the first substrate 20, the epitaxial layer including a first semiconductor layer 22, a light emitting layer 24, and a second semiconductor layer 26 stacked in sequence;
in this embodiment, the first substrate 20 may be, but is not limited to, a Si (silicon) substrate, a GaN substrate, a Cu (copper) substrate, an LSAT (strontium lanthanum tantalate) substrate, a LiGaO2 (lithium gallate) substrate, or the like.
Step S104, depositing a first insulating layer 28 on the epitaxial layer;
step S106, preparing a first electrode 30, wherein the first electrode 30 penetrates through the first insulating layer 28, the first semiconductor layer 22 and the light-emitting layer 24, and is electrically connected to the first semiconductor layer 22;
step S108, depositing a bonding layer 34 on the first insulating layer 28, the bonding layer 34 being electrically connected to the first electrode 30;
in step S1010, a second electrode 32 is prepared, wherein the second electrode 32 penetrates through the bonding layer 34 and the first insulating layer 28, and is electrically connected to the second semiconductor layer 26.
In an alternative embodiment, the preparation of the epitaxial layer on the first substrate 20 comprises:
step S1022 of sequentially laminating the first semiconductor layer 22, the light-emitting layer 24, and the second semiconductor layer 26 on the first surface of the first substrate 20;
wherein the laminating of the second semiconductor layer 26 on the first surface of the light emitting layer 24 includes:
step S1024, sequentially stacking the inner film layer 262, the reflective mirror 264 and the reflective mirror protection layer 266 on the first surface of the light emitting layer 24, wherein the reflective mirror 264 is arranged on the first surface of the inner film layer 262 at a predetermined interval, and the reflective mirror protection layer 266 and the reflective mirror 264 are arranged in a one-to-one correspondence and wrap the reflective mirror 264.
In this embodiment, a magnetron sputtering or electron beam evaporation process is used to prepare the reflector 264 on the surface of the inner film layer 262, and then the prepared reflector 264 is annealed at a high temperature in a rapid annealing furnace, wherein the annealing atmosphere is N2/O2 mixed gas, and the ratio of the mixed gas is N2: o2 ═ 50: 1-1: 50 at 200-700 ℃ for 60-600 seconds, and then treating the reflector 264 by wet etching in combination with a standard photolithography process to obtain a reflector hole and a first channel, wherein the wet etching solution is a hydrochloric acid solution or an ammonia-hydrogen peroxide mixed solution (as shown in fig. 4 and 5).
As shown in fig. 6, a mirror protection layer 266 is then prepared on the surface of the mirror 264 by magnetron sputtering or electron beam evaporation, and a mirror protection layer hole and a second via are obtained by photolithography and lift-off process, wherein the mirror protection layer hole covers the mirror hole, the bottom of the first via and the sidewall of the first via.
In an alternative embodiment, depositing the first insulating layer 28 on the epitaxial layer includes:
in step S1042, a first predetermined number of first mesa holes 2662 penetrating into the first semiconductor layer 22 are opened between the mirror protection layers 266, and the first mesa holes 2662 are filled with the first insulating layer 28, wherein the mirror protection layers 266 are wrapped by the first insulating layer 28.
In this embodiment, as shown in fig. 7, a first MESA hole (MESA hole) 2662 is formed in the mirror protection layer hole by an inductively coupled plasma etching method, and the first MESA hole 2232 radially penetrates through the inner film layer 262 and the light-emitting layer 24, so as to expose the first semiconductor layer 2222 located at the bottom of the mirror protection layer hole; wherein the power of the upper etching electrode is 200W-900W, the power of the lower etching electrode is 80W-500W, and the etching rate is 15A/s-100A/s.
Subsequently, as shown in fig. 8, a first insulating layer 28 is formed in the first mesa hole 2232 and over the first via.
In an alternative embodiment, preparing the first electrode 30 includes:
step S1062, forming a first through hole 282 penetrating into the first semiconductor layer 22 in the first insulating layer 28, and filling a first metal in the first through hole 282 to form a first electrode 30, wherein a first portion of the first electrode 30 penetrates through the first surface of the first insulating layer 28 along the first through hole 282; the first through hole 282 is located in the first mesa hole 2662, and a bottom of the first through hole 282 overlaps with a portion of a bottom of the first mesa hole 2662.
In the present embodiment, as shown in fig. 9 and 10, a wet etching process is used to obtain a first through hole 282 in the first insulating layer 28, and the etching solution is a BOE solution; a first metal is then filled in the first insulating layer 28 to form a first electrode 30, wherein the first metal directly contacts the first semiconductor layer 22 at the bottom of the opening of the reflector.
In one embodiment, depositing bonding layer 34 on first insulating layer 28 includes:
step S1082, flipping the first bonding layer 342, and moving the flipped first bonding layer 342 to a position above the second substrate 38;
in this embodiment, as shown in fig. 11, a first bonding layer 342 is prepared on the surface of the first insulating layer 28 by a magnetron sputtering or electron beam evaporation process, and then the first bonding layer 342 is flipped by a bonding machine.
In step S1084, the first bonding layer 342 moved above the second substrate 38 is bonded and fixed to the second bonding layer 344.
In the present embodiment, the first bonding layer 342 is moved and bonded by a bonding machine.
In an alternative embodiment, before bonding and fixing the first bonding layer 342 and the second bonding layer 344, the method further comprises:
step S1086, growing a second bonding layer 344 on the second substrate 38;
in the present embodiment, a second bonding layer 344 is prepared on the surface of the second substrate 38 close to the epitaxial layer by a magnetron sputtering or electron beam evaporation process;
in an alternative embodiment, after bonding and fixing the first bonding layer 342 and the second bonding layer 344, the method further comprises:
step S1088, the first substrate 20 is stripped, and the second insulating layer 36 is prepared on the second surface of the first semiconductor layer 22.
In the present embodiment, the method for peeling the first substrate 20 is mechanical polishing plus chemical etching. And removing the chip buffer layer on the surface of the stripped chip by using dry etching, completely exposing the back surface of the first semiconductor layer 22, and treating the first semiconductor layer 22 by using a chemical solution so as to reduce the total reflection effect of the GaN-air interface. Wherein the chemical solution for etching the residual first substrate 20 may be a combination of nitric acid and glacial acetic acid, and the first semiconductor layer 22 may be etched with a hot solution of KOH to reduce the total reflection effect of the GaN-air interface (as shown in fig. 12 in particular).
In an alternative embodiment, preparing the second electrode 32 includes:
step S10102, forming a second mesa hole 382 penetrating to the first insulating layer 28 on the second surface of the bonding layer 34;
in this embodiment, the back surface of the second substrate 38 is mechanically ground, and then a standard photolithography process is used to prepare a second mesa hole 382 by using an inductively coupled plasma etching, wherein the bottom of the second mesa hole 382 extends to the first insulating layer 28; wherein, the power of the upper electrode is 200W-1200W, the power of the lower electrode is 100W-800W, and the etching rate is 15A/s-100A/s (as shown in FIG. 13).
Step S10104, as shown in fig. 14, filling a third insulating layer 40 in the second mesa hole 382, where the third insulating layer 40 covers the first surface of the bonding layer 34, and the first surface of the bonding layer 34 is far away from the first insulating layer 28;
in step S10106, a second through hole 402 penetrating to the second semiconductor is formed in the third insulating layer 40, and a second metal is filled in the second through hole to form the second electrode 32, where the second through hole 402 is located in the second mesa hole 382, and a pore channel of the second through hole 402 overlaps with a partial pore channel of the second mesa hole 382.
As shown in fig. 15, the third insulating layer hole is prepared by a standard photolithography process and a wet etching process, and the etching solution is a BOE solution; the third insulating layer hole is then filled with a second electrode metal to form the second electrode 32, wherein the second electrode metal is in direct contact with the metal in the mirror protection layer 266.
The process of the invention is described below in relation to a specific example.
Referring to fig. 16, the method of the present invention includes:
step S151, growing an epitaxial wafer on an epitaxial substrate;
step S152, preparing a reflector 2228 on the first surface of the epitaxial wafer, and forming a reflector hole and a via in the reflector 2228;
step S153, preparing a mirror protective layer 2230 on the outer surface of the mirror, and forming a mirror protective layer hole and a walkway on the mirror protective layer 2230;
step S154, opening an MESA hole in the mirror protective layer 2230;
step S155, preparing an X insulating layer on the mirror protective layer 2230 and in the MESA hole;
step S156, forming a first through hole 2242 in a region of the X insulating layer corresponding to the MESA hole, and filling an N electrode metal in the first through hole 2242 to prepare an N electrode;
step S157, preparing a first bonding layer 262 and a second bonding layer 264, and bonding and fixing the first bonding layer 262 and the second bonding layer 264;
step S158, stripping the epitaxial substrate;
step S159, preparing a Y insulating layer on the second surface of the epitaxial wafer;
step S160, preparing a P electrode area;
step 161, preparing a Z insulating layer in the P electrode region, and preparing a P electrode hole in the Z insulating layer;
step S162, filling P metal in the P electrode hole to prepare a P electrode.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (10)
1. A light emitting diode chip, comprising:
the LED comprises a first semiconductor layer, a light emitting layer, a second semiconductor layer, a first insulating layer and a bonding layer which are sequentially stacked; and the number of the first and second groups,
a first electrode and a second electrode;
the first electrode penetrates through the first insulating layer, the second semiconductor layer and the light emitting layer and is electrically connected with the first semiconductor layer and the bonding layer;
the second electrode penetrates through the bonding layer and the first insulating layer and is electrically connected with the second semiconductor layer.
2. The light-emitting diode chip of claim 1, wherein the second semiconductor layer comprises:
the light-emitting diode comprises an inner film layer, reflectors and reflector protection layers which are sequentially stacked, wherein the reflectors are arranged on a first surface of the inner film layer at preset intervals, the first surface of the inner film layer is far away from a light-emitting layer, and the reflector protection layers and the reflectors are arranged in a one-to-one correspondence mode and wrap the reflectors;
a first preset number of first mesa holes penetrating into the first semiconductor layer are formed between the reflector protection layers, and the first insulating layer wraps the reflector protection layers and fills the first mesa holes;
a first through hole is formed in the first insulating layer filling the first mesa hole, the first electrode is filled in the first through hole, a first portion of the first electrode penetrates out of the first surface of the first insulating layer along the first through hole, and the first surface of the first insulating layer is far away from the reflector protective layer.
3. The light emitting diode chip of claim 1, wherein the bonding layer comprises:
the first bonding layer and the second bonding layer are sequentially stacked, wherein the first bonding layer covers a first surface of the first insulating layer and a first portion of the first electrode, and the first surface of the first insulating layer is far away from the light emitting layer.
4. The light emitting diode chip of claim 1, further comprising:
the second insulating layer is arranged on one side, far away from the light emitting layer, of the first semiconductor layer.
5. The light emitting diode chip of claim 1, further comprising:
a second substrate, wherein the second substrate is arranged on the first surface of the bonding layer, and the first surface of the bonding layer is far away from the first insulating layer; second mesa holes with a second preset number are formed in the second substrate, penetrate through the second substrate and reach the inside of the first insulating layer, the hole bottoms of the second mesa holes are overlapped with the first surface of the second semiconductor layer, and the first surface of the second semiconductor layer is close to the first insulating layer;
a third insulating layer filling the second mesa hole;
a second through hole is formed in a third insulating layer filling the second mesa hole, the second electrode is filled in the second through hole, a first portion of the second electrode penetrates through the first surface of the second substrate along the second through hole, and the first surface of the second substrate is far away from the first insulating layer.
6. A preparation method of a light-emitting diode chip is characterized by comprising the following steps:
preparing an epitaxial layer on a first substrate, wherein the epitaxial layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked;
depositing a first insulating layer on the epitaxial layer;
preparing a first electrode which penetrates through the first insulating layer, the first semiconductor layer and the light emitting layer and is electrically connected with the first semiconductor layer;
depositing a bonding layer on the first insulating layer, the bonding layer being electrically connected to the first electrode;
preparing a second electrode penetrating the bonding layer and the first insulating layer and electrically connected to the second semiconductor layer.
7. The method for manufacturing a light-emitting diode chip as claimed in claim 6, wherein said manufacturing an epitaxial layer on a first substrate comprises:
sequentially laminating the first semiconductor layer, the light emitting layer and the second semiconductor layer on the first surface of the first substrate;
wherein laminating the second semiconductor layer on the first surface of the light emitting layer includes:
sequentially laminating an inner film layer, a reflector and a reflector protection layer on the first surface of the light-emitting layer, wherein the first surface of the light-emitting layer is far away from the first substrate; the reflecting mirrors are arranged on the first surface of the inner film layer at preset intervals, the first surface of the inner film layer is far away from the light emitting layer, and the reflecting mirror protective layers are arranged in one-to-one correspondence with the reflecting mirrors and wrap the reflecting mirrors.
8. The method of manufacturing a light emitting diode chip of claim 7, wherein said depositing a first insulating layer on said epitaxial layer comprises:
and arranging a first preset number of first mesa holes penetrating into the first semiconductor layer between the reflector protective layers, and filling first insulating layers in the first mesa holes, wherein the reflector protective layers are wrapped by the first insulating layers.
9. The method for manufacturing a light-emitting diode chip as claimed in claim 8, wherein said manufacturing a first electrode includes:
forming a first through hole penetrating into the first semiconductor layer on the first insulating layer, and filling a first metal in the first through hole to form the first electrode, wherein a first part of the first electrode penetrates out of the first surface of the first insulating layer along the first through hole, and the first surface of the first insulating layer is far away from the mirror protection layer; the first through hole is located in the first table-board hole, and the bottom of the first through hole is overlapped with part of the bottom of the first table-board hole.
10. The method for manufacturing a light-emitting diode chip as claimed in claim 6, wherein said manufacturing a second electrode includes:
forming a second mesa hole penetrating to the first insulating layer on the second surface of the bonding layer;
filling a third insulating layer in the second mesa hole, wherein the third insulating layer covers the first surface of the bonding layer, and the first surface of the bonding layer is far away from the first insulating layer;
and opening a second through hole penetrating through the third insulating layer to the second semiconductor, and filling a second metal in the second through hole to form a second electrode, wherein the second through hole is located in the second mesa hole, and a pore channel of the second through hole is overlapped with a partial pore channel of the second mesa hole.
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Application publication date: 20210615 |