CN109755365A - A kind of light emitting diode (LED) chip with vertical structure and preparation method thereof - Google Patents
A kind of light emitting diode (LED) chip with vertical structure and preparation method thereof Download PDFInfo
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- CN109755365A CN109755365A CN201910003899.5A CN201910003899A CN109755365A CN 109755365 A CN109755365 A CN 109755365A CN 201910003899 A CN201910003899 A CN 201910003899A CN 109755365 A CN109755365 A CN 109755365A
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Abstract
The invention discloses a kind of light emitting diode (LED) chip with vertical structure, including metal layer on back, the second substrate on metal layer on back, bonded layer, etching barrier layer, reflecting layer, current-diffusion layer, epitaxial layer, insulating layer and electrode layer, second substrate is equipped with recess portion and protrusion, the surface of protrusion is higher than the surface of recess portion, the bonded layer includes center bonded layer and edge bonded layer, the recess portion of the second substrate is arranged in the center bonded layer, the protrusion of the second substrate is arranged in the edge bonded layer, etching barrier layer and insulating layer are successively set on edge bonded layer, etching barrier layer, reflecting layer, current-diffusion layer, epitaxial layer, insulating layer and electrode layer are successively set on the bonded layer of center, the electrode layer is connect through the insulating layer with epitaxial layer.Correspondingly, the present invention also provides a kind of production methods of light emitting diode (LED) chip with vertical structure.Chip of the invention, angularity is low, and yield and stability are high.
Description
Technical field
The present invention relates to LED technology fields more particularly to a kind of light emitting diode (LED) chip with vertical structure and preparation method thereof.
Background technique
Light emitting diode (Light-Emitting Diode, LED) with energy conservation and environmental protection, safety durable, photoelectricity due to turning
The features such as rate is high, controllability is strong, is widely used in the related fieldss such as display, automotive lighting, general illumination.
At present LED chip structure be broadly divided into formal dress, vertically with three kinds of upside-down mounting.Positive assembling structure is that LED is adopted at first in history
Structure, structure is simple, and process flow is quick, but since positive electrode blocks out light, affects light extraction efficiency.?
In luminous bottom surface, top surface is that sapphire face is also light-emitting surface for the electrode setting of assembling structure, solves the light-blocking technical problem of electrode,
But since levels of current transmission has current crowding, in addition upside-down mounting electrode and bottom surface contact area are small, in high-power lower difficulty
To solve heat dissipation problem, therefore, it is necessary to further find new LED structure.Then, light emitting diode (LED) chip with vertical structure comes into being, and hangs down
For straight structure LED chip since front electrode and bottom-side electrodes are respectively in the two sides of luminescent layer, electric current transmission is achieved longitudinal biography
It is defeated, the problem of improving current crowding well, utilize the high substrate of thermal conductivity, such as lining of the silicon substrate as vertical chip
Bottom realizes large area heat dissipation, so that powerful heat dissipation problem can also be readily solved.Light emitting diode (LED) chip with vertical structure is by its knot
The advantage of structure, in LED, shared share is more important in the market in recent years, becomes research hotspot.
Existing light emitting diode (LED) chip with vertical structure, former growth substrates such as Sapphire Substrate are nonconductive substrate, to replace with conduction
Substrate such as silicon substrate needs to utilize substrate transfer technology.Substrate transfer technology is usually bonding techniques and substrate desquamation technology phase
In conjunction with.Bonding process be by the epitaxial wafer of former growth substrates and transfer substrate be combined together under certain temperature and pressure, but
The problem of due to high-temperature heat expansion CTE mismatch and stress accumulation, is easy to happen great buckling deformations in bonding process, and
Extension chip size is bigger, and deformation degree is more severe.The substrate desquamation that warpage will lead to next step is easy to produce crackle, or even broken
It splits, has seriously affected the yield and technology stability of production.Reducing the angularity that bonding techniques are formed is always vertical structure LED
The important problem of chip.In addition, the excessively high global voltage that will affect light emitting diode (LED) chip with vertical structure of the Ohmic contact of bonded layer, how
The Ohmic resistance for reducing bonded layer is also one of the difficult point of bonding technology research.
Summary of the invention
Technical problem to be solved by the present invention lies in provide a kind of light emitting diode (LED) chip with vertical structure, angularity is low, ohm electricity
Hinder small, yield height.
The present invention also technical problems to be solved are, a kind of production method of light emitting diode (LED) chip with vertical structure are provided, so that core
The angularity of piece is low, and Ohmic resistance is small, and yield is high.
In order to solve the above-mentioned technical problems, the present invention provides a kind of light emitting diode (LED) chip with vertical structure, including metal layer on back,
The second substrate, bonded layer, etching barrier layer, reflecting layer, current-diffusion layer, epitaxial layer, insulating layer on metal layer on back
And electrode layer, second substrate are equipped with recess portion and protrusion, the surface of protrusion is higher than the surface of recess portion, during the bonded layer includes
The recess portion of the second substrate is arranged in heart bonded layer and edge bonded layer, the center bonded layer, and the edge bonded layer setting exists
The protrusion of second substrate, etching barrier layer and insulating layer are successively set on edge bonded layer, etching barrier layer, reflecting layer, electricity
Stream diffusion layer, epitaxial layer, insulating layer and electrode layer are successively set on the bonded layer of center, and the electrode layer runs through the insulating layer
It is connect with epitaxial layer.
As an improvement of the above scheme, the thickness of the center bonded layer is equal to the thickness of edge bonded layer, the center
Bonded layer and edge bonded layer are made of two or more in Cr, Ti, Ni, Sn, Au and Pt, with a thickness of 0.4-4 μm.
As an improvement of the above scheme, the width of the protrusion is 5-50 μm.
Correspondingly, the present invention also provides a kind of production methods of light emitting diode (LED) chip with vertical structure, comprising:
Form epitaxial layer on the first substrate, the epitaxial layer includes the n type gallium nitride layer being sequentially arranged on substrate, active
Layer and p-type gallium nitride layer；
P-type gallium nitride layer is performed etching, multiple first protrusions and multiple first recess portions are formed；
Current-diffusion layer, reflecting layer, etching barrier layer and the first bonded layer are sequentially formed on the first protrusion, it is recessed first
Etching barrier layer and the first bonded layer are sequentially formed in portion；
The second substrate is provided, second substrate is equipped with the second recess portion and second to match with the first protrusion and the first recess portion
Protrusion；
The second bonded layer is formed on the second protrusion and the second recess portion；
First bonded layer and the second bonded layer are bonded, bonded layer is formed；
Remove the first substrate and the first recess portion；
Insulating layer is formed on exposed epitaxial layer and etching barrier layer；
Electrode layer is formed, the electrode layer is connect through the insulating layer with epitaxial layer；
Metal layer on back is formed on the second substrate.
As an improvement of the above scheme, constant temperature and pressure carries out under vacuum conditions for first bonded layer and the second bonded layer
Bonding, wherein temperature is 150-350 DEG C, pressure 5-15KN, and vacuum degree is lower than 8x 10-2Pa, bonding time 5-60min.
As an improvement of the above scheme, first bonded layer and the second bonded layer are laminated construction, the first bonded layer
The top layer of top layer and the second bonded layer is Au-Au, one of Au-In, Au-Sn, Ni-Sn, Cu-Sn, Pb-In and Cu-Cu.
As an improvement of the above scheme, the bonded layer is made of two or more in Cr, Ti, Ni, Sn, Au and Pt,
With a thickness of 0.4-4 μm.
As an improvement of the above scheme, the structure of the bonded layer is Cr/Ti/Pt/Au, Cr/Ti/Pt/Sn or Au/Sn/
Pt/Sn。
As an improvement of the above scheme, the etching barrier layer be laminated construction, the etching barrier layer by Cr, Pt, Ti,
Two or more compositions in Au, Ni and TiW, with a thickness of 0.2-0.8 μm.
As an improvement of the above scheme, the metal layer on back be laminated construction, the metal layer on back by Cr, Ti, Ni,
Two or more compositions in Sn, Au and Pt, with a thickness of 0.2-1 μm.
The invention has the following beneficial effects:
1, a kind of light emitting diode (LED) chip with vertical structure provided by the invention, the second substrate is equipped with recess portion and protrusion, and recess portion correspondence is set
There are center bonded layer, protrusion to be correspondingly provided with edge bonded layer, and the surface of center bonded layer and edge bonded layer is not same flat
Face, therefore the contact area of bonded layer of the present invention greatly increases, the contact gap of bonded layer greatly reduces, and is forming bonded layer
When, bonded layer is more uniformly stressed, and is heated also more uniform, to reduce angularity, and then improves chip yield and stabilization
Property.
2, since the contact area of bonded layer of the present invention greatly increases, the contact gap of bonded layer greatly reduces, therefore key
It closes layer and combines even closer, it is not easy to which the defects of hole occur influences Ohmic contact, therefore the Ohmic resistance of bonded layer is also big
It is big to reduce.
3, the production method of a kind of light emitting diode (LED) chip with vertical structure provided by the invention, performs etching p-type gallium nitride layer, with
Multiple first protrusions and multiple first recess portions are formed, and form the first bonded layer on the first protrusion and the first recess portion, in addition, this
Invention on the second protrusion of the second substrate and the second recess portion by forming the second bonded layer, and by the first key on the first recess portion
It closes layer to be bonded with the second bonded layer of the second protrusion, the first bonded layer of the first protrusion is bonded with the second of the second recess portion
Layer is bonded, final to realize substrate transfer to form bonded layer.And pass through the concave-convex knot of the first bonded layer and the second bonded layer
Structure, the contact area of Lai Zengjia the first bonded layer and the second bonded layer, reduces contact gap between the two, is being bonded
When, the first bonded layer and the second bonded layer are more uniformly stressed, it is heated also more uniform, so that angularity is reduced, Jin Erti
High chip yield and stability.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of light emitting diode (LED) chip with vertical structure of the present invention；
Fig. 2 a is that the present invention forms the schematic diagram after epitaxial layer on the first substrate；
Fig. 2 b is that the present invention forms the schematic diagram after the first protrusion and the first recess portion；
Fig. 2 c is that the present invention forms the schematic diagram after the first bonded layer；
Fig. 2 d is the structural schematic diagram of the second substrate of the invention；
Fig. 2 e is the schematic diagram that the present invention forms the second bonded layer on the second substrate；
Fig. 2 f is that the present invention forms the schematic diagram after bonded layer；
Fig. 2 g is that the present invention removes the schematic diagram after the first substrate and the first recess portion；
Fig. 2 h is that the present invention forms the schematic diagram after insulating layer and electrode layer；
Fig. 2 i is that the present invention forms the schematic diagram after metal layer on back.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, the present invention is made into one below in conjunction with attached drawing
Step ground detailed description.
Referring to Fig. 1, a kind of light emitting diode (LED) chip with vertical structure provided by the invention, including metal layer on back 11, be set to back metal
The second substrate 12, bonded layer 13, etching barrier layer 14 on layer 11, reflecting layer 15, current-diffusion layer 16, epitaxial layer 17, insulation
Layer 18 and electrode layer 19.
Metal layer on back 11 is laminated construction, and metal layer on back 11 is by two or more in Cr, Ti, Ni, Sn, Au and Pt
Composition, with a thickness of 0.2-1 μm.Preferably, the structure of metal layer on back 11 is Cr/Pt/Au, Au/Pt/Au or Ni/Cr/Ti.
Second substrate 12 is transfer substrate, is used to support light emitting structure.Second substrate 12 of the invention is copper substrate or leads
Electric silicon substrate.It should be noted that the size of the second substrate 12 is 2-8 cuns.Since the present invention passes through bonded layer 13 for epitaxial layer
It is transferred on the second substrate 12, therefore the size of the second substrate 12 can achieve 8 cun.
Specifically, the second substrate 12 is equipped with recess portion 121 and protrusion 122, the surface of protrusion 122 is higher than the surface of recess portion 121.
Preferably, the area of recess portion 121 is greater than the area of protrusion 122, and the width of protrusion 122 is 5-50 μm.
Bonded layer 13 of the invention is for connecting epitaxial layer 17 and the second substrate 12.Specifically, bonded layer 13 includes center
Bonded layer 131 and edge bonded layer 132, the center are bonded 131 layers of recess portion 121 that the second substrate 12 is arranged in, the edge
The protrusion 122 of the second substrate 12 is arranged in bonded layer 132.The structure phase of the center bonded layer 131 and edge bonded layer 132
Together, it is made of two or more in Cr, Ti, Ni, Sn, Au and Pt.Preferably, center bonded layer 131 and edge bonded layer
132 structure is Cr/Ti/Pt/Au, Cr/Ti/Pt/Sn or Au/Sn/Pt/Sn.
When in order to guarantee bonding, bonded layer 13 uniform force and can be heated evenly, therefore the thickness of center bonded layer 131
Equal to the thickness of edge bonded layer 132.Preferably, center bonded layer 131 and edge bonded layer 132 with a thickness of 0.4-4 μm.If
The thickness of bonded layer 13 is lower than 0.4 μm, then angularity increases, it is difficult to which epitaxial layer is transferred on the second substrate；If bonded layer 13
Thickness be greater than 4 μm, then bonding time is too long, increase cost.
It should be noted that protrusion 122 of the invention is equivalent to the Cutting Road of chip, it is subsequent need along protrusion 122 into
Row cutting, to form single chip.Preferably, the width of protrusion 122 is 5-50 μm.
Specifically, etching barrier layer 14 and insulating layer 18 are successively set on edge bonded layer 132, etching barrier layer 14,
Reflecting layer 15, current-diffusion layer 16, epitaxial layer 17, insulating layer 18 and electrode layer 19 are successively set on center bonded layer 131,
In, the electrode layer 19 is connect through the insulating layer 18 with epitaxial layer 17.
Etching barrier layer 14 of the invention is for completely cutting off reflecting layer 15 and bonded layer 13, since reflecting layer 13 is by aluminium or silver etc.
The metal for being easy migration is made, therefore reflecting layer 13 is easy to happen metal ion transport diffusion, and the present invention is by being added etching resistance
Barrier 14 can prevent reflecting layer 13 from metal ion transport diffusion occurs.Specifically, etching barrier layer 14 is laminated construction, etching
Barrier layer 14 is made of two or more in Cr, Pt, Ti, Au, Ni and TiW, with a thickness of 0.2-0.8 μm.Preferably, etching resistance
The structure of barrier 14 is Cr/TiW or Cr/Pt/Au.
Specifically, reflecting layer 15 of the invention is made of Ag and/or Al, with a thickness of 100-700nm, reflectivity 80-
98%.Current-diffusion layer 16 is made by one or more of tin indium oxide (ITO), fluorine oxide tin (FTO) and aluminum zinc oxide (AZO)
At with a thickness of 25-500nm.Epitaxial layer 17 includes n type gallium nitride layer, active layer and p-type gallium nitride layer.Insulating layer 18 is by dioxy
SiClx is made, with a thickness of 150-300nm.The electrode layer 19 is made of metal.
When the epitaxial layer of existing thin-film LED and the substrate bonding of plane, contact gap will form, discontinuity,
It will also result in the even problem of uneven heating simultaneously during heating, the mismatch of epitaxial layer and the thermal expansion coefficient of transfer substrate is made
At stress can accumulate in bonded layer, it is excessive to be eventually exhibited as warpage.
Second substrate of the invention is equipped with recess portion and protrusion, and protrusion is correspondingly provided with center bonded layer, recess portion is correspondingly provided with
Edge bonded layer, and the surface of center bonded layer and edge bonded layer is in same plane, therefore the contact of bonded layer of the present invention
Area greatly increases, and the contact gap of bonded layer greatly reduces, and when forming bonded layer, bonded layer is more uniformly stressed,
It is heated also more uniform, to reduce angularity, and then improve chip yield and stability.
Further, since the contact area of bonded layer of the present invention greatly increases, the contact gap of bonded layer greatly reduces, therefore
Bonded layer combines even closer, it is not easy to which the defects of hole occur influences Ohmic contact, therefore the Ohmic resistance of bonded layer
Greatly reduce.
Secondly, the work of current spread and reflection light is played in current-diffusion layer and reflecting layer in light emitting diode (LED) chip with vertical structure
With, if etched area deposits this double-layer structure, influence the subsequent cutting technique of chip, therefore the present invention eliminate on protrusion this two
Layer structure.
Correspondingly, the present invention also provides a kind of production methods of light emitting diode (LED) chip with vertical structure, comprising the following steps:
S101, epitaxial layer is formed on the first substrate, the epitaxial layer includes the n type gallium nitride being sequentially arranged on substrate
Layer, active layer and p-type gallium nitride layer；
A referring to fig. 2 forms epitaxial layer 22 on 21 surface of substrate using MOCVD device.
The material of substrate 21 of the present invention can be sapphire, silicon carbide or silicon, or other semiconductor materials.It is preferred that
, substrate 21 of the invention is Sapphire Substrate.
The epitaxial layer 22 includes n type gallium nitride layer, active layer and the p-type gallium nitride layer being sequentially arranged on substrate.
S102, p-type gallium nitride layer is performed etching, forms multiple first protrusions and multiple first recess portions；
B referring to fig. 2 performs etching p-type gallium nitride layer using dry etching, forms multiple first protrusions 221 and multiple
First recess portion 222.
The present invention can only the p-type gallium nitride layer to epitaxial layer perform etching, active layer cannot be etched to, otherwise walked below
In rapid, when deposition-etch barrier layer and the first bonded layer are on the first recess portion 222, chip short circuit will lead to.
It should be noted that the first recess portion 222 of the invention is equivalent to the Cutting Road of chip, subsequent needs are recessed along first
Portion 222 is cut, to form single chip.Preferably, the width of the first recess portion 222 is 5-50 μm.
S103, current-diffusion layer, reflecting layer, etching barrier layer and the first bonded layer are sequentially formed on the first protrusion,
Etching barrier layer and the first bonded layer are sequentially formed on first recess portion；
C referring to fig. 2 sequentially forms current-diffusion layer 23, reflecting layer 24,25 and of etching barrier layer on the first protrusion 221
First bonded layer 26；Etching barrier layer 25 and the first bonded layer 26 are sequentially formed on the first recess portion 222.
Etching barrier layer 25 of the invention for completely cutting off reflecting layer 24 and the first bonded layer 26, due to reflecting layer 24 by aluminium or
The metal of the easy migration such as silver is made, therefore reflecting layer 24 is easy to happen metal ion transport diffusion, and the present invention is carved by being added
Erosion barrier layer 25 can prevent reflecting layer 24 from metal ion transport diffusion occurs.Specifically, etching barrier layer 25 is laminated construction,
Etching barrier layer 25 is made of two or more in Cr, Pt, Ti, Au, Ni and TiW, with a thickness of 0.2-0.8 μm.Preferably, it carves
The structure for losing barrier layer 25 is Cr/TiW or Cr/Pt/Au.
Specifically, reflecting layer 24 of the invention is made of Ag and/or Al, with a thickness of 100-700nm, reflectivity 80-
98%.Current-diffusion layer 23 is made by one or more of tin indium oxide (ITO), fluorine oxide tin (FTO) and aluminum zinc oxide (AZO)
At with a thickness of 25-500nm.
S104, the second substrate is provided, second substrate is equipped with the second recess portion to match with the first protrusion and the first recess portion
With the second protrusion；
D referring to fig. 2, the second substrate 31 provided by the invention include the second recess portion 311 and the second protrusion 312, wherein second
Recess portion 311 and the first protrusion 221 match, and the second protrusion 312 and the first recess portion 222 match.
It should be noted that the second substrate 12 of the invention is transfer substrate, it is used to support light emitting structure.Of the invention
Two substrates 12 are copper substrate or conductive silicon substrate.It should be noted that the size of the second substrate 12 is 2-8 cuns.Due to the present invention
Epitaxial layer is transferred on the second substrate 12 by bonded layer 13, therefore the size of the second substrate 12 can achieve 8 cun.
S105, the second bonded layer is formed on the second protrusion and the second recess portion；
E referring to fig. 2 forms the second bonded layer 32 on the second protrusion 312 and the second recess portion 311 respectively.
In order to enable the first bonded layer and the second bonded layer to be preferably bonded, the top layer of the first bonded layer 26 and
The top layer group of two bonded layers 32 is combined into one of Au-Au, Au-In, Au-Sn, Ni-Sn, Cu-Sn, Pb-In and Cu-Cu.Bonding
LED chip formation after the completion is placed in the recess portion center bonded layer of the second substrate and is placed in the protrusion edge bonded layer of the second substrate.
S106, the first bonded layer and the second bonded layer are bonded, form bonded layer；
First bonded layer 26 and the second bonded layer 32 are bonded by f referring to fig. 2 using bonding technology, and shape is integral
Bonded layer 33.Specifically, the second bonded layer 32 of the first bonded layer 26 and the second protrusion 312 on the first recess portion 222 carries out
Bonding, the first bonded layer 26 of the first protrusion 221 are bonded with the second bonded layer 32 of the second recess portion 311.
Bonded layer 33 of the invention is the important knot for realizing substrate transfer for connecting epitaxial layer 22 and the second substrate 31
Structure.Specifically, bonded layer 33 includes center bonded layer 331 and edge bonded layer 332, the center is bonded 331 layers of setting the
The second protrusion 312 of the second substrate 31 is arranged in second recess portion 311 of two substrates 31, the edge bonded layer 332.The center
Bonded layer 331 is identical with the structure of edge bonded layer 332, is made of two or more in Cr, Ti, Ni, Sn, Au and Pt.
Preferably, the structure of center bonded layer 331 and edge bonded layer 332 is Cr/Ti/Pt/Au, Cr/Ti/Pt/Sn or Au/Sn/Pt/
Sn。
When in order to guarantee bonding, bonded layer 33 uniform force and can be heated evenly, and the thickness of center bonded layer 331 is equal to
The thickness of edge bonded layer 332.Preferably, center bonded layer 331 and edge bonded layer 332 with a thickness of 0.4-4 μm.If bonding
The thickness of layer 33 is lower than 0.4 μm, then angularity increases, it is difficult to which epitaxial layer is transferred on the second substrate；If the thickness of bonded layer 33
Degree is greater than 4 μm, then bonding time is too long, increases cost.
It should be noted that the warpage of metal bonding layer is mainly that coefficient of thermal expansion mismatch is formed by.In order to form gold
Belong to bonding, is usually bonded under constant temperature and pressure under vacuum and carries out, and kept for a period of time.
Specifically, the bonding temperature of first bonded layer and the second bonded layer is 150-350 DEG C, pressure 5-15KN,
Vacuum degree is lower than 8x10-2Pa, bonding time 5-60min.If temperature is lower than 150 DEG C, temperature is lower than metal bonding eutectic point,
It can not be bonded；If temperature is higher than 350 DEG C, angularity is big.If pressure is lower than 5KN, bonding can not be formed；If being higher than
15KN, then pressure is excessive, and angularity is big.
Preferably, the bonding temperature of first bonded layer and the second bonded layer is 200-300 DEG C, pressure 8-13KN,
Vacuum degree is lower than 8x10-2Pa, bonding time 10-40min.
S107, the first substrate and the first recess portion are removed；
G referring to fig. 2 removes the first substrate 21 and the first recess portion 222.It is cut since the first recess portion 222 of the invention is equivalent to
It cuts, subsequent needs are cut along the first recess portion 222, and the first bonded layer in the first recess portion 222 is served as a contrast with second
Second bonded layer at bottom bonds together to form one, if continuing to retain the first recess portion 222, influences the subsequent cutting technique of chip.
S108, insulating layer is formed on exposed epitaxial layer and current-diffusion layer；
H referring to fig. 2, the deposition of insulative material on exposed epitaxial layer 22 and current-diffusion layer 23 form insulating layer
27.The insulating layer 27 is for protecting chip, it is preferred that the insulating layer 27 is made of silica, with a thickness of 150-
300nm。
S109, electrode layer is formed, the electrode layer is connect through the insulating layer with epitaxial layer.
The insulating layer 27 is performed etching, the surface of epitaxial layer 22 is etched to, electrode hole is formed, in electrode hole
Deposited metal forms electrode layer 28.The electrode layer 28 is equivalent to the N-type electrode of chip.
S110, metal layer on back is formed on the second substrate.
I referring to fig. 2 forms metal layer on back 28 using vacuum evaporation process on the second substrate 31.Wherein, back metal
Layer 29 is equivalent to the P-type electrode of chip.
Specifically, metal layer on back 29 is laminated construction, metal layer on back 29 is by two in Cr, Ti, Ni, Sn, Au and Pt
Kind or a variety of compositions, with a thickness of 0.2-1 μm.Preferably, the structure of metal layer on back 29 is Cr/Pt/Au, Au/Pt/Au or Ni/
Cr/Ti。
The present invention performs etching p-type gallium nitride layer, to form multiple first protrusions and multiple first recess portions, and first
The first bonded layer is formed on protrusion and the second protrusion, in addition, the present invention passes through in the second protrusion of the second substrate and the second recess portion
The second bonded layer of upper formation, and the first bonded layer on the first recess portion is bonded with the second bonded layer of the second protrusion, it will
First bonded layer of the first protrusion is bonded with the second bonded layer of the second recess portion, to form bonded layer, finally realizes substrate
Transfer.
The present invention passes through the concaveconvex structure of the first bonded layer and the second bonded layer, the first bonded layer of Lai Zengjia and the second bonding
The contact area of layer, reduces contact gap between the two, when being bonded, the stress of the first bonded layer and the second bonded layer
It is more uniform, it is heated also more uniform, to reduce angularity, and then improves chip yield and stability.
Further, since the contact area of bonded layer of the present invention greatly increases, the contact gap of bonded layer greatly reduces, therefore
Bonded layer combines even closer, it is not easy to which the defects of hole occur influences Ohmic contact, therefore the Ohmic resistance of bonded layer
Greatly reduce.
Above disclosed is only a preferred embodiment of the present invention, cannot limit the power of the present invention with this certainly
Sharp range, therefore equivalent changes made in accordance with the claims of the present invention, are still within the scope of the present invention.
Claims (10)
1. a kind of light emitting diode (LED) chip with vertical structure, which is characterized in that the second lining including metal layer on back, on metal layer on back
Bottom, bonded layer, etching barrier layer, reflecting layer, current-diffusion layer, epitaxial layer, insulating layer and electrode layer, second substrate are equipped with
Recess portion and protrusion, the surface of protrusion are higher than the surface of recess portion, and the bonded layer includes center bonded layer and edge bonded layer, described
The recess portion of the second substrate is arranged in center bonded layer, and the protrusion of the second substrate, etching barrier layer is arranged in the edge bonded layer
It is successively set on edge bonded layer with insulating layer, etching barrier layer, reflecting layer, current-diffusion layer, epitaxial layer, insulating layer and electricity
Pole layer is successively set on the bonded layer of center, and the electrode layer is connect through the insulating layer with epitaxial layer.
2. light emitting diode (LED) chip with vertical structure as described in claim 1, which is characterized in that the thickness of the center bonded layer is equal to side
The thickness of edge bonded layer, the center bonded layer and edge bonded layer are by two or more groups in Cr, Ti, Ni, Sn, Au and Pt
At with a thickness of 0.4-4 μm.
3. light emitting diode (LED) chip with vertical structure as described in claim 1, which is characterized in that the width of the protrusion is 5-50 μm.
4. a kind of production method of light emitting diode (LED) chip with vertical structure characterized by comprising
Form epitaxial layer on the first substrate, the epitaxial layer include the n type gallium nitride layer being sequentially arranged on substrate, active layer and
P-type gallium nitride layer；
P-type gallium nitride layer is performed etching, multiple first protrusions and multiple first recess portions are formed；
Sequentially form current-diffusion layer, reflecting layer, etching barrier layer and the first bonded layer in the first protrusion, the first recess portion successively
Form etching barrier layer and the first bonded layer；
The second substrate is provided, second substrate is convex equipped with the second recess portion and second to match with the first protrusion and the first recess portion
Portion；
The second bonded layer is formed on the second protrusion and the second recess portion；
First bonded layer and the second bonded layer are bonded, bonded layer is formed；
Remove the first substrate and the first recess portion；
Insulating layer is formed on exposed epitaxial layer and etching barrier layer；
Electrode layer is formed, the electrode layer is connect through the insulating layer with epitaxial layer；
Metal layer on back is formed on the second substrate.
5. the production method of light emitting diode (LED) chip with vertical structure as claimed in claim 4, which is characterized in that first bonded layer and
Constant temperature and pressure is bonded two bonded layers under vacuum conditions, wherein temperature is 150-350 DEG C, pressure 5-15KN, vacuum degree
Lower than 8x10-2Pa, bonding time 5-60min.
6. the production method of light emitting diode (LED) chip with vertical structure as claimed in claim 5, which is characterized in that first bonded layer and
Two bonded layers are laminated construction, and the top layer group of the top layer of the first bonded layer and the second bonded layer is combined into Au-Au, Au-In, Au-Sn,
One of Ni-Sn, Cu-Sn, Pb-In and Cu-Cu.
7. the production method of light emitting diode (LED) chip with vertical structure as claimed in claim 6, which is characterized in that the lamination knot of the bonded layer
Structure is made of two or more in Cr, Ti, Ni, Sn, Au and Pt, with a thickness of 0.4-4 μm.
8. the production method of light emitting diode (LED) chip with vertical structure as claimed in claim 7, which is characterized in that the structure of the bonded layer is
Cr/Ti/Pt/Au, Cr/Ti/Pt/Sn or Au/Sn/Pt/Sn.
9. the production method of light emitting diode (LED) chip with vertical structure as claimed in claim 4, which is characterized in that the etching barrier layer is folded
Layer structure, the etching barrier layer is made of two or more in Cr, Pt, Ti, Au, Ni and TiW, with a thickness of 0.2-0.8 μm.
10. the production method of light emitting diode (LED) chip with vertical structure as claimed in claim 4, which is characterized in that the metal layer on back is folded
Layer structure, the metal layer on back is made of two or more in Cr, Ti, Ni, Sn, Au and Pt, with a thickness of 0.2-1 μm.
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