CN103560193B - Light emitting diode chip with vertical of low cost and preparation method thereof - Google Patents
Light emitting diode chip with vertical of low cost and preparation method thereof Download PDFInfo
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- CN103560193B CN103560193B CN201310383588.9A CN201310383588A CN103560193B CN 103560193 B CN103560193 B CN 103560193B CN 201310383588 A CN201310383588 A CN 201310383588A CN 103560193 B CN103560193 B CN 103560193B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
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- H01L2933/0025—Processes relating to coatings
Abstract
The invention discloses light emitting diode chip with vertical of a kind of low cost and preparation method thereof, its structure comprises: substrate layer, and the epitaxial loayer in growth substrates is transferred on described substrate layer; Between substrate layer and epitaxial loayer, there are block protective layer, dilution protective layer and gluing layer from top to bottom successively; N electrode is positioned on epitaxial loayer.Its utilizes the dilution protective layer and block protective layer that are made up of the lamination of various metals or alloy; overcome low cost, the problem such as destructible light emitting diode construction and photoelectric properties such as resistance to corrosion that low-melting-point metal exists as gluing layer material is poor, diffusivity is strong; thus noble metal can be replaced as hot pressing bonding material; greatly reduce the preparation cost of vertical LED on the one hand; lower hot pressing temperature and pressure on the other hand; reduce the residual stress of hot pressing self, the photoelectric properties of device and reliability are improved.The present invention is mainly used on light emitting semiconductor device.
Description
Technical field
The present invention relates to light emitting semiconductor device and preparation method thereof, particularly relate to light emitting diode chip with vertical of a kind of low cost and preparation method thereof.
background technology:
From the structure of light-emitting diode, the light-emitting diode chip for backlight unit of GaN base can be divided into positive assembling structure, inverted structure and vertical stratification.The structure of tradition formal dress structure light-emitting diode chip is simple, technique relative maturity, but it has current crowding and heat radiation difficulty two large shortcomings; Inverted structure light-emitting diode chip for backlight unit effectively improves the heat dissipation problem of traditional formal dress structure light-emitting diode chip, it is by welding together light-emitting diode chip for backlight unit and the good substrate of heat conductivility, light-emitting diode chip for backlight unit is made to be upside down on substrate, thus by substrate heat radiation, be applicable to large-sized light-emitting diode chip for backlight unit.But, the same with formal dress structure light-emitting diode chip, the p of inverted structure light-emitting diode chip for backlight unit, n-electrode are still at light-emitting diode chip for backlight unit homonymy, and electric current will flow transversely through N-shaped material, the phenomenon of current crowding still exists, and limits the further increase of drive current.The light-emitting diode of vertical stratification then can solve the problem of heat radiation difficulty and current crowding effectively, and meanwhile, light emitting diode chip with vertical also solves the problem that P electrode is in the light, and improves lighting area.In addition, another large advantage of light emitting diode chip with vertical is also: after film transfer, N-shaped material is exposed, thus uses the methods such as surface coarsening to have feasibility, and this can improve the light extraction efficiency of LED greatly.Therefore, light emitting diode chip with vertical has become the development trend of great power LED, also becomes the main product of LED for illumination chip gradually.
The main distinction of the technique of light emitting diode chip with vertical and positive assembling structure, inverted structure light-emitting diode chip for backlight unit technique is to introduce film transferring technique, namely first binded by wafer hot pressing or electric plating method by epitaxial wafer together with there is the base plate bonding of high conductivity, high-termal conductivity, then remove former growth substrates by the method for laser lift-off or wet etching.The method that current industrialization production vertical structure LED is all binded by wafer hot pressing carries out film transfer, but particularly the wafer hot pressing stage of binding needs to use a large amount of precious metal materials such as gold, platinum, golden tin current thin film transfer techniques, and noble metal accounts for very large ratio in whole light emitting diode chip with vertical manufacturing cost, limit the further decline of vertical structure LED cost, and cost is still current LED light source one of bottleneck entering general illumination field on a large scale.
summary of the invention:
First object of the present invention is the light emitting diode chip with vertical providing a kind of low cost.
Second object of the present invention is the preparation method of the light emitting diode chip with vertical providing a kind of low cost; be there is by design P face protective layer, the substrate protective layer of various metals laminated construction; make the considerable wafer hot pressing bonding material required for wafer hot pressing adhesion process can adopt the common metal of low melting point, low cost; and avoid adopting the noble metals such as Au, Pt, AuSn, greatly reduce the cost preparing light emitting diode chip with vertical.
First object of the present invention is achieved in that
A kind of light emitting diode chip with vertical of low cost, comprise: substrate layer, substrate layer is by substrate back side contact layer from bottom to up successively, base plate stress modulating layer, substrate back side protective layer, supporting substrate, substrate front side block protective layer and substrate front side dilution protective layer are formed, feature is: on substrate, be provided with gluing layer successively, p face protective layer, p face ohmic contact metal layer and epitaxial loayer, p face protective layer dilutes protective layer by p face from bottom to up successively and p face block protective layer is formed, epitaxial loayer is by p-type semiconductor layer from bottom to up successively, light emitting active layer, n-type semiconductor layer and resilient coating are formed, n-electrode is positioned on n-type semiconductor layer.
Preferably, the thickness of described gluing layer is 0.5 μm ~ 5 μm.
Preferably, the thickness of described p face protective layer is 0.1 μm ~ 15 μm.
Preferably, the thickness of described p face ohmic contact metal layer is 0.05 μm ~ 0.5 μm.
Preferably, the thickness of described substrate front side dilution protective layer is 0.5 μm ~ 10 μm.
Preferably, the thickness of described substrate front side block protective layer is 0.2 μm ~ 5 μm.
Preferably, the thickness of described supporting substrate is 60 μm ~ 600 μm.
Preferably, the thickness of described base plate stress modulating layer is 1 μm ~ 20 μm.
Preferably, the thickness of described substrate back side contact layer is 0.1 μm ~ 5 μm.
Preferably, the structure of described light emitting diode chip with vertical comprises passivation layer, the figure texture layer of increase bright dipping, complementary structure, the light antireflection layer with electrode.
Second object of the present invention is achieved in that
A preparation method for the light emitting diode chip with vertical of low cost, feature is:
A, elder generation deposit resilient coating, n-type semiconductor layer, light emitting active layer and p-type semiconductor layer successively in growth substrates, form epitaxial loayer;
B, on epitaxial loayer, deposit p face ohmic contact metal layer successively and carry out graphical treatment again, make itself and n-electrode pad have complementary structure;
C, deposit and dilute by p face block protective layer and p face the p face protective layer that protective layer forms again;
D, then deposit successively in the front of supporting substrate substrate front side block protective layer and substrate front side dilution protective layer;
E, deposition gluing layer;
F, deposit substrate back side protective layer, base plate stress modulating layer and substrate back side contact layer successively at the reverse side of supporting substrate;
Epitaxial loayer and substrate are bonded together by gluing layer by G, the mode adopting wafer hot pressing to bind;
H, removal growth substrates, finally prepare the figure texture layer, passivation layer, light antireflection layer and the n-electrode that increase bright dipping, obtain finished product by common method.
The depositional mode of described gluing layer is the one of following three kinds of modes: on substrate front side dilution protective layer, deposit gluing layer; Or gluing layer is deposited on p face dilution protective layer; Or gluing layer is deposited respectively on substrate front side dilution protective layer and p face dilution protective layer.
Preferably, before grown buffer layer, first growing patterned substrate, the growth substrates after graphical can play and regulate epitaxial loayer stress, improve the important function such as LED light emission rate.
Preferably, the depositional mode of described p face ohmic contact metal layer, p face protective layer, gluing layer, substrate front side protective layer and substrate back side protective layer all adopts the mode of electron beam evaporation.
Preferably, described gluing layer is the alloy material adopting Sn, Al, In, Pb, Bi, Sb, Zn low melting point, low cost metal and formed with Ag, Cu, Au common metal.
Preferably; described p face dilution protective layer, substrate front side dilution protective layer, base plate stress modulating layer are Ag, Cu, Au, Al, Ni, Cr, W, Ti single-layer metal; or more the lamination of metal; as Cu/Ni/Cu, Ag/Ni/Ag, Cu/Ti/Ni/Ag, Cu/Ni/Ti/Mo, Cu/Ni/Ti/Al/Ti/A; or alloy, as TiW, FeNiCr, FeCoCr are formed.
Preferably, described p face block protective layer, substrate front side block protective layer, substrate back side protective layer are by various metals: Cr, Ti, Pt, Au, Ni, W, Cu or metal alloy: the lamination of TiW, FeNiCr, FeCoCr is formed.
Preferably, the material of described supporting substrate is Si, Ge, GaAs, GaP, Cu (W), Mo, C, SiO
2or more material composite base plate in one.
Preferably, the pressure that described wafer hot pressing is binded is 100kg ~ 1000Kg.
Preferably, the temperature that described wafer hot pressing is binded is 150 DEG C ~ 400 DEG C.
Preferably, described growth substrates is any one in Sapphire Substrate, silicon carbide substrates, silicon substrate, GaN substrate or AlN substrate;
The preparation method of the light-emitting diode chip for backlight unit of described vertical stratification, comprises the following structure of preparation: the figure texture layer of reflector layer, passivation layer, increase bright dipping, complementary structure, light antireflection layer with electrode.
The present invention regulates the stress of epitaxial loayer, with the reliability of the yield and chip that improve chip manufacturing by the structure and thickness regulating p face block protective layer; The stress of epitaxial loayer is regulated by the pressure and temperature regulating wafer hot pressing to bind; By regulating the thickness of base plate stress modulating layer, the evenness of substrate can be adjusted, being conducive to improving the yield of wafer and the reliability of chip.
The present invention proposes a kind of low cost metal replaces noble metal to bind the method for hot-pressed material as wafer hot pressing, it is by preparing the mode of p face dilution protective layer and substrate front side dilution protective layer respectively in the both sides of gluing layer, make low cost metal can not be diffused into p face ohmic contact layer while binding hot-pressed material as wafer hot pressing, also the firmness of the bonding between substrate and epitaxial loayer can not be affected, this method adopts low cost metal to replace gold, the hot-pressed material that the expensive metal such as gold tin are binded as wafer hot pressing, thus greatly reduce the production cost of light emitting diode (LED) chip with vertical structure.
Required for monolithic wafer of the present invention, the precious metals pt of evaporation, the thickness of Au are reduced to 2.1 microns by original 5.4 microns, assuming that employing capacity is the filming equipment of electron beam evaporation platform as metal of 100 × 2 inch plaques, each complete flowing water processing procedure can save precious metals pt, the amount of Au is 55g/100 sheet, this greatly reduces the cost of product, improves productivity effect.
The present invention is suitable for the gallium nitride based LED film transfer of the substrate Epitaxial growth in silicon substrate, Sapphire Substrate, silicon carbide substrates and prior art field thereof to new substrate to prepare light emitting diode (LED) chip with vertical structure.
accompanying drawing illustrates:
Fig. 1 is the structure chart of a kind of light emitting diode (LED) chip with vertical structure using method of the present invention to obtain;
Fig. 2 be growth substrates graphical after profile;
Fig. 3 is epitaxial wafer generalized section;
Fig. 4 is the generalized section after p face ohmic contact metal layer preparing by epitaxial wafer;
Fig. 5 has prepared the generalized section after the protective layer of p face;
Fig. 6 deposited the later generalized section of gluing layer on the substrate layer;
Fig. 7 is the generalized section after LED film and substrate layer bond;
Fig. 8 gets rid of the generalized section after former growth substrates;
Fig. 9 is the generalized section after chip trimming;
Figure 10 is the generalized section after chip surface alligatoring;
Figure 11 be chip passivation after generalized section;
Figure 12 is the generalized section after n-electrode preparation.
embodiment:
Below in conjunction with accompanying drawing, embodiments of the invention are described in detail.The particular content that the present invention protects is not limited only to following described various examples of implementation, and any apparent amendment make following examples or reconfiguring of various example key element are all subject to protection of the present invention.
Embodiments of the present invention are suitable for the gallium nitride based LED film transfer of the substrate Epitaxial growth in silicon substrate, Sapphire Substrate, silicon carbide substrates and prior art field thereof to new substrate to prepare light emitting diode (LED) chip with vertical structure.
Embodiment:
The invention provides a kind of light emitting diode chip with vertical of low cost, its structure comprises: substrate layer, gluing layer, p face protective layer, P face ohmic contact metal layer, epitaxial loayer and n-electrode; In addition, in order to improve reliability or the luminous efficiency of LED chip, chip structure also preferably include prepare passivation layer, the figure texture layer that increases bright dipping, with the complementary structure of electrode and light antireflection layer in one or more.
The present invention also provides the preparation method of the light emitting diode chip with vertical of above-mentioned low cost.For the ease of understanding, first sketch whole process prepared by its chip:
A, growing patterned substrate;
B, growing gallium nitride base LED film, i.e. epitaxial loayer;
C, deposition p face ohmic contact layer, and carry out graphical treatment, make itself and n-electrode pad have complementary structure;
D, deposition p face protective layer;
E, prepare substrate layer: deposition substrate straight tackling protective layer, substrate front side dilution protective layer and substrate back side protective layer, base plate stress modulating layer and substrate back side contact layer on supporting substrate;
F, substrate front side dilution protective layer on deposit gluing layer;
Epitaxial loayer and substrate layer are bonded together, and remove former growth substrates by G, the method adopting wafer hot pressing to bind;
The trimming process of H, epitaxial loayer film;
The Surface Texture process of I, epitaxial loayer film;
J, deposit passivation layer make passivation layer figure by lithography;
K, preparation n-electrode and pad.
Said process is described in detail as follows:
Fig. 2 be growth substrates graphical after profile.In figure, 000 is growth substrates, and 001 is the convex wall in growth substrates 000, and growth substrates 000 has been divided into the growth platform of cyclic array formula by convex wall 001.The material of convex wall 001 is different from growth substrates 000, and its special character is: when adopting metallochemistry CVD (Chemical Vapor Deposition) method growing gallium nitride base LED film, the LED film except resilient coating 100 can not grow on this convex wall 001.Growth substrates 000 can be any one in Sapphire Substrate, silicon substrate, silicon carbide substrates and existing gallium nitride based LED technical field in film growth substrate.The growth substrates 000 of the present embodiment is silicon substrate.Convex wall 001 on silicon substrate can regulate the stress between epitaxial loayer film and growth substrates 000 effectively, reduces the generation of crackle in epitaxial loayer.Can be the shapes such as square, triangle, rectangle, rhombus by the growth platform that convex wall 001 is separated into, the present embodiment be square.
Fig. 3 is epitaxial wafer generalized section.It adopts the method for metallochemistry vapour deposition to obtain, and its epitaxial loayer at least comprises resilient coating 100, n semiconductor layer 101, light emitting active layer 102, p-type semiconductor layer 103.As shown in Figure 3, the convex wall 001 of growth substrates 000 only grown resilient coating 100, other layers of gallium nitride based LED film do not grow on convex wall 001, complete square LED film is then grown in the growth platform of silicon substrate, thus groove is defined between each square LED film square, groove can play the important function regulating LED membrane stress.
Fig. 4 is the generalized section after p face ohmic contact metal layer preparing by epitaxial wafer.Deposition p face ohmic contact metal layer 201 can be the metal laminated of nickel and silver, and also can be fine silver, can also be the alloy of combination in any in the metals such as silver, platinum, nickel, palladium, rhodium, aluminium.Before preparation p face ohmic contact metal layer 201, can in the enterprising line activating process of p-type semiconductor layer 103, specific implementation method: any one metal in first deposited gold, platinum, nickel, palladium, silver, cobalt or the lamination of combination in any, first make it form p face ohmic contact layer 201 and anneal, then removed; Or directly p-type semiconductor layer 103 is at high temperature annealed.Deposition p face ohmic contact layer 201 front and rear, can carry out graphical treatment to p surface semiconductor layer 103 and p face ohmic contact layer 201 respectively, to form complementary structure with the follow-up n-electrode that will prepare and pad.In addition, in order to improve the light extraction efficiency of LED, reflector layer can be deposited after p face ohmic contact layer 201, or the p face ohmic contact layer 201 of deposition inherently has good reflecting effect.
fig. 5 has prepared the generalized section after the protective layer of p face.P face protective layer comprises p face block protective layer 202 and p face dilution protective layer 203.Preferably, p face block protective layer 202 be a kind of metal in Cr, Ti, Pt, Au, W, the alloy that formed of various metals or laminated construction; Preferably dilution protective layer 203 in p face is a kind of single-layer metal in Ag, Cu, Au, Al, Fe, Ni, Cr, W, Mo, Ir, Zr, Ti, or more the lamination of metal: Cu/Ni/Cu, Ag/Ni/Ag, Cu/Ti/Ni/Ag, Cu/Ni/Ti/Mo, Cu/Ni/Ti/Al/Ti/Ag.The thickness range on barrier layer, p face 202 0.1 μm ~ 5 μm, preferably, thickness is 0.5 μm ~ 1.5 μm; The thickness range of p face diluent zone 203 0.5 μm ~ 10 μm, preferably, thickness is 2 μm ~ 4 μm.
fig. 6 deposited the later generalized section of gluing layer 400 on the substrate layer.Substrate layer comprises supporting substrate 300, substrate front side block protective layer 301, substrate front side dilution protective layer 302, substrate back side protective layer 303, base plate stress modulating layer 304 and substrate back side contact layer 305.Adopt the mode of electron beam evaporation; first in the front of supporting substrate 300, deposition substrate straight tackling protective layer 301, substrate front side dilute protective layer 302 successively; then at reverse side deposition substrate reverse side protective layer 303, base plate stress modulating layer 304 and the substrate back side contact layer 305 successively of supporting substrate 300, finally deposition gluing layer 400 on substrate front side dilution protective layer 302.Gluing layer 400 can only be deposited on above substrate front side dilution protective layer 302, also can only be deposited on above p face dilution protective layer 203, also can be deposited on above substrate front side dilution protective layer 302 and p face dilution protective layer 203 simultaneously.Described supporting substrate 300 is any one in silicon substrate, metal substrate, ceramic substrate or other composite base plates, and the supporting substrate 300 of the present embodiment is silicon substrate, and the thickness of supporting substrate 300 is between 60 μm ~ 600 μm.Preferably, the thickness of supporting substrate 300 is between 100 μm ~ 200 μm.Preferably, substrate front side block protective layer 301 adopts a kind of single-layer metal in Cr, Ti, Pt, Au, W, or more the alloy of metal and laminated construction, thickness is 0.5 μm ~ 1.5 μm.Preferably; substrate front side dilution protective layer 302 adopts a kind of single-layer metal such as Ag, Cu, Au, Al, Fe, Ni, Cr, W, Mo, Ir, Zr, Ti; or more the lamination of metal: Cu/Ni/Cu, Ag/Ni/Ag, Cu/Ti/Ni/Ag, Cu/Ni/Ti/Mo, Cu/Ni/Ti/Al/Ti/Ag, thickness is 3 μm ~ 4 μm.Preferably, substrate back side protective layer 303 adopts the laminated construction of the various metals such as Cr, Ti, Pt, Au, W, and thickness is 0.3 μm ~ 1.0 μm.Preferably, base plate stress modulating layer 304 adopts the single-layer metals such as Ag, Cu, Au, Al, Ni, Ti, or more the lamination of metal: Cu/Ni/Cu, Ag/Ni/Ag, Cu/Ti/Ni/Ag, Cu/Ni/Ti/Al/Ti/Ag etc., thickness is 6 μm ~ 14 μm.Preferably, substrate back side contact layer 305 adopts a kind of physicochemical properties such as Pt, Au, Ag stablize and have the single-layer metal of good heat conductive electric conducting material, or two or more metal laminated such as Pt/Au/Pt/Au, or alloy A uSn, AgSn etc., thickness is 0.1 μm ~ 2.5 μm.Preferably, 400 alloys adopting the low melting point such as Sn, Al, In, Bi, Pb, Zn, Sb, low cost metal and formed with the common metal such as Ag, Cu, Fe, Au, thickness is 0.5 μm ~ 5 μm.
Fig. 7 is the generalized section after LED film and substrate layer bond.The bonding of LED film and substrate layer is the mode adopting wafer hot pressing to bind.The temperature and pressure that wafer hot pressing is binded and the material of gluing layer 400 will affect the firmness that LED film and substrate layer bond; in addition; the temperature and pressure that can bind by controlling wafer hot pressing regulates the stress state of epitaxial wafer, also can by the stress state selecting the depositing temperature etc. of the material category of gluing layer 400, p face ohmic contact metal layer 201, p face block protective layer 202 and p face dilution protective layer 203 to regulate epitaxial wafer.For Sn as gluing layer 400 material, preferably, the temperature that wafer hot pressing is binded is at 230 DEG C ~ 280 DEG C, and pressure is at 100Kg ~ 600Kg.
Fig. 8 gets rid of the generalized section after former growth substrates.Growth substrates 000 in the present embodiment is silicon substrate, removes silicon substrate and usually adopts the method for wet etching, and the method technology maturation, simple to operate, cost is low.While removal growth substrates 000, the convex wall 001 on it also can be removed, and so far just to achieve LED film by primary long substrate-transfer to the process of the film transfer of substrate layer.As shown in Figure 8, after film transfer, LED film presents periodic array structure, fluted between each box-shaped film, and this groove correspond to the convex wall 001 in former growth substrates 000; In addition, can also see film turn after resilient coating 100 exposed, so just can be improved the light extraction efficiency of LED by techniques such as surface coarsenings.
What the present embodiment adopted is box-shaped patterned substrate, and as mentioned above, the LED film main stor(e)y except resilient coating only grows in foursquare growth platform.Due to edge effect, poor at the usual crystal mass of LED film at square edge, growth thickness is thicker, is required to be follow-up dicing processes slot milling in addition, therefore needs the edge of each square LED film to remove, i.e. trimming.
Fig. 9 is the generalized section after chip trimming.Trimming can adopt the method for photoetching and wet etching to carry out, and also can be undertaken by the method for photoetching and dry etching.Usually first one deck SiO is grown before trimming photoetching
2, the material such as SiN or metal as mask layer, prepare figure by photoetching process subsequently, the method finally by wet etching or dry etching removes the skirt materials needing to remove.
Figure 10 is the generalized section after chip surface alligatoring.Roughened layer 500 adopts the method preparation of wet etching usually, the Surface Texture process of other form, such as photonic crystal etc., usually adopts the method for photoetching technique and dry etching to carry out.
Surface coarsening process and trimming technique, regardless of the sequencing of processing, first surface coarsening process can be carried out trimming technique again, also can first carry out the surface coarsening process again of trimming technique.
Figure 11 be chip passivation after generalized section.Passivation layer 600 usually adopts the method for physics or chemistry to prepare the dielectric materials such as SiO2, SiN, polyimides at chip surface, passivation and protect IC surface and edge.
The sequencing of passivation, trimming and surface coarsening also can carry out like this: first trimming, carries out boundary-passivated subsequently, then roughening treatment, finally can select whether to carry out surface passivation.
Figure 12 is the generalized section after n-electrode preparation.N-electrode 700 can adopt the method for photoetching and wet etching to prepare, and also can be prepared by the method for photoetching and stripping.Preferably, n-electrode 700 be electric conductivity better and the metal material of better ohmic contact can be formed with n-type semiconductor, Pt, Au, Al, Ti, Cr, Ni, Cu, Ag etc., thickness is 1 μm ~ 10 μm.
Claims (10)
1. the light emitting diode chip with vertical that can reduce costs, comprise: substrate layer, substrate layer is by substrate back side contact layer from bottom to up successively, base plate stress modulating layer, substrate back side protective layer, supporting substrate, substrate front side block protective layer and substrate front side dilution protective layer are formed, it is characterized in that: on substrate layer, be provided with gluing layer successively, p face protective layer, p face ohmic contact metal layer and epitaxial loayer, p face protective layer dilutes protective layer by p face from bottom to up successively and p face block protective layer is formed, epitaxial loayer is by p-type semiconductor layer from bottom to up successively, light emitting active layer, n-type semiconductor layer and resilient coating are formed, n-electrode is positioned on n-type semiconductor layer.
2. light emitting diode chip with vertical according to claim 1; it is characterized in that: the thickness of described gluing layer is 0.5 μm ~ 5 μm; the thickness of described p face protective layer is 0.1 μm ~ 15 μm; the thickness of described substrate front side dilution protective layer is 0.5 μm ~ 10 μm; the thickness of described substrate front side block protective layer is 0.2 μm ~ 5 μm; the thickness of described supporting substrate is 60 μm ~ 600 μm; the thickness of described base plate stress modulating layer is 1 μm ~ 20 μm, and the thickness of described substrate back side contact layer is 0.1 μm ~ 5 μm.
3. a preparation method for the light emitting diode chip with vertical that can reduce costs, is characterized in that:
A, elder generation deposit resilient coating, n-type semiconductor layer, light emitting active layer and p-type semiconductor layer successively in growth substrates, form epitaxial loayer;
B, on epitaxial loayer, deposit p face ohmic contact metal layer successively and carry out graphical treatment again, make itself and n-electrode pad have complementary structure;
C, deposit and dilute by p face block protective layer and p face the p face protective layer that protective layer forms again;
D, then deposit successively in the front of supporting substrate substrate front side block protective layer and substrate front side dilution protective layer;
E, deposition gluing layer;
F, deposit substrate back side protective layer, base plate stress modulating layer and substrate back side contact layer successively at the reverse side of supporting substrate;
Epitaxial loayer and substrate are bonded together by gluing layer by G, the mode adopting wafer hot pressing to bind;
H, removal growth substrates, finally prepare the figure texture layer, passivation layer, light antireflection layer and the n-electrode that increase bright dipping, obtain finished product by common method.
4. preparation method according to claim 3, is characterized in that: described gluing layer is the alloy material adopting Sn, Al, In, Pb, Bi, Sb, Zn low melting point, low cost metal and formed with Ag, Cu, Au common metal.
5.
preparation method according to claim 3; it is characterized in that: described p face dilution protective layer, substrate front side dilution protective layer, base plate stress modulating layer are Ag, Cu, Au, Al, Ni, Cr, W, Ti single-layer metal; or more the lamination of metal, or more the alloy of metal form.
6.
preparation method according to claim 3, is characterized in that: described p face block protective layer, substrate front side block protective layer, substrate back side protective layer are by various metals: Cr, Ti, Pt, Au, Ni, W, Cu, or more metal alloy lamination form.
7.
preparation method according to claim 3, is characterized in that: the material of described supporting substrate is the one in the composite base plate of Si, Ge, GaAs, GaP, CuW, Mo, C, SiO2 or more material.
8.
preparation method according to claim 3, is characterized in that: the pressure that described wafer hot pressing is binded is 100kg ~ 1000Kg.
9.
preparation method according to claim 3, is characterized in that: the temperature that described wafer hot pressing is binded is 150 DEG C ~ 400 DEG C.
10.
preparation method according to claim 3, is characterized in that: described growth substrates is any one in Sapphire Substrate, silicon carbide substrates, silicon substrate, GaN substrate or AlN substrate.
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| CN104362224B (en) * | 2014-09-22 | 2017-01-18 | 南昌大学 | Method for manufacturing substrate of LED thin film chip and structure of substrate |
| CN104795472B (en) * | 2015-03-23 | 2017-11-07 | 易美芯光（北京）科技有限公司 | A kind of preparation method of light emitting semiconductor device |
| KR102351775B1 (en) * | 2015-11-18 | 2022-01-14 | 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. | Image forming apparatus and light emitting device therein |
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