CN103560193A - Vertical structure light emitting diode chip with low cost and preparation method thereof - Google Patents
Vertical structure light emitting diode chip with low cost and preparation method thereof Download PDFInfo
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- CN103560193A CN103560193A CN201310383588.9A CN201310383588A CN103560193A CN 103560193 A CN103560193 A CN 103560193A CN 201310383588 A CN201310383588 A CN 201310383588A CN 103560193 A CN103560193 A CN 103560193A
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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Abstract
The invention discloses a vertical structure light emitting diode chip with low cost and a preparation method thereof. The structure of the chip comprises a base plate layer. An epitaxial layer growing on a substrate is transferred to the base plate layer. A barrier protection layer, a dilution protection layer and an adhesive layer are orderly arranged from top to bottom between the base plate layer and the epitaxial layer. An N electrode is on the epitaxial layer. By using the dilution protection layer and the barrier protection layer which are formed by the overlapping of many kinds of metal or alloy, a problem that low cost and low melting point metal which is taken as a bonding layer material has the problems of poor corrosion resistance ability, strong diffusion ability, easy destroying of the structure and photoelectric performance of the light emitting diode and the like is overcome, thus the dilution protection layer and the barrier protection layer can replace noble metal to be a hot pressing adhesive material, on one hand, the preparation cost of the vertical structure light emitting diode chip is greatly reduced, one the other hand, the hot pressing temperature and pressure are low, the residual stress of hot pressing is reduced, and the photoelectric performance and reliability of a device are raised. The vertical structure light emitting diode chip is mainly used in a semiconductor light emitting device.
Description
Technical field
The present invention relates to light emitting semiconductor device and preparation method thereof, relate in particular to a kind of light emitting diode chip with vertical and preparation method thereof cheaply.
background technology:
From the structure of light-emitting diode, the light-emitting diode chip for backlight unit of GaN base can be divided into positive assembling structure, inverted structure and vertical stratification.Tradition formal dress structure light-emitting diode chip simple in structure, technique is relatively ripe, yet it has current crowding and heat radiation difficulty two large shortcomings; Inverted structure light-emitting diode chip for backlight unit has improved the heat dissipation problem of traditional formal dress structure light-emitting diode chip effectively, it is by welding together light-emitting diode chip for backlight unit and the good substrate of heat conductivility, light-emitting diode chip for backlight unit is upside down on substrate, thereby can dispel the heat by substrate, be applicable to large-sized light-emitting diode chip for backlight unit.But, the same with formal dress structure light-emitting diode chip, the p of inverted structure light-emitting diode chip for backlight unit, n electrode are still at light-emitting diode chip for backlight unit homonymy, and electric current is crossed N-shaped material by cross-current, the phenomenon of current crowding still exists, and has limited the further increase of drive current.The light-emitting diode of vertical stratification can solve the problem of heat radiation difficulty and current crowding effectively, and meanwhile, light emitting diode chip with vertical has also solved the problem that P electrode is in the light, and has improved lighting area.In addition, another large advantage of light emitting diode chip with vertical is also: after film transfer, N-shaped material is exposed, thereby uses the methods such as surface coarsening to have feasibility, and this can improve the light extraction efficiency of LED greatly.Therefore, light emitting diode chip with vertical has become the development trend of great power LED, also becomes gradually the main product of LED for illumination chip.
The technique of light emitting diode chip with vertical is to have introduced film transfer technology with the main distinction of positive assembling structure, inverted structure light-emitting diode chip for backlight unit technique, first by wafer hot pressing, bind or electric plating method by epitaxial wafer together with thering is the base plate bonding of high conductivity, high-termal conductivity, then by the method for laser lift-off or wet etching, remove former growth substrates.The method that the production of industrialization at present vertical structure LED all binds by wafer hot pressing is carried out film transfer, particularly but the wafer hot pressing bonding stage need to be used the precious metal materials such as a large amount of gold, platinum, golden tin to current thin film transfer techniques, and noble metal accounts for very large ratio in whole light emitting diode chip with vertical manufacturing cost, limit the further decline of vertical structure LED cost, and cost is still current LED light source, entered on a large scale one of the bottleneck in general illumination field.
summary of the invention:
First object of the present invention is to provide a kind of light emitting diode chip with vertical cheaply.
Second object of the present invention is to provide a kind of preparation method of light emitting diode chip with vertical cheaply; P face protective layer, the substrate protective layer by design with various metals laminated construction; make the needed considerable wafer hot pressing of wafer hot pressing adhesion process bonding material can adopt low melting point, common metal cheaply; and avoid adopting the noble metals such as Au, Pt, AuSn, greatly reduce the cost of preparing light emitting diode chip with vertical.
First object of the present invention is achieved in that
A kind of light emitting diode chip with vertical cheaply, comprise: substrate layer, substrate layer is by substrate reverse side contact layer from bottom to up successively, base plate stress modulating layer, substrate reverse side protective layer, supporting substrate, substrate front side block protective layer and substrate front side dilution protective layer form, feature is: on substrate, be provided with successively gluing layer, p face protective layer, p face ohmic contact metal layer and epitaxial loayer, p face protective layer is by p face from bottom to up dilution protective layer and p face block protective layer form successively, epitaxial loayer is by p-type semiconductor layer from bottom to up successively, luminescence activity layer, N-shaped semiconductor layer and resilient coating form, n electrode is positioned on N-shaped semiconductor layer.
Preferably, the thickness of described gluing layer is 0.5um～5um.
Preferably, the thickness of described p face protective layer is 0.1 um～15um.
Preferably, the thickness of described p face ohmic contact metal layer is 0.05um～0.5 um.
Preferably, the thickness of described substrate front side dilution protective layer is 0.5 um～10 um.
Preferably, the thickness of described substrate front side block protective layer is 0.2um～5um.
Preferably, the thickness of described supporting substrate is 60um～600um.
Preferably, the thickness of described base plate stress modulating layer is 1 um～20 um.
Preferably, the thickness of described substrate reverse side contact layer is 0.1 um～5 um.
Preferably, the structure of described light emitting diode chip with vertical comprise passivation layer, increase bright dipping figure texture layer, with complementary structure, the light antireflection layer of electrode.
Second object of the present invention is achieved in that
A preparation method for light emitting diode chip with vertical cheaply, feature is:
A, first resilient coating, N-shaped semiconductor layer, luminescence activity layer and the p-type semiconductor layer of depositing successively in growth substrates, form epitaxial loayer;
B, on epitaxial loayer, deposit successively p face ohmic contact metal layer and carry out graphical treatment again, make itself and n electrode pad there is complementary structure;
C, deposit the p face protective layer being formed by p face block protective layer and p face dilution protective layer again;
D, then in the front of supporting substrate, deposit successively substrate front side block protective layer and substrate front side dilution protective layer;
E, deposition gluing layer;
F, at the reverse side of supporting substrate, deposit successively substrate reverse side protective layer, base plate stress modulating layer and substrate reverse side contact layer;
G, the mode that adopts wafer hot pressing to bind are bonded together epitaxial loayer and substrate by gluing layer;
H, removal growth substrates, finally, by figure texture layer, passivation layer, light antireflection layer and the n electrode of common method preparation increase bright dipping, obtain finished product.
The depositional mode of described gluing layer is a kind of of following three kinds of modes: on substrate front side dilution protective layer, deposit gluing layer; Or deposit gluing layer on p face dilution protective layer; Or deposit respectively gluing layer on substrate front side dilution protective layer and p face dilution protective layer.
Preferably, before grown buffer layer, first growing patterned substrate, the growth substrates after graphical can play and regulate epitaxial loayer stress, improve the important function such as LED light emission rate.
Preferably, the depositional mode of described p face ohmic contact metal layer, p face protective layer, gluing layer, substrate front side protective layer and substrate reverse side protective layer all adopts the mode of electron beam evaporation.
Preferably, the alloy material of described gluing layer for adopting Sn, Al, In, Pb, Bi, Sb, Zn low melting point, low-cost metal and forming with Ag, Cu, Au common metal.
Preferably; described p face dilution protective layer, substrate front side dilution protective layer, base plate stress modulating layer are Ag, Cu, Au, Al, Ni, Cr, W, Ti single-layer metal; or the lamination of above metal; as Cu/Ni/Cu, Ag/Ni/Ag, Cu/Ti/Ni/Ag, Cu/Ni/Ti/Mo, Cu/Ni/Ti/Al/Ti/A; or alloy, as TiW, FeNiCr, FeCoCr form.
Preferably, described p face block protective layer, substrate front side block protective layer, substrate reverse side protective layer form by the lamination of various metals: Cr, Ti, Pt, Au, Ni, W, Cu or metal alloy: TiW, FeNiCr, FeCoCr.
Preferably, the material of described supporting substrate is Si, Ge, GaAs, GaP, Cu (W), Mo, C, SiO
2or a kind of in the composite base plate of above material.
Preferably, the pressure that described wafer hot pressing is binded is 100kg～1000Kg.
Preferably, the temperature that described wafer hot pressing is binded is 150 ℃～400 ℃.
Preferably, described growth substrates is any one in Sapphire Substrate, silicon carbide substrates, silicon substrate, GaN substrate or AlN substrate;
The preparation method of the light-emitting diode chip for backlight unit of described vertical stratification, comprises the following structure of preparation: the figure texture layer of reflector layer, passivation layer, increase bright dipping, with complementary structure, the light antireflection layer of electrode.
The present invention can be by regulating the structure of p face block protective layer and the stress that thickness regulates epitaxial loayer, to improve the reliability of yield and the chip of chip manufacturing; By the pressure and temperature that regulates wafer hot pressing to bind, regulate the stress of epitaxial loayer; By regulating the thickness of base plate stress modulating layer, can adjust the evenness of substrate, be conducive to improve the reliability of yield and the chip of wafer.
The present invention proposes the low-cost metal of a kind of use replaces noble metal as wafer hot pressing, to bind the method for hot-pressed material, it prepares respectively the mode of p face dilution protective layer and substrate front side dilution protective layer by the both sides at gluing layer, make low-cost metal can not be diffused into p face ohmic contact layer when binding hot-pressed material as wafer hot pressing, can not affect the firm degree of the bonding between substrate and epitaxial loayer yet, this method adopts low-cost metal to replace gold, the hot-pressed material that the expensive metal such as gold tin are binded as wafer hot pressing, thereby greatly reduce the production cost of light emitting diode (LED) chip with vertical structure.
The precious metals pt of the required evaporation of monolithic wafer of the present invention, the thickness of Au are reduced to 2.1 microns by original 5.4 microns, suppose that employing capacity is that the electron beam evaporation platform of 100 * 2 inches of sheets is as the filming equipment of metal, the amount that each complete flowing water processing procedure can be saved precious metals pt, Au is 55g/100 sheet, the cost that this greatly reduces product, has improved productivity effect.
The present invention is suitable for epitaxially grown gallium nitride based LED film transfer on the substrate in silicon substrate, Sapphire Substrate, silicon carbide substrates and prior art field thereof to new substrate and prepares light emitting diode (LED) chip with vertical structure.
accompanying drawing explanation:
Fig. 1 is the structure chart that uses a kind of light emitting diode (LED) chip with vertical structure that method of the present invention can obtain;
Fig. 2 is the profile of growth substrates after graphical;
Fig. 3 is epitaxial wafer generalized section;
Fig. 4 is the generalized section of preparing on epitaxial wafer after p face ohmic contact metal layer;
Fig. 5 has prepared p face protective layer generalized section afterwards;
Fig. 6 has deposited the generalized section after gluing layer on substrate layer;
Fig. 7 is the generalized section after LED film and substrate layer bonding;
Fig. 8 gets rid of former growth substrates generalized section afterwards;
Fig. 9 is the generalized section after chip trimming;
Figure 10 is the generalized section after chip surface alligatoring;
Figure 11 is the generalized section after chip passivation;
Figure 12 is the generalized section after the preparation of n electrode.
embodiment:
Below in conjunction with accompanying drawing, embodiments of the invention are elaborated.The particular content that the present invention protects is not limited only to following described various examples of implementation, and reconfiguring of any apparent modification that following examples is made or various example key elements is all subject to protection of the present invention.
Embodiments of the present invention are suitable for epitaxially grown gallium nitride based LED film transfer on the substrate in silicon substrate, Sapphire Substrate, silicon carbide substrates and prior art field thereof to new substrate and prepare light emitting diode (LED) chip with vertical structure.
Embodiment:
The invention provides a kind of light emitting diode chip with vertical cheaply, its structure comprises: substrate layer, gluing layer, p face protective layer, P face ohmic contact metal layer, epitaxial loayer and n electrode; In addition, in order to improve reliability or the luminous efficiency of LED chip, chip structure also preferably include the figure texture layer preparing passivation layer, increase bright dipping, with the complementary structure of electrode and light antireflection layer in one or more.
The present invention also provides the preparation method of above-mentioned light emitting diode chip with vertical cheaply.For the ease of understanding, first sketch whole process prepared by its chip:
A, growing patterned substrate;
B, growing gallium nitride base LED film, i.e. epitaxial loayer;
C, deposition p face ohmic contact layer, and carry out graphical treatment, make itself and n electrode pad there is complementary structure;
D, deposition p face protective layer;
E, prepare substrate layer: deposition substrate straight tackling protective layer, substrate front side dilution protective layer and substrate reverse side protective layer, base plate stress modulating layer and substrate reverse side contact layer on supporting substrate;
F, on substrate front side dilution protective layer, deposit gluing layer;
G, the method that adopts wafer hot pressing to bind are bonded together epitaxial loayer and substrate layer, and remove former growth substrates;
The trimming of H, epitaxial loayer film is processed;
The Surface Texture of I, epitaxial loayer film is processed;
J, deposit passivation layer also make passivation layer figure by lithography;
K, preparation n electrode and pad.
Said process is described in detail as follows:
Fig. 2 is the profile of growth substrates after graphical.In figure, 000 is growth substrates, the 001st, and the convex wall in growth substrates 000, convex wall 001 has been divided into growth substrates 000 growth platform of cyclic array formula.The material of convex wall 001 is different from growth substrates 000, and its special character is: while adopting metallochemistry CVD (Chemical Vapor Deposition) method growing gallium nitride base LED film, the LED film except resilient coating 100 can not be grown on this convex wall 001.Growth substrates 000 can be any in film growth substrate in Sapphire Substrate, silicon substrate, silicon carbide substrates and existing gallium nitride based LED technical field.The growth substrates 000 of the present embodiment is silicon substrate.Convex wall 001 on silicon substrate can regulate the stress between epitaxial loayer film and growth substrates 000 effectively, reduces the generation of crackle in epitaxial loayer.The growth platform being separated into by convex wall 001 can be the shapes such as square, triangle, rectangle, rhombus, and the present embodiment is square.
Fig. 3 is epitaxial wafer generalized section.It is to adopt the method for metallochemistry vapour deposition to obtain, and its epitaxial loayer at least comprises resilient coating 100, n semiconductor layer 101, luminescence activity layer 102, p-type semiconductor layer 103.As shown in Figure 3, the resilient coating 100 of only having grown on the convex wall 001 of growth substrates 000, the not growth on convex wall 001 of other layers of gallium nitride based LED film, the square LED film of having grown complete in the growth platform of silicon substrate, thereby between each square LED film square, formed groove, groove can play the important function that regulates LED membrane stress.
Fig. 4 is the generalized section of preparing on epitaxial wafer after p face ohmic contact metal layer.Deposition p face ohmic contact metal layer 201 can be the metal laminated of nickel and silver, can be also fine silver, can also be the alloy of combination in any in the metals such as silver, platinum, nickel, palladium, rhodium, aluminium.Before preparation p face ohmic contact metal layer 201, can process at the enterprising line activating of p-type semiconductor layer 103, specific implementation method: any one metal in first deposited gold, platinum, nickel, palladium, silver, cobalt or the lamination of combination in any, first make it form p face ohmic contact layer 201 and anneal, then by its removal; Or directly p-type semiconductor layer 103 is at high temperature annealed.Deposition p face ohmic contact layer 201 front and rears, can carry out graphical treatment to p surface semiconductor layer 103 and p face ohmic contact layer 201 respectively, to form complementary structure with the follow-up n electrode that will prepare and pad.In addition, in order to improve the light extraction efficiency of LED, can be at the rear deposition reflector layer of p face ohmic contact layer 201, or the p face ohmic contact layer 201 of deposition itself just has good reflecting effect.
Fig. 5 has prepared p face protective layer generalized section afterwards.P face protective layer comprises p face block protective layer 202 and p face dilution protective layer 203.Preferably, p face block protective layer 202 is various metals or the metal alloys such as Cr, Ti, Pt, Au, W, as the laminated construction of TiW etc.; Preferably p face dilutes protective layer; 203 is the lamination of a kind of single-layer metals such as Ag, Cu, Au, Al, Fe, Ni, Cr, W, Mo, Ir, Zr, Ti or above metal, as structures such as Cu/Ni/Cu, Ag/Ni/Ag, Cu/Ti/Ni/Ag, Cu/Ni/Ti/Mo, Cu/Ni/Ti/Al/Ti/Ag.Thickness range 0.1 um～5 um on p face barrier layer 202, preferably, thickness is 0.5 um～1.5um; Thickness range 0.5 um～10 um of p face diluent zone 203, preferably, thickness is 2 um～4 um.
Fig. 6 has deposited the later generalized section of gluing layer 400 on substrate layer.Substrate layer comprises supporting substrate 300, substrate front side block protective layer 301, substrate front side dilution protective layer 302, substrate reverse side protective layer 303, base plate stress modulating layer 304 and substrate reverse side contact layer 305.Adopt the mode of electron beam evaporation; first in the front of supporting substrate 300, deposition substrate straight tackling protective layer 301, substrate front side are diluted protective layer 302 successively; then at the reverse side of supporting substrate 300 successively deposition substrate reverse side protective layer 303, base plate stress modulating layer 304 and substrate reverse side contact layer 305, finally on substrate front side dilution protective layer 302, deposit gluing layer 400.Gluing layer 400 can only be deposited on above substrate front side dilution protective layer 302, also can only be deposited on above p face dilution protective layer 203, also can be deposited on substrate front side dilution protective layer 302 and p face simultaneously and dilute above protective layer 203.Described supporting substrate 300 is any in silicon substrate, metal substrate, ceramic substrate or other composite base plates, and the supporting substrate 300 of the present embodiment is silicon substrate, and the thickness of supporting substrate 300 is between 60um～600um.Preferably, the thickness of supporting substrate 300 is between 100 um～200 um.Preferably, substrate front side block protective layer 301 adopts various metals or the metal alloys such as Cr, Ti, Pt, Au, W, and as the laminated construction of TiW etc., thickness is 0.5 um～1.5um.Preferably; substrate front side dilution protective layer 302 adopts the lamination of a kind of single-layer metals such as Ag, Cu, Au, Al, Fe, Ni, Cr, W, Mo, Ir, Zr, Ti or above metal; as structures such as Cu/Ni/Cu, Ag/Ni/Ag, Cu/Ti/Ni/Ag, Cu/Ni/Ti/Mo, Cu/Ni/Ti/Al/Ti/Ag, thickness is 3 um～4 um.Preferably, substrate reverse side protective layer 303 adopts the laminated construction of the various metals such as Cr, Ti, Pt, Au, W, and thickness is 0.3 um～1.0um.Preferably, base plate stress modulating layer 304 adopts the single-layer metals such as Ag, Cu, Au, Al, Ni, Ti, or the lamination of above metal, and as Cu/Ni/Cu, Ag/Ni/Ag, Cu/Ti/Ni/Ag, Cu/Ni/Ti/Al/Ti/Ag etc., thickness is 6 um～14 um.Preferably, substrate reverse side contact layer 305 adopts a kind of physicochemical properties such as Pt, Au, Ag stable and have two or more metal laminated or alloy A uSn, the AgSn etc. such as the single-layer metal of good heat conductive electric conducting material or Pt/Au/Pt/Au, and thickness is 0.1 um～2.5 um.Preferably, 400 alloys that adopt the low melting points such as Sn, Al, In, Bi, Pb, Zn, Sb, low-cost metal and form with the common metal such as Ag, Cu, Fe, Au, thickness is 0.5 um～5 um.
Fig. 7 is the generalized section after LED film and substrate layer bonding.The bonding of LED film and substrate layer is the mode that adopts wafer hot pressing to bind.The temperature and pressure that wafer hot pressing is binded and the material of gluing layer 400 will affect LED film and the bonding firmness of substrate layer; in addition; can regulate by controlling temperature and pressure that wafer hot pressing binds the stress state of epitaxial wafer, also can be by selecting the depositing temperature etc. of material category, p face ohmic contact metal layer 201, p face block protective layer 202 and the p face dilution protective layer 203 of gluing layer 400 to regulate the stress state of epitaxial wafer.The Sn of take is example as gluing layer 400 materials, and preferably, the temperature that wafer hot pressing is binded is at 230 ℃ ~ 280 ℃, and pressure is at 100Kg～600Kg.
Fig. 8 gets rid of former growth substrates generalized section afterwards.Growth substrates 000 in the present embodiment is silicon substrate, removes the method that silicon substrate adopts wet etching conventionally, and the method technology maturation, simple to operate, cost is low.When removing growth substrates 000, the convex wall 001 on it also can be removed, and has so far just realized by LED film the process to the film transfer of substrate layer by former growth substrate-transfer.As shown in Figure 8, after film transfer, LED film presents periodic array structure, fluted between each box-shaped film, and this groove correspondence the convex wall 001 in former growth substrates 000; In addition, can also see film turn after resilient coating 100 exposed, so just can improve by techniques such as surface coarsenings the light extraction efficiency of LED.
What the present embodiment adopted is box-shaped patterned substrate, and as mentioned above, the LED film main stor(e)y except resilient coating is only grown in foursquare growth platform.Due to edge effect, poor at the common crystal mass of the LED at square edge film, growth thickness is thicker, is required to be in addition follow-up scribing operation slot milling, therefore the edge of each square LED film need be removed, i.e. trimming.
Fig. 9 is the generalized section after chip trimming.Trimming can adopt the method for photoetching and wet etching to carry out, and also can be undertaken by the method for photoetching and dry etching.Conventionally one deck SiO first grows before trimming photoetching
2, the material such as SiN or metal is as mask layer, prepares figure subsequently by photoetching process, finally by the method for wet etching or dry etching, removes the skirt materials that need to remove.
Figure 10 is the generalized section after chip surface alligatoring.Roughened layer 500 adopts the method preparation of wet etching conventionally, and the Surface Texture of other form is processed, and such as photonic crystal etc., conventionally adopts the method for photoetching technique and dry etching to carry out.
Surface coarsening processing and trimming technique, regardless of the sequencing of processing, can first surface coarsening processing be carried out trimming technique again, also can first carry out the surface coarsening processing again of trimming technique.
Figure 11 is the generalized section after chip passivation.Passivation layer 600 adopts the method for physics or chemistry at chip surface, to prepare the dielectric materials such as SiO2, SiN, polyimides conventionally, passivation and protection chip surface and edge.
The sequencing of passivation, trimming and surface coarsening also can carry out like this: first trimming, carry out subsequently edge passivation, and then roughening treatment, finally can select whether to carry out surface passivation.
Figure 12 is the generalized section after the preparation of n electrode.N electrode 700 can adopt the method preparation of photoetching and wet etching, also can prepare by photoetching and the method for peeling off.Preferably, n electrode 700 better and with N-shaped semi-conducting material can form the metal material of better ohmic contact for electric conductivity, and as Pt, Au, Al, Ti, Cr, Ni, Cu, Ag etc., thickness is 1um～10 um.
Claims (10)
1. a light emitting diode chip with vertical cheaply, comprise: substrate layer, substrate layer is by substrate reverse side contact layer from bottom to up successively, base plate stress modulating layer, substrate reverse side protective layer, supporting substrate, substrate front side block protective layer and substrate front side dilution protective layer form, it is characterized in that: on substrate, be provided with successively gluing layer, p face protective layer, p face ohmic contact metal layer and epitaxial loayer, p face protective layer is by p face from bottom to up dilution protective layer and p face block protective layer form successively, epitaxial loayer is by p-type semiconductor layer from bottom to up successively, luminescence activity layer, N-shaped semiconductor layer and resilient coating form, n electrode is positioned on N-shaped semiconductor layer.
2. light emitting diode chip with vertical according to claim 1; it is characterized in that: the thickness of described gluing layer is 0.5um～5um; the thickness of described p face protective layer is 0.1 um～15um; the thickness of described substrate front side dilution protective layer is 0.5 um～10 um; the thickness of described substrate front side block protective layer is 0.2um～5um; the thickness of described supporting substrate is 60um～600um; the thickness of described base plate stress modulating layer is 1 um～20 um, and the thickness of described substrate reverse side contact layer is 0.1 um～5 um.
3. a preparation method for light emitting diode chip with vertical cheaply, is characterized in that:
A, first resilient coating, N-shaped semiconductor layer, luminescence activity layer and the p-type semiconductor layer of depositing successively in growth substrates, form epitaxial loayer;
B, on epitaxial loayer, deposit successively p face ohmic contact metal layer and carry out graphical treatment again, make itself and n electrode pad there is complementary structure;
C, deposit the p face protective layer being formed by p face block protective layer and p face dilution protective layer again;
D, then in the front of supporting substrate, deposit successively substrate front side block protective layer and substrate front side dilution protective layer;
E, deposition gluing layer;
F, at the reverse side of supporting substrate, deposit successively substrate reverse side protective layer, base plate stress modulating layer and substrate reverse side contact layer;
G, the mode that adopts wafer hot pressing to bind are bonded together epitaxial loayer and substrate by gluing layer;
H, removal growth substrates, finally, by figure texture layer, passivation layer, light antireflection layer and the n electrode of common method preparation increase bright dipping, obtain finished product.
4. preparation method according to claim 3, is characterized in that: the alloy material of described gluing layer for adopting Sn, Al, In, Pb, Bi, Sb, Zn low melting point, low-cost metal and forming with Ag, Cu, Au common metal.
5. preparation method according to claim 3; it is characterized in that: described p face dilution protective layer, substrate front side dilution protective layer, base plate stress modulating layer are Ag, Cu, Au, Al, Ni, Cr, W, Ti single-layer metal; or the lamination of above metal; as Cu/Ni/Cu, Ag/Ni/Ag, Cu/Ti/Ni/Ag, Cu/Ni/Ti/Mo, Cu/Ni/Ti/Al/Ti/A; or alloy, as TiW, FeNiCr, FeCoCr form.
6. preparation method according to claim 3, is characterized in that: described p face block protective layer, substrate front side block protective layer, substrate reverse side protective layer form by the lamination of various metals: Cr, Ti, Pt, Au, Ni, W, Cu or metal alloy: TiW, FeNiCr, FeCoCr.
7. preparation method according to claim 3, is characterized in that: the material of described supporting substrate is Si, Ge, GaAs, GaP, Cu (W), Mo, C, SiO
2or a kind of in the composite base plate of above material.
8. preparation method according to claim 3, is characterized in that: the pressure that described wafer hot pressing is binded is 100kg～1000Kg.
9. preparation method according to claim 3, is characterized in that: the temperature that described wafer hot pressing is binded is 150 ℃～400 ℃.
10. preparation method according to claim 3, is characterized in that: described growth substrates is any one in Sapphire Substrate, silicon carbide substrates, silicon substrate, GaN substrate or AlN substrate.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104347762A (en) * | 2014-09-22 | 2015-02-11 | 南昌大学 | Preparation method of LED (Light-Emitting Diode) film chip with meltback layer and structure |
| CN104362224A (en) * | 2014-09-22 | 2015-02-18 | 南昌大学 | Method for manufacturing substrate of LED thin film chip and structure of substrate |
| CN104795472A (en) * | 2015-03-23 | 2015-07-22 | 易美芯光（北京）科技有限公司 | Preparation method for semiconductor light-emitting device |
| CN105514229A (en) * | 2016-01-26 | 2016-04-20 | 河源市众拓光电科技有限公司 | Making method of wafer level LED vertical chip |
| CN105702824A (en) * | 2016-01-26 | 2016-06-22 | 河源市众拓光电科技有限公司 | A method for manufacturing an LED vertical chip through adoption of a wafer-level Si patterned substrate |
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| CN108767083A (en) * | 2018-05-30 | 2018-11-06 | 河源市众拓光电科技有限公司 | A kind of adjustable light emitting diode (LED) chip with vertical structure of stress and preparation method thereof |
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| CN109103747A (en) * | 2017-06-20 | 2018-12-28 | 稳懋半导体股份有限公司 | To reduce the structure-improved of compound semiconductor wafer deformation |
| CN109103163A (en) * | 2017-06-20 | 2018-12-28 | 稳懋半导体股份有限公司 | To reduce the structure-improved of compound semiconductor wafer deformation |
| CN110571318A (en) * | 2019-08-29 | 2019-12-13 | 天津三安光电有限公司 | Flip-chip light emitting element |
| CN113161868A (en) * | 2021-04-12 | 2021-07-23 | 武汉仟目激光有限公司 | Wafer and manufacturing method thereof |
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| CN104347762B (en) * | 2014-09-22 | 2017-03-22 | 南昌大学 | Preparation method of LED (Light-Emitting Diode) film chip with meltback layer and structure |
| CN104362224A (en) * | 2014-09-22 | 2015-02-18 | 南昌大学 | Method for manufacturing substrate of LED thin film chip and structure of substrate |
| CN104347762A (en) * | 2014-09-22 | 2015-02-11 | 南昌大学 | Preparation method of LED (Light-Emitting Diode) film chip with meltback layer and structure |
| CN104362224B (en) * | 2014-09-22 | 2017-01-18 | 南昌大学 | Method for manufacturing substrate of LED thin film chip and structure of substrate |
| CN104795472A (en) * | 2015-03-23 | 2015-07-22 | 易美芯光（北京）科技有限公司 | Preparation method for semiconductor light-emitting device |
| CN104795472B (en) * | 2015-03-23 | 2017-11-07 | 易美芯光（北京）科技有限公司 | A kind of preparation method of light emitting semiconductor device |
| CN108463776A (en) * | 2015-11-18 | 2018-08-28 | 惠普打印机韩国有限公司 | Imaging device and including light-emitting component in an imaging device |
| CN105702824A (en) * | 2016-01-26 | 2016-06-22 | 河源市众拓光电科技有限公司 | A method for manufacturing an LED vertical chip through adoption of a wafer-level Si patterned substrate |
| CN105702824B (en) * | 2016-01-26 | 2018-07-24 | 河源市众拓光电科技有限公司 | A method of LED vertical chip is made using wafer scale Si graph substrates |
| CN105514229A (en) * | 2016-01-26 | 2016-04-20 | 河源市众拓光电科技有限公司 | Making method of wafer level LED vertical chip |
| CN105762263A (en) * | 2016-04-01 | 2016-07-13 | 陕西新光源科技有限责任公司 | Method for preparing bonding substrate for LED chip |
| CN109103747A (en) * | 2017-06-20 | 2018-12-28 | 稳懋半导体股份有限公司 | To reduce the structure-improved of compound semiconductor wafer deformation |
| CN109103163A (en) * | 2017-06-20 | 2018-12-28 | 稳懋半导体股份有限公司 | To reduce the structure-improved of compound semiconductor wafer deformation |
| CN108767083A (en) * | 2018-05-30 | 2018-11-06 | 河源市众拓光电科技有限公司 | A kind of adjustable light emitting diode (LED) chip with vertical structure of stress and preparation method thereof |
| CN108933187A (en) * | 2018-08-22 | 2018-12-04 | 南昌大学 | A kind of light-emitting surface is the LED chip and preparation method thereof of specific plane geometric figure |
| CN108933187B (en) * | 2018-08-22 | 2024-02-09 | 南昌大学 | LED chip with luminous surface in specific plane geometric figure and preparation method thereof |
| CN110571318A (en) * | 2019-08-29 | 2019-12-13 | 天津三安光电有限公司 | Flip-chip light emitting element |
| CN113161868A (en) * | 2021-04-12 | 2021-07-23 | 武汉仟目激光有限公司 | Wafer and manufacturing method thereof |
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Address after: Annex building 2, engineering technology research center, No. 679, aixihu North Road, Nanchang high tech Industrial Development Zone, Nanchang City, Jiangxi Province Co-patentee after: Nanchang University Patentee after: NANCHANG GUIJI SEMICONDUCTOR TECHNOLOGY Co.,Ltd. Address before: 330047 No. seven, No. 192, hi tech Zone, Nanchang hi tech Zone, Jiangxi Co-patentee before: Nanchang University Patentee before: NANCHANG HUANGLYU LIGHTING Co.,Ltd. |