CN108933187A - A kind of light-emitting surface is the LED chip and preparation method thereof of specific plane geometric figure - Google Patents
A kind of light-emitting surface is the LED chip and preparation method thereof of specific plane geometric figure Download PDFInfo
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- CN108933187A CN108933187A CN201810947645.4A CN201810947645A CN108933187A CN 108933187 A CN108933187 A CN 108933187A CN 201810947645 A CN201810947645 A CN 201810947645A CN 108933187 A CN108933187 A CN 108933187A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 463
- 239000000758 substrate Substances 0.000 claims abstract description 113
- 239000002184 metal Substances 0.000 claims abstract description 72
- 229910052751 metal Inorganic materials 0.000 claims abstract description 72
- 238000002161 passivation Methods 0.000 claims abstract description 71
- 239000011241 protective layer Substances 0.000 claims abstract description 66
- 150000002739 metals Chemical class 0.000 claims abstract description 53
- 230000000295 complement effect Effects 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims description 34
- 239000010931 gold Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 29
- 229910052709 silver Inorganic materials 0.000 claims description 20
- 229910052737 gold Inorganic materials 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052804 chromium Inorganic materials 0.000 claims description 14
- 229910052719 titanium Inorganic materials 0.000 claims description 11
- 238000010276 construction Methods 0.000 claims description 10
- 238000001459 lithography Methods 0.000 claims description 10
- 238000002310 reflectometry Methods 0.000 claims description 10
- 229910052697 platinum Inorganic materials 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 239000002356 single layer Substances 0.000 claims description 8
- 230000007797 corrosion Effects 0.000 claims description 7
- 238000005260 corrosion Methods 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 230000001458 anti-acid effect Effects 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 6
- 230000003760 hair shine Effects 0.000 claims description 6
- 230000026267 regulation of growth Effects 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 239000003518 caustics Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 4
- UBMXAAKAFOKSPA-UHFFFAOYSA-N [N].[O].[Si] Chemical compound [N].[O].[Si] UBMXAAKAFOKSPA-UHFFFAOYSA-N 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 239000002648 laminated material Substances 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 3
- 229910052703 rhodium Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000003513 alkali Substances 0.000 claims 1
- 239000002585 base Substances 0.000 claims 1
- 230000003628 erosive effect Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 238000005538 encapsulation Methods 0.000 abstract description 7
- 238000010923 batch production Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 241001465382 Physalis alkekengi Species 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 229910017750 AgSn Inorganic materials 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000003447 ipsilateral effect Effects 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- 229910000599 Cr alloy Inorganic materials 0.000 description 1
- 238000000018 DNA microarray Methods 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910001260 Pt alloy Inorganic materials 0.000 description 1
- UIIMBOGNXHQVGW-UHFFFAOYSA-M Sodium bicarbonate Chemical compound [Na+].OC([O-])=O UIIMBOGNXHQVGW-UHFFFAOYSA-M 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000004038 photonic crystal Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 102220062245 rs1800369 Human genes 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/405—Reflective materials
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention discloses the LED chip that a kind of light-emitting surface is specific plane geometric figure, the LED chip includes substrate layer, and substrate layer successively includes contact layer, substrate back side protective layer, supporting substrate, substrate front side protective layer, bonded layer from bottom to up；The upper surface of substrate layer is successively arranged bonding protective layer, reflective metals contact layer from bottom to up, is equipped with graphical epitaxial layer in the upper surface of reflective metals contact layer；Graphical epitaxial layer successively includes: complementary structure layer, p-type layer, luminescent layer, n-layer from bottom to up；The first passivation layer, N electrode and the second passivation layer are equipped on graphical epitaxial layer；The graphical epitaxial layer shape is specific plane geometric figure.The invention also provides the LED core piece preparation methods that a kind of light-emitting surface is specific plane geometric figure.The present invention can save the design and manufacture link at LED encapsulation manufacture end and the cost of batch production, and not increase LED chip manufacturing cost.
Description
Technical field
The present invention relates to light emitting semiconductor devices and preparation method thereof, are that specific plane is several more particularly, to a kind of light-emitting surface
The LED chip and preparation method thereof of what figure.
Background technique
Light emitting diode (LED) is developed so far, and is used widely in various lighting areas, and gradually moves towards intelligent
And diversified development.In recent years, the light quality of LED illumination is suggested higher requirement, especially in portable lighting, entertainment lighting etc.
Field, there are diversified demands for LED chip luminous pattern.For example, having spy in standard circular, entertainment lighting in portable lighting
Different shape or the luminous pattern comprising various texts etc..Currently, obtain the luminous patterns of the above particular demands usually in encapsulation or
Be designed in lamps and lanterns manufacturing process, due to the luminous patterns of most LED chips be it is rectangular, this is particular demands luminous pattern
Design is made troubles, and increases the cost of encapsulation and lamps and lanterns manufacture, it is often more important that is irradiated by encapsulation or Design of Luminaires
Particular demands luminous pattern quality it is not high, uniformity is poor.If LED chip can directly irradiate required illuminated diagram
Shape avoids carrying out Secondary Design in encapsulation and lamps and lanterns manufacturing process, can not only reduce cost, and can be improved illuminated diagram
The quality of shape, the demand of LED will be improved in specific lighting area, and the application field of LED is expanded.
According to chip structure, LED chip can be divided into three categories, and be LED chip, the upside-down mounting of traditional positive assembling structure respectively
The LED chip of structure and the LED chip of vertical structure.Traditional packed LED chip, P electrode and N electrode are in LED film
Ipsilateral and be located at light-emitting surface, light is emitted through transparent substrates from surrounding, and front is added to go out light altogether for five faces, in this way, light is spatially out
Be unevenly distributed, electrode is light-blocking, and be located at light-emitting surface, cause the light intensity of normal orientation weaker, rely primarily on side and go out light.
The LED chip of inverted structure, light-emitting surface are the back side (therefore relatively positive assembling structure, be referred to as upside-down mounting), P electrode and N electrode still position
In ipsilateral and be directly connected with substrate (heat sink), it is light-blocking and be located at light-emitting surface and lead to normal luminous intensity to avoid electrode in positive assembling structure
Weak disadvantage, but be similarly five faces and go out light, the light of sending need to be all emitted through substrate, and the distribution of light spatially is not still out
Uniformly.At least there are five light-emitting surface, light is unevenly distributed the chip of positive assembling structure and inverted structure space multistory angle, is needed
The light-emitting surface of nearly lambertian distribution could be obtained by increasing diffusion barrier and lens in encapsulation process.The LED chip of vertical structure is thin
Membrane DNA chip needs to remove LED film from growth substrates and be transferred on the substrate with preferable conductive and heat-conductive ability, core
The P electrode and N electrode of piece are located at film two sides, therefore referred to as vertical structure.The thin film chip of vertical structure only has front to go out light
(single direction), distribution of the light at space multistory angle out is in nearly Lambertian pattern, is shone uniform.
In conclusion having the characteristics that there is the LED chip of vertical structure single side to go out light, if by designing energy in die terminals
The structure for enough irradiating various shape luminous pattern, the luminous pattern irradiated have higher quality and can save LED envelope
The design and manufacture link at dress manufacture end and the cost of batch production, and do not increase the cost of LED chip manufacture.For example,
The shape of LED chip remain as it is rectangular, can by design LED chip in each functional layer structure, light-emitting surface be designed to justify
The shapes such as shape, sector, circular ring shape, five-pointed star or light-emitting surface include other specific characters etc., such chip, specific
Relatively broad application prospect will be had by the segmenting market.
Some LED core piece preparation methods in the prior art and structure, are set by the shape of complementation electrode layer and N electrode
Meter realizes the plane geometric figure of LED chip irradiation particular design in conjunction with metallic reflection rate difference.But it can not completely cut off completely
Electric current makes it be not particularly suited for the occasion high to power conservation requirement in the injection of non-luminous region so that power consumption increases,
Working time when shortening using battery driving.
Summary of the invention
To overcome defect in the prior art, the invention proposes the LED that a kind of light-emitting surface is specific plane geometric figure
Chip, the LED chip include substrate layer, and substrate layer successively includes contact layer, substrate back side protective layer, branch support group from bottom to up
Plate, substrate front side protective layer, bonded layer；The upper surface of substrate layer is successively arranged bonding protective layer, reflective metals contact from bottom to up
Layer is equipped with graphical epitaxial layer in the upper surface of reflective metals contact layer；Graphical epitaxial layer and reflective metals contact layer have phase
Same shape；
Graphical epitaxial layer successively includes: complementary structure layer, p-type layer, luminescent layer, n-layer from bottom to up；Graphical outer
Prolong and is equipped with the first passivation layer, N electrode and the second passivation layer above layer；
The graphical epitaxial layer shape is specific plane geometric figure, and the light-emitting surface is patterned epitaxial layer,
The first passivation layer is equipped with above graphical epitaxial layer, the first passivation layer is equipped with N electrode, and entire chip surface is equipped with the second passivation
Layer；
The first passivation layer at light-emitting surface is identical with N electrode shape, and shape forms complementary with graphical epitaxial layer shape；
It is complementary structure layer that N electrode, which projects INFERIOR GRAPH epitaxial layer corresponding region,.
Wherein, reflective metals contact layer and graphical epitaxial layer form lower ohmic contact resistance, and have high reflection
Rate, corresponding graphical epitaxial layer light emission luminance is high at reflective metals contact layer, and corresponding figure at complementary structure layer region
It is low to change epitaxial layer light emission luminance, while graphical epi region is overseas does not shine.
Wherein, the graphical epitaxial layer is the plane geometric figure knot of circle, sector, circular ring shape, Pentagram shape
It include various text shapes in structure, or the graphic structure of graphical epitaxial layer.
Wherein, the first passivation material is one of silica, silicon nitride, nitrogen-oxygen-silicon, polyimides, makes p-type layer and n
Type layer is realized in edge to insulate.
Wherein, complementary structure layer is dielectric film；Or to form the metal of high contact resistance with graphical epitaxial layer
Layer；Or the graphical epi-layer surface to pass through plasma surface treatment, being destroyed, between reflective metals contact layer
Ohmic contact resistance becomes larger；Or to etch away the graphical epitaxial layer of current extending by etching technics, make its current expansion
It is less able.
Wherein, the material of the reflective metals contact layer and graphical epitaxial layer form lower ohmic contact resistance, and
Metal single layer with high reflectivity or laminated construction with high reflectivity；The material of the reflective metals contact layer be Ag,
One of A1, Pt, Rh, Ni/Ag, Ag/Ni/Ag, Ni/A1 or Ni/Ag/Ni/Ag.
Wherein, the contact resistance between the material and graphical epitaxial layer of the bonding protective layer is very high, and has low
The metal single layer with antiacid caustic corrosion ability of reflectivity；Or bonding protective layer be laminated construction, and in laminated construction with figure
First layer material of shape epitaxial layer contact is difficult to formed low ohm contact resistance, and has antiradar reflectivity, laminated material
With antiacid caustic corrosion ability；The metal single layer material of the bonding protective layer is one of Cr, Pt, Ti, W or Au；Or
The material of the laminated construction of the bonding protective layer is Cr/Pt/Au, Cr/Pt/Ag, Cr/Pt/Ag/Cu/Ag, Cr/Pt/Cr/
One of Pt/Au/Ag, Ti/Pt/Au or Ti/W/Ti/Pt/Au.
Wherein, first passivation layer thickness be 0.1 μm~10 μm, the bonded layer with a thickness of 1 μm~10 μm,
The described bonding protective layer with a thickness of 0.1 μm~10 μm, the reflective metals contact layer is with a thickness of 0.05 μm~1 μm, institute
The substrate front side protective layer stated with a thickness of 0.5 μm~10 μm, the substrate back side protective layer with a thickness of 0.5 μm~10 μ
m；The substrate layer with a thickness of 60 μm~600 μm, the contact layer with a thickness of 0.1 μm~10 μm.
The present invention also proposes that a kind of light-emitting surface is the LED core piece preparation method of specific plane geometric figure, which is characterized in that
The described method includes:
Step 1: provide substrate, over the substrate formed LED epitaxial layer, the epitaxial layer include buffer layer, n-layer,
Luminescent layer and p-type layer；
Step 2: complementary structure layer, reflective metals contact layer, bonding protective layer are sequentially formed on the epitaxial layer；
Step 3: supporting substrate is provided, sequentially forms substrate front side protective layer, bonded layer in the front of the supporting substrate,
Substrate back side protective layer, contact layer are sequentially formed in the reverse side of the supporting substrate；
Step 4: using wafer thermocompression bonding method, by bonded layer and bond protective layer for the epitaxial layer and substrate layer
It binds together；
Step 5: removing the substrate, buffer layer, obtain the epitaxial layer of vertical structure, be followed successively by n-layer, hair from top to bottom
Photosphere and p-type layer；
Step 6: preparing roughened layer on the n-layer surface；
Step 7: removal specific region epitaxial layer, the graphical epitaxial layer structure remained are specific plane geometric graph
Shape；
Step 8: preparing the first passivation layer in chip surface and make the first passivation layer pattern by lithography, it is blunt to obtain graphical first
Change layer；
Step 9: preparing N electrode in the first passivation layer surface and graphical epitaxial layer portion region surface；
Step 10: two passivation layer of growth regulation simultaneously makes the second passivation layer pattern by lithography, obtains graphical second passivation layer, obtains
Light-emitting surface is the LED chip of particular geometric figure.
Wherein, in the step 7, the graphical epitaxial layer remained is circle, sector, circular ring shape, pentalpha
Comprising various text shapes in the plane geometric figure structure of shape, or the graphic structure of graphical epitaxial layer that remains.For
Obtain the LED chip that light-emitting surface is specific plane geometric figure, the shape that the present invention passes through epitaxial layer, reflective metals contact layers
Design realizes the reflection gold for having high reflectance and capable of forming Ohmic contact with LED epitaxial layer by patterned epitaxial layer
Belong to chip area corresponding to contact layer to shine, no epitaxial layer region does not shine, so that obtaining LED chip light-emitting surface is specific set
The plane geometric figure of meter, plane geometric figure can be specific figure, or specific " word " type.
The present invention realizes that chip light emitting face is specific plane geometric figure, chip light emitting face by graphical epitaxial structure layer
With higher quality and the design and manufacture link at LED encapsulation manufacture end and the cost of batch production can be saved, and is not increased
Add LED chip manufacturing cost.Meanwhile removing light emitting region epitaxial layer, isolation electric current is reduced in the injection of non-luminous region
Power consumption increases working time when driving using battery suitable for the occasion high to power conservation requirement.
Detailed description of the invention
Fig. 1 is the diagrammatic cross-section of epitaxial layer of the present invention and substrat structure；
After Fig. 2 forms complementary structure layer for using plasma lithographic method on epitaxial layer of the invention, it is sequentially depositing anti-
It penetrates metal contact layer and bonds the diagrammatic cross-section after protective layer；
Fig. 3 is the structural profile illustration of substrate layer of the invention；
Fig. 4 is after the bonding protective layer of the invention that will be formed on epitaxial layer is bound together with bonded layer on substrate layer
Structural profile illustration；
Fig. 5 is the structural schematic diagram of removal substrate and buffer layer of the invention；
Fig. 6 is of the invention by the structural profile illustration of the LED chip formed after n-layer roughing in surface；
Fig. 7 is the structural profile illustration of the LED chip of the invention graphically formed later by epitaxial layer；
Fig. 8 is one passivation layer of growth regulation of the invention and makes the LED chip formed after the first passivation layer pattern by lithography
Structural profile illustration；
Fig. 9 is the structural profile illustration of the LED chip formed after prepared by N electrode of the invention；
Figure 10 is of the invention for the second passivation layer of growth and to make the LED chip formed after the second passivation layer pattern by lithography
Structural profile illustration；
Figure 11 is the top view for the LED chip that a kind of light-emitting surface of the invention is circular shape；
Figure 12 is the top view for the LED chip that another light-emitting surface of the invention is fan shape；
Figure 13 is the top view for the LED chip that another light-emitting surface of the invention is Pentagram shape；
Figure 14 is the top view for the LED chip that another light-emitting surface of the invention is annulus shape；
Figure 15 is the top view for the LED chip that another light-emitting surface of the invention is " NCU " printed words.
Wherein, 000: graphical epitaxial layer；100: epitaxial layer；101: substrate；102: buffer layer；103:n type layer；104: hair
Photosphere；105:p type layer；200: substrate layer；201: supporting substrate；202: substrate front side protective layer；203: bonded layer；204: substrate
Reverse side protective layer；205: contact layer；301: complementary structure layer；302: reflective metals contact layer；303: bonding protective layer；401: thick
Change layer；501: the first passivation layers；601:N electrode；701: the second passivation layers.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
Member's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
It is the LED core of particular geometric figure to a kind of light-emitting surface proposed by the present invention below in conjunction with the drawings and specific embodiments
Structure of piece and preparation method thereof is described in detail.It should be noted that attached drawing of the invention is all made of the non-essence simplified very much
Quasi- ratio, only to convenient, the apparent aid illustration present invention.
Fig. 1 is the diagrammatic cross-section of epitaxial layer and substrat structure of the invention.As shown in Figure 1, the substrate 101 can be
Any in Sapphire Substrate, silicon substrate, silicon carbide substrates and existing gallium nitride based LED technical field in film growth substrates
Kind.In an embodiment of the present invention, substrate 101 is silicon substrate.GaN base LED epitaxial layer is using Organometallic Chemistry gas
Mutually the method for deposition obtains, and since substrate 101, the epitaxial layer at least successively includes buffer layer 102, n-layer 103, hair
Photosphere 104, p-type layer 105.
Fig. 2 is the present invention after preparing complementary structure layer 301, and reflective metals contact layer 302 is sequentially depositing on epitaxial layer
And the diagrammatic cross-section after bonding protective layer 303.The preparation method of complementary structure layer 301 is using plasma etching,
The surface of p-type layer 105 is destroyed, complementary structure layer 301 makes p-type layer 105 and reflective metals contact layer on the surface of p-type layer 105
Ohmic contact between 302 is deteriorated, thus reach LED epitaxial layer in the operating condition, the corresponding luminescent layer of complementary structure 301
104 positions it is luminous very weak.Complementary structure layer 301 is patterned structures layer, and shape and specific plane geometry are formed mutually
It mends.Reflective metals contact layer 302 is patterned structures layer, and shape is identical as specific plane geometry.
It the material requirements of reflective metals contact layer 302 reflectivity with higher and can be formed with 105 material of p-type layer
Preferable Ohmic contact.Reflective metals contact layer 302 can be the metal laminated of Ni and Ag, is also possible to pure Ag, can also be
The alloy of specific combination in the metals such as Ag, Pt, Ni, Al, Ti, Pd, Rh.The preparation method of reflective metals contact layer 302 is usually
Physical vapour deposition (PVD), such as electron beam evaporation, sputtering.Reflective metals contact layer 302 with a thickness of 0.05 μm~1 μm.Preferably,
The material of reflective metals contact layer 302 is Ag in the present embodiment, with a thickness of 0.1 μm~0.5 μm.
The material for bonding protective layer 303 is the metal single layer with antiacid caustic corrosion ability, such as Cr, Pt, Ti, W；Or bonding
Protective layer 303 is laminated construction, and the first layer material of laminated construction is difficult to form low ohm contact resistance with p-type layer 105, and
Metal with antiradar reflectivity, laminated material have antiacid caustic corrosion ability, such as Cr/Pt/Au, Cr/Pt/Ag, Cr/Pt/Cr/
Pt/Au/Ag, Ti/Pt/Au, Ti/W/Pt/Au.Another effect for bonding protective layer 303 is to be bundled in substrate layer 200
Together, it is desirable that the last layer material of bonding protective layer 303 has preferable metal wellability.Bond the thickness of protective layer 303
It is 0.1 μm~10 μm.Preferably, in one embodiment of the invention, bonding protective layer 303 using Cr/Pt/Cr/Pt.../
Au/Ag.Preferably, bond protective layer 303 with a thickness of 0.5 μm~10 μm, Cr/Pt period lamination with a thickness of 0.3 μm~1 μ
M, Au/Ag with a thickness of 0.2 μm~5 μm.
Fig. 3 is to deposited the later diagrammatic cross-section of bonded layer 203 on the substrate layer.Substrate layer include supporting substrate 201,
Substrate front side protective layer 202, bonded layer 203, substrate back side protective layer 204 and contact layer 205, the substrate front side protective layer
202, successively on the front of supporting substrate 201, the substrate back side protective layer 204 and contact layer 205 successively exist bonded layer 203
On the reverse side of supporting substrate 201.First in the positive deposition substrate front protecting layer 202 of supporting substrate 201, then in branch support group
The reverse side of plate 201 is sequentially depositing substrate back side protective layer 204 and contact layer 205, finally sinks on substrate front side protective layer 202
Product bonded layer 203.Bonded layer 203 can be only deposited on above substrate front side protective layer 202, can also only be deposited on bonding protection
Above layer 303, it can also be deposited on simultaneously above substrate front side protective layer 202 and bonding protective layer 303.Substrate front side protective layer
202 with a thickness of 0.5 μm~10 μm, substrate back side protective layer 204 with a thickness of 0.5 μm~10 μm；Substrate layer 200 with a thickness of
60 μm~600 μm.Preferably, bonded layer 203 is only deposited on above substrate front side protective layer 202 in the present embodiment.The branch
Support group plate 201 is any one of Si, Ge, GaAs, AlN, Al2O3, GaP, Cu (W), Mo, C, SiO2 or other composite substrates,
The supporting substrate 201 of the present embodiment is silicon substrate, supporting substrate 201 with a thickness of between 60 μm~600 μm.Preferably, it supports
Substrate 201 with a thickness of between 80 μm~200 μm.Preferably, substrate front side protective layer 202 and substrate back side protective layer 204 are adopted
With the various metals such as Cr, Pt, Au, W or metal alloy, such as the laminated construction of TiW, such as Cr/Pt/Cr/Au, Cr/Pt/Au, Pt/
Au/Pt/Au, Cr/Pt/TiW.With a thickness of 0.5 μm~1.5 μm.The contact layer 205 is a kind of physico using Pt, Au, Cu etc.
Learn two or more metal laminated such as the stable and single-layer metal with good heat conductive conductive material of property or Pt/Au/Pt/Au or
Alloy AuSn, AgSn etc., with a thickness of 0.1 μm~10 μm.Material used in the bonded layer 203 have lower fusing point or
With stronger diffusivity, bonded layer 203 with a thickness of 1 μm~10 μm；Preferably, the material of the bonded layer 203 is
Sn, In, Pb, Bi, Sb, Zn low-melting-point metal or its alloy (such as AuSn, AuIn, AgIn, AgSn) formed with Ag, Cu, Au, A1
In specific one kind, structure is the lamination that a kind of metal single layer or various metals are constituted, such as Au/AuSn, Ag/Sn, Ag/
In,Au/Au.Preferably, bonded layer 203 with a thickness of 0.5 μm~5 μm.
Fig. 4 is the diagrammatic cross-section after epitaxial layer of the invention is bonded with substrate layer.Epitaxial layer is bonded with substrate layer
It is by bonded layer 203 and to bond protective layer 303 for the LED epitaxial layer 100 and substrate by the way of wafer thermocompression bonding
Layer 200 is bound together.The temperature and pressure of wafer thermocompression bonding and the material of bonded layer 203 will will affect LED epitaxial layer
100 firmness bonded with substrate layer 200.For using Sn as 203 material of bonded layer, it is preferable that 2 inch wafer thermocompression bondings
Temperature at 230 DEG C~280 DEG C, pressure is in 100Kg~1000Kg.
The structural schematic diagram of removal substrate and buffer layer Fig. 5 of the invention.Substrate 101 in the present embodiment is silicon substrate,
The removal silicon substrate method that generallys use wet etching, it is the method technology maturation, easy to operate, at low cost.So far it is achieved that
LED epitaxial layer 100 is transferred to the process of the epitaxial layer transfer of substrate layer 200 by former substrate 101.
As shown in fig. 6, n-layer 103 is exposed after epitaxial layer transfer, can thus be improved by techniques such as roughing in surface
The light extraction efficiency of LED.Fig. 6 is that the structural profile of the invention by the LED chip formed after 103 roughing in surface of n-layer shows
It is intended to.The method that roughened layer 401 generallys use wet etching is prepared on 103 surface of n-layer, at the surface of other form
Reason, such as photonic crystal etc., the method for generalling use photoetching technique and dry etching carry out.In the present embodiment, roughing in surface is adopted
It is obtained with thermokalite wet corrosion technique.
Fig. 7 is the structural profile illustration of the LED chip of the invention graphically formed later by epitaxial layer, can be adopted
It is carried out, can also be carried out by the method for photoetching and dry etching with the method for photoetching and wet etching.Before epitaxial layer removal
The materials such as one layer of silica, silicon nitride are usually first grown as mask layer, and figure is then prepared by photoetching process, finally by
The epitaxial film materials that the removal of the method for wet etching or dry etching needs to remove.The removal of the present embodiment epitaxial layers uses hot phosphorus
Sour wet corrosion technique obtains.Graphical 000 shape of epitaxial layer is specific plane geometric figure.
Fig. 8 is one passivation layer of growth regulation of the invention and makes the LED chip formed after the first passivation layer pattern by lithography
Structural profile illustration, 501 material of the first passivation layer are the insulation films media such as silica, silicon nitride, nitrogen-oxygen-silicon, polyimides
One of material realizes p-type layer 105 and n-layer 103 in edge and insulate.The setting of first passivation layer 501 is graphical outer
Prolong on layer 000.It is covered on graphical 000 upper surface of epitaxial layer and side, and bonding 303 upper surface of protective layer, the first passivation
Layer 501 with a thickness of 0.1 μm~10 μm.Preparation method is chemical vapor deposition, physical vapour deposition (PVD), atomic layer deposition or molten
One of the methods of glue gel.In the present embodiment, the method preparation SiO2 that using plasma enhances chemical vapor deposition makees
For 501 material of the first passivation layer.
Fig. 9 is the structural profile illustration of LED chip formed after N electrode preparation, N electrode 601 can using photoetching and
Prepared by the method for wet etching, can also be prepared by the method for photoetching and removing.N electrode 601 is arranged in the first passivation layer 501
000 partial region surface of surface and graphical epitaxial layer.The N electrode 601 be electric conductivity preferably and can with n-layer material
The metal material of preferable Ohmic contact, such as Pt, Au, Al, Ti, Cr, Ni, Cu, Ag are formed, with a thickness of 1 μm~10 μm.It is preferred that
Ground, N electrode Cr/Pt/Au, Al/Ti/Au, Al/Ni/Ti/Au.
Figure 10 is two passivation layer of growth regulation of the present invention and the knot for making the LED chip formed after the second passivation layer pattern by lithography
Structure diagrammatic cross-section, 701 material of the second passivation layer are the insulation films medium materials such as silica, silicon nitride, nitrogen-oxygen-silicon, polyimides
One of material plays the role of passivation and protection chip surface and edge.Second passivation layer 701 is arranged in entire chip table
On all areas in addition to welding disking area.Preparation method is chemical vapor deposition, physical vapour deposition (PVD), atomic layer deposition or molten
One of the methods of glue gel.In the present embodiment, the method preparation SiO2 that using plasma enhances chemical vapor deposition makees
For 502 material of the second passivation layer.
Specifically, a kind of light-emitting surface is the LED chip of specific plane geometric figure, as shown in Figure 10, including substrate layer
200, substrate layer 200 sequentially consists of contact layer 205, substrate back side protective layer 204, supporting substrate 201, substrate front side and protects
Sheath 202, bonded layer 203, the upper surface of substrate layer 200 are successively arranged bonding protective layer 303, reflective metals contact layer from bottom to up
302, it is equipped with graphical epitaxial layer 000 in the upper surface of reflective metals contact layer 302, graphical epitaxial layer 000 is successively from bottom to up
For complementary structure layer 301, p-type layer 105, luminescent layer 104, n-layer 103, the first passivation is equipped on graphical epitaxial layer 000
Layer 501, N electrode 601 and the second passivation layer 701,000 shape of graphical epitaxial layer are specific plane geometric figure, figure
Shape epitaxial layer 000 is equipped with the first passivation layer 501 above, and the first passivation layer 501 is equipped with N electrode 601, and entire chip surface is set
There is the second passivation layer 701；Graphical epitaxial layer 000 and reflective metals contact layer 302 are of similar shape.At light-emitting surface
One passivation layer 501 is identical with 601 shape of N electrode, shape formed with graphical 000 shape of epitaxial layer it is complementary, other than light-emitting surface
N electrode figure can be with particular design, while it is complementation that N electrode 601, which projects 000 corresponding region of INFERIOR GRAPH epitaxial layer,
Structure sheaf 301；Reflective metals contact layer 302 and graphical epitaxial layer form lower ohmic contact resistance, and have high reflection
Rate, corresponding graphical 000 light emission luminance of epitaxial layer is high at reflective metals contact layer 302, and at complementary structure layer region 301 pair
000 light emission luminance of graphical epitaxial layer answered is low, while not shining outside graphical 000 region of epitaxial layer.Therefore, chip light emitting face
Shape is special pattern identical with graphical 000 shape of epitaxial layer.
Figure 11 is the top view for the LED chip that light-emitting surface of the invention is circular shape；Graphical epitaxial layer 000 and reflection
The circular shape having the same of metal contact layer 302.The first passivation layer 501 at light-emitting surface is identical with 601 shape of N electrode,
Shape forms complementary with graphical 000 shape of epitaxial layer, and N electrode figure other than light-emitting surface can be with particular design, while N
It is complementary structure layer 301 that electrode 601, which projects 000 corresponding region of INFERIOR GRAPH epitaxial layer, is corresponded at reflective metals contact layer 302
Graphical epitaxial layer 000 shine, and corresponding graphical epitaxial layer 000 shines weak at complementary structure layer region 301, schemes simultaneously
Shape epitaxial layer does not shine outside 000 region.Therefore, chip light emitting face shape illustrated in Figure 11 is a standard circular.Wherein
The logical relation of characteristic size d are as follows: d1=d2=d3 < d4 < d5, wherein d1, d2, d3, d4, d5 respectively represent complementary structure
The diameter of layer, reflective metals contact layer, N electrode, the first passivation layer, luminescent layer.
Figure 12 is the top view for the LED chip that a kind of light-emitting surface of the invention is fan shape；000 He of graphical epitaxial layer
The fan shape having the same of reflective metals contact layer 302.601 shape phase of the first passivation layer 501 and N electrode at light-emitting surface
Together, shape is formed complementary with graphical 000 shape of epitaxial layer, the N electrode figure other than light-emitting surface can with particular design,
It is complementary structure layer 301, reflective metals contact layer 302 that N electrode 601, which projects 000 corresponding region of INFERIOR GRAPH epitaxial layer, simultaneously
Locate corresponding graphical epitaxial layer 000 shine, and at complementary structure layer region 301 corresponding graphical epitaxial layer 000 shine it is weak,
It does not shine outside graphical 000 region of epitaxial layer simultaneously.Therefore, chip light emitting face shape illustrated in Figure 12 is a standard fan
Shape.The wherein logical relation of feature ruler r are as follows: r1=r2=r3 < r4 < r5, wherein r1, r2, r3, r4, r5 respectively represent complementation
Structure sheaf, reflective metals contact layer, N electrode, the first passivation layer, luminescent layer fan-shaped radius.
Figure 13 is the top view for the LED chip that a kind of light-emitting surface of the invention is Pentagram shape；Graphical epitaxial layer 000
With the Pentagram shape having the same of reflective metals contact layer 302.601 shape of the first passivation layer 501 and N electrode at light-emitting surface
Identical, shape forms complementary with graphical 000 shape of epitaxial layer, and the N electrode figure other than light-emitting surface is can be with particular design
, while it is complementary structure layer 301, reflective metals contact layer that N electrode 601, which projects 000 corresponding region of INFERIOR GRAPH epitaxial layer,
Corresponding graphical epitaxial layer 000 shines at 302, and corresponding graphical epitaxial layer 000 shines at complementary structure layer region 301
It is weak, while not shining outside graphical 000 region of epitaxial layer.Therefore, chip light emitting face shape illustrated in Figure 13 is a standard
Pentagon.The wherein logical relation of feature ruler 1 are as follows: l1=l2=l3 < l4 < l5, wherein l1, l2, l3, l4, l5 are respectively represented
Complementary structure layer, reflective metals contact layer, N electrode, the characteristic size of the first passivation layer, luminescent layer.
Figure 14 is the top view for the LED chip that a kind of light-emitting surface of the invention is annulus shape；000 He of graphical epitaxial layer
The annulus shape having the same of reflective metals contact layer 302.601 shape phase of the first passivation layer 501 and N electrode at light-emitting surface
Together, shape is formed complementary with graphical 000 shape of epitaxial layer, the N electrode figure other than light-emitting surface can with particular design,
It is complementary structure layer 301, reflective metals contact layer 302 that N electrode 601, which projects 000 corresponding region of INFERIOR GRAPH epitaxial layer, simultaneously
Locate corresponding graphical epitaxial layer 000 shine, and at complementary structure layer region 301 corresponding graphical epitaxial layer 000 shine it is weak,
It does not shine outside graphical 000 region of epitaxial layer simultaneously.Therefore, chip light emitting face shape illustrated in Figure 14 is a standard annulus
Shape.The wherein logical relation of feature ruler d are as follows: d11=d12=d13 < d14 < d15, wherein d11, d12, d13, d14, d15 points
The outside diameter of complementary structure layer, reflective metals contact layer, N electrode, the first passivation layer, luminescent layer is not represented；D21=d22=
D23 > d24 > d25, wherein d21, d22, d23, d24, d25 respectively represent complementary structure layer, reflective metals contact layer, N electrode,
The interior circular diameter of first passivation layer, luminescent layer.
Figure 15 is the vertical view for the LED chip that the three chips units that a kind of light-emitting surface of the invention is " NCU " printed words form
Schematic diagram；Graphical epitaxial layer 000 and reflective metals contact layer 302 are respectively to have alphabetical " N " " C " " u "-shaped shape.At light-emitting surface
The first passivation layer 501 it is identical with 601 shape of N electrode, shape forms complementary, light-emitting surface with graphical 000 shape of epitaxial layer
N electrode figure in addition can be with particular design, while the projection of N electrode 601 000 corresponding region of INFERIOR GRAPH epitaxial layer is
Complementary structure layer 301, corresponding graphical epitaxial layer 000 shines at reflective metals contact layer 302, and complementary structure layer region
Corresponding graphical epitaxial layer 000 shines weak at 301, while not shining outside graphical 000 region of epitaxial layer.Therefore, Tu15Suo
The chip light emitting face shape of signal is " NCU " printed words.
To manufacture the LED chip that a kind of light-emitting surface above-mentioned is specific plane geometric figure, the present invention also proposes a kind of hair
Smooth surface is the LED core piece preparation method of specific plane geometric figure, comprising the following steps:
Step 1: substrate 101 being provided, forms LED epitaxial layer 100, including buffer layer 102, n-layer on the substrate 101
103, luminescent layer 104 and p-type layer 105；
Step 2: complementary structure layer 301, reflective metals contact layer 302, bonding are sequentially formed on the epitaxial layer 100
Protective layer 303；
Step 3: supporting substrate 201 being provided, sequentially forms substrate front side protective layer in the front of the supporting substrate 201
202, bonded layer 203 sequentially form substrate back side protective layer 204, contact layer 205 in the reverse side of the supporting substrate 201；
Step 4: using wafer thermocompression bonding method, by bonded layer 203 and bond protective layer 303 for the epitaxial layer
100 bind together with substrate layer 200；
Step 5: removing the substrate 101, buffer layer 102, obtain the epitaxial layer of vertical structure, be followed successively by n from top to bottom
Type layer 103, luminescent layer 104 and p-type layer 105；
Step 6: preparing roughened layer 401 on 103 surface of n-layer；
Step 7: removal specific region epitaxial layer, 000 structure of graphical epitaxial layer remained are specific plane geometry
Figure；
Step 8: preparing the first passivation layer in chip surface and make the first passivation layer pattern by lithography, it is blunt to obtain graphical first
Change layer 501；
Step 9: preparing N electrode in the first passivation layer surface and graphical epitaxial layer portion region surface；
Step 10: two passivation layer of growth regulation simultaneously makes the second passivation layer pattern by lithography, obtains graphical second passivation layer 701,
Obtain the LED chip that light-emitting surface is particular geometric figure.
It is different specific plane geometric figures for light-emitting surface, compares basic structure and its preparation side of above-mentioned LED chip
Method.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (10)
1. the LED chip that a kind of light-emitting surface is specific plane geometric figure, it is characterised in that: the LED chip includes substrate layer,
Substrate layer successively includes contact layer, substrate back side protective layer, supporting substrate, substrate front side protective layer, bonded layer from bottom to up；Base
The upper surface of plate layer is successively arranged bonding protective layer, reflective metals contact layer from bottom to up, sets in the upper surface of reflective metals contact layer
There is graphical epitaxial layer；Graphical epitaxial layer and reflective metals contact layer are of similar shape；
Graphical epitaxial layer successively includes: complementary structure layer, p-type layer, luminescent layer, n-layer from bottom to up；In graphical epitaxial layer
It is equipped with the first passivation layer, N electrode and the second passivation layer above；
The graphical epitaxial layer shape is specific plane geometric figure, and the light-emitting surface is patterned epitaxial layer, figure
Change and be equipped with the first passivation layer above epitaxial layer, the first passivation layer is equipped with N electrode, and entire chip surface is equipped with the second passivation layer；
The first passivation layer at light-emitting surface is identical with N electrode shape, and shape forms complementary with graphical epitaxial layer shape；
It is complementary structure layer that N electrode, which projects INFERIOR GRAPH epitaxial layer corresponding region,.
2. the LED chip that light-emitting surface according to claim 1 is specific plane geometric figure, it is characterised in that: reflection gold
Belong to contact layer and graphical epitaxial layer forms lower ohmic contact resistance, and there is high reflectance, at reflective metals contact layer
Corresponding graphical epitaxial layer light emission luminance is high, and corresponding graphical epitaxial layer light emission luminance is low at complementary structure layer region,
Graphically epi region is overseas simultaneously does not shine.
3. the LED chip that light-emitting surface according to claim 1 is specific plane geometric figure, it is characterised in that: described
Graphical epitaxial layer is circle, the plane geometric figure structure of sector, circular ring shape, Pentagram shape, or graphically epitaxial layer
It include various text shapes in graphic structure.
4. the LED chip that light-emitting surface according to claim 1 is specific plane geometric figure, it is characterised in that: first is blunt
Change layer material is one of silica, silicon nitride, nitrogen-oxygen-silicon, polyimides, realizes p-type layer and n-layer in edge exhausted
Edge.
5. the LED chip that light-emitting surface according to claim 1 is specific plane geometric figure, it is characterised in that: complementation knot
Structure layer is dielectric film；Or to form the metal layer of high contact resistance with graphical epitaxial layer；Or for by plasma
The graphical epi-layer surface be surface-treated, being destroyed, the ohmic contact resistance between reflective metals contact layer become larger；Or
For the graphical epitaxial layer for etching away current extending by etching technics, keep its current expansion less able.
6. the LED chip that light-emitting surface according to claim 1 is specific plane geometric figure, it is characterised in that: described anti-
It penetrates the material of metal contact layer and graphical epitaxial layer forms lower ohmic contact resistance, and metal list with high reflectivity
Layer or laminated construction with high reflectivity；The material of the reflective metals contact layer is Ag, Al, Pt, Rh, Ni/Ag, Ag/
One of Ni/Ag, Ni/Al or Ni/Ag/Ni/Ag.
7. the LED chip that light-emitting surface according to claim 1 is specific plane geometric figure, it is characterised in that: described
The contact resistance bonded between the material and graphical epitaxial layer of protective layer is very high, and has antiacid alkali rotten with antiradar reflectivity
The metal single layer of erosion ability；Or protective layer is bonded as laminated construction, and first contacted in laminated construction with graphical epitaxial layer
Layer material is difficult to formed low ohm contact resistance, and has antiradar reflectivity, and laminated material has antiacid caustic corrosion ability；Institute
The metal single layer material for the bonding protective layer stated is one of Cr, Pt, Ti, W or Au；Or the lamination of the bonding protective layer
The material of structure is Cr/Pt/Au, Cr/Pt/Ag, Cr/Pt/Ag/Cu/Ag, Cr/Pt/Cr/Pt/Au/Ag, Ti/Pt/Au or Ti/
One of W/Ti/Pt/Au.
8. the LED chip that light-emitting surface according to claim 1 is specific plane geometric figure, it is characterised in that: described
First passivation layer thickness is 0.1 μm~10 μm, the bonded layer with a thickness of 1 μm~10 μm, the described bonding protective layer
With a thickness of 0.1 μm~10 μm, the reflective metals contact layer is with a thickness of 0.05 μm~1 μm, the substrate front side protective layer
With a thickness of 0.5 μm~10 μm, the substrate back side protective layer with a thickness of 0.5 μm~10 μm；The thickness of the substrate layer
Degree be 60 μm~600 μm, the contact layer with a thickness of 0.1 μm~10 μm.
9. the LED core piece preparation method that a kind of light-emitting surface is specific plane geometric figure, which is characterized in that the described method includes:
Step 1: substrate being provided, forms LED epitaxial layer over the substrate, the epitaxial layer includes buffer layer, n-layer, shines
Layer and p-type layer；
Step 2: complementary structure layer, reflective metals contact layer, bonding protective layer are sequentially formed on the epitaxial layer；
Step 3: supporting substrate being provided, substrate front side protective layer, bonded layer are sequentially formed in the front of the supporting substrate, in institute
The reverse side for stating supporting substrate sequentially forms substrate back side protective layer, contact layer；
Step 4: using wafer thermocompression bonding method, bound the epitaxial layer and substrate layer by bonded layer and bonding protective layer
Together；
Step 5: removing the substrate, buffer layer, obtain the epitaxial layer of vertical structure, be followed successively by n-layer, luminescent layer from top to bottom
And p-type layer；
Step 6: preparing roughened layer on the n-layer surface；
Step 7: removal specific region epitaxial layer, the graphical epitaxial layer structure remained are specific plane geometric figure；
Step 8: preparing the first passivation layer in chip surface and make the first passivation layer pattern by lithography, obtain graphical first passivation
Layer；
Step 9: preparing N electrode in the first passivation layer surface and graphical epitaxial layer portion region surface；
Step 10: two passivation layer of growth regulation simultaneously makes the second passivation layer pattern by lithography, obtains graphical second passivation layer, is shone
Face is the LED chip of particular geometric figure.
10. light-emitting surface according to claim 9 is the LED core piece preparation method of specific plane geometric figure, feature exists
In in the step 7, the graphical epitaxial layer remained is circle, the plane of sector, circular ring shape, Pentagram shape is several
Comprising various text shapes in what graphic structure, or the graphic structure of graphical epitaxial layer that remains.
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