CN107026116B - 用于减小半导体器件中的热机械应力的方法以及对应器件 - Google Patents

用于减小半导体器件中的热机械应力的方法以及对应器件 Download PDF

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CN107026116B
CN107026116B CN201610983331.0A CN201610983331A CN107026116B CN 107026116 B CN107026116 B CN 107026116B CN 201610983331 A CN201610983331 A CN 201610983331A CN 107026116 B CN107026116 B CN 107026116B
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layer
metallization
semiconductor device
metallization layer
corner
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CN107026116A (zh
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P·科尔帕尼
A·米拉尼
L·瓜里诺
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STMicroelectronics SRL
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Abstract

在一个实施例中，一种半导体器件包括一个或多个金属化层，诸如例如Cu‑RDL金属化层，设置在电介质层之上的钝化层上。在金属化层的角部附近穿过钝化层和电介质层提供过孔。过孔可以是不具有去往有源器件的电连接的“虚设”过孔，并且可以设置在距位于下方金属层上的所述汇聚侧边的每一个近似1微米(10‑6m)和近似10微米(10‑5m)之间的距离处。

Description

用于减小半导体器件中的热机械应力的方法以及对应器件
技术领域
本说明书涉及减小半导体器件中的热机械应力。
一个或多个实施例可以适用于例如，例如用于车辆和消费产品的集成电路。
背景技术
各种类型的集成电路(IC)可以采用诸如BCD(双极-CMOS-DMOS)技术之类的技术。
BCD技术可以有利地例如用于生产具有功率电子器件和逻辑控制电子器件的集成电路。BCD技术提供了一系列硅工艺，每个硅工艺将三个不同工艺技术的效力组合至单个芯片上：用于精确模拟功能的双极，用于数字设计的CMOS(互补金属氧化物半导体)，以及用于功率和高电压元件的DMOS(双扩散金属氧化物半导体)。
实施BCD技术可以包括顶层铜金属互联，所谓的再分布层(RDL)。
例如由在接线键合和封装工艺期间的热弹性耦合和应力所引起的、钝化和中间绝缘层对于可靠性的抵抗问题可能呈现需要关注的因素。
氮化硅(SiN)或碳化硅(SiC)可以用于制造IC以提供用于微芯片的钝化层，例如用于提供抵抗水分子以及微电子中的腐蚀和不稳定性的其他来源的阻挡层。
在诸如Cu(铜)RDL顶部金属化层之类的金属化层的结构角部中，由于不同材料之间的热机械失配而可能引起应力，不同的材料例如阻挡层(TiW，Ta，TaN)、金属化包覆层(Ni-Pd，Ni-Pd-Au，Ni-Au)、钝化层(SiN，SiC)三相点。
发明内容
一个或多个实施例克服前文中所述的现有技术的问题而作出贡献，例如在Cu RDL结构的边缘处(例如，在角部处)的钝化层上表面中的钝化应力。
根据一个或多个实施例，一种方法制造半导体器件并且包括：
在电介质层之上提供钝化层；
在钝化层上提供金属化层，金属化层具有角部；以及
提供在所述角部附近穿过所述钝化层和所述电介质层的过孔。
一个或多个实施例也可以涉及对应的半导体器件。
权利要求是在此所提供的一个或多个实施例的技术公开的整体部分。
一个或多个实施例可以包括，例如插入虚设过孔(也即不具有至有源器件的电连接的过孔)，诸如再分布层(RDL)过孔，尽可能靠近RDL角部位于下方金属层(Metal n-1)上。类似的实施例可以包括设计用于获得与虚设过孔相同的RDL角部接近度的电功能性过孔。
一个或多个实施例可以降低例如三相点应力。
一个或多个实施例可以通过仅作用于布图规则而提高钝化鲁棒性，无需工艺修改，也即并未影响最终用户。
附图说明
现在将参照附图、纯粹借由示例的方式描述一个或多个实施例，其中：
图1是一个或多个实施例可以适用的金属化层的垂直截面图，以及
图2是根据一个或多个实施例的如图1中所示例的金属化层的一部分的平面图。
应该知晓的是，为了说明清晰的目的，附图可以不按照相同比例而绘制。
具体实施方式
在随后的说明书中，示出了一个或多个具体细节，目的在于提供对实施例的示例的深入理解。可以在不采用一个或多个具体细节的情况下或者采用其他方法、部件、材料等而获得实施例。在其他情形中，已知的结构、材料或操作并未详细示出或描述，以使得将不模糊实施例的某些特定方面。
在本说明书的框架中对“实施例”或“一个实施例”的参考意在指示关于实施例所述的特定配置、结构或特性被包括在至少一个实施例中。因此，可以存在于本说明书的一个或多个点中的、诸如“在实施例中”或“在一个实施例中”之类的短语不必涉及相同实施例。此外，特定的构造、结构或特性可以以任何适当的方式在一个或多个实施例中组合。
在此所使用的参考纯粹为了方便而被提供并且并未限定保护范围或实施例的范围。
诸如，可能涉及在无电镀沉积之前的Cu激活工艺的例如具有Ni-Pd、Ni-Pd-Au、Ni-Au和/或镍基包覆层的Cu结构的半导体器件金属化层展现了技术调研的广阔区域。
相关活动的示例，例如是：
-P.K.Yee等人：“Palladium-Copper Inter-diffusion during CopperActiviation for Electroless Nickel Plating Process on Copper Power Metal”，2014年第21届IEEE国际集成电路物理与失效分析会议(IPFA)，
-US 6 093 631 B1，或
-US 6 413 863 B1。
图1是在半导体器件中的金属化层10的可能布置的示例，诸如例如设置在衬底上的Cu接线键合焊盘，衬底诸如具有在电介质层22之上的钝化层(例如，SiN、SiC)12、具有在金属化层10(例如Cu-RDL(再布线层)结构)下方用作阻挡层的层14(例如，TiW、Ta、TaN)的衬底。
在一个或多个实施例中，如图2中所示的金属化层(Cu-RDL结构)10可以展现朝向角部10b汇聚的两个侧边10a。在一个或多个实施例中，角部10b可以包括例如，至少略微倾斜的顶点(或适当的角部)。
观察到，诸如钝化应力之类的应力可能在例如Cu-RDL结构的边缘(足部)处SiN或SiC上表面中出现，在Cu_RDL角部10b处具有较高数值，例如在Cu-RDL结构10下方的阻挡层14与设置在金属化层10上的(例如，Ni基)包覆层20接触处的三相点TP(参见图1)处。
在一个或多个实施例中，至少一个过孔16(也即钝化层12和电介质层22中通孔)可以设置在位于下方金属层24上的金属化层10下方。
在一个或多个实施例中，过孔16可以包括“虚设”过孔，也即不具有至任何有源器件的电连接的过孔。
在如图1中所示的一个或多个实施例中，金属化层10可以延伸进入过孔16中。
在如图1中所示的一个或多个实施例中，用作金属化层10下方的阻挡层的阻挡层14(例如，TiW、Ta、TaN)可以形成为过孔16加衬的衬垫层。
在一个或多个实施例中，过孔16可以例如是再布线层(RDL)过孔，位于再布线层(RDL)过孔上的当前称作Metal n-1(下方金属层24)。
在一个或多个实施例中，过孔16可以被布置为尽可能靠近角部10b。
在一个或多个实施例中这可以包括提供过孔16，为该目的，可以距联合限定了金属化层10的角部部分10b的每个汇聚侧边10a在近似1微米(10-6m)和近似10微米(10-5m)之间的距离d’、d”通过任何已知手段来提供过孔16。
在一个或多个实施例中，发现该措施通过仅作用于金属化层的布图规则而改进了钝化鲁棒性，无需工艺修改，也即并未对最终产品性能产生显著影响。
本申请人公司执行的试验已经证明过孔16的该布置展现了与钝化故障发生的相关性，在提供了过孔16的那些位置处故障的数目减少(并且理论上为零)。
因此，可以得出结论，过孔的存在可以有效地降低钝化层应力。
在损害以下原理的情况下，细节和实施例可以相对于纯粹借由示例方式公开的内容而改变、甚至显著改变，而并未脱离保护范围。
如上所述的各个实施例可以组合以提供其他实施例。可以在以上详述的说明书的教导下对实施例做出这些和其他改变。通常，在以下权利要求中，使用的术语不应解释为将权利要求限定于说明书和权利要求中所公开的具体实施例，而是应该解释为包括所有可能的实施例以及这些权利要求被赋予的等价形式的全部范围。因此，权利要求不由本公开限制。

Claims (16)

1.一种方法，包括：
制造半导体器件，所述制造包括：
在电介质层之上提供钝化层；
在所述钝化层上提供金属化层，所述金属化层具有角部；以及
在所述角部附近提供穿过所述钝化层和所述电介质层的过孔，所述金属化层的一部分在所述过孔中，其中所述金属化层在所述过孔中的所述部分成形为截头锥体，所述截头锥体具有基部和顶端，所述顶端比所述基部离所述钝化层更远。
2.根据权利要求1所述的方法，其中提供所述过孔包括提供不具有去往有源器件的电连接的过孔。
3.根据权利要求1所述的方法，其中：
所述角部包括汇聚侧边；以及
提供所述过孔包括以距所述汇聚侧边的每一个1微米和10微米之间的距离而提供所述过孔。
4.根据权利要求1所述的方法，其中提供所述金属化层作为Cu金属化层。
5.根据权利要求1所述的方法，其中提供所述过孔包括提供所述过孔作为位于下方金属层上的过孔。
6.根据权利要求1所述的方法，进一步包括，形成为所述过孔加衬并且在所述金属化层下方的阻挡层。
7.一种半导体器件，包括：
电介质层；
钝化层，在所述电介质层之上；
金属化层，具有角部；
过孔，在所述角部附近穿过所述钝化层和所述电介质层；以及
在所述电介质层下方的下方金属层，其中所述金属化层在所述过孔中的部分包括位于所述下方金属层上的过孔，其中所述金属化层是有源层，并且所述下方金属层除了与所述过孔中的所述金属化层的所述部分的连接之外被电隔离。
8.根据权利要求7所述的半导体器件，其中所述过孔不具有去往有源器件的电连接。
9.根据权利要求7所述的半导体器件，其中所述角部包括汇聚侧边，其中所述过孔距所述汇聚侧边的每一个1微米和10微米之间的距离。
10.根据权利要求7所述的半导体器件，其中所述金属化层包括Cu金属化层。
11.根据权利要求7所述的半导体器件，进一步包括为所述过孔加衬并且在所述金属化层下方的阻挡层。
12.一种半导体器件，包括：
电介质层；
钝化层，在所述电介质层之上；
金属化层，具有角部；
过孔，靠近所述角部穿过所述钝化层和所述电介质层，其中所述金属化层在所述过孔中延伸；
阻挡层，为所述过孔加衬并且在所述金属化层和所述钝化层之间延伸；以及
在所述金属化层上方的包覆层，所述包覆层在所述金属化层的所述角部处抵接所述阻挡层。
13.根据权利要求12所述的半导体器件，其中所述过孔不具有去往有源器件的电连接。
14.根据权利要求12所述的半导体器件，其中所述角部包括汇聚侧边，其中所述过孔距所述汇聚侧边的每一个1微米和10微米之间距离。
15.根据权利要求12所述的半导体器件，其中所述金属化层包括Cu金属化层。
16.根据权利要求12所述的半导体器件，进一步包括在所述电介质层下方的下方金属层，其中所述过孔包括位于所述下方金属层上的过孔。
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