CN107017174B - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN107017174B CN107017174B CN201611241079.2A CN201611241079A CN107017174B CN 107017174 B CN107017174 B CN 107017174B CN 201611241079 A CN201611241079 A CN 201611241079A CN 107017174 B CN107017174 B CN 107017174B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 289
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims description 38
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000010949 copper Substances 0.000 claims abstract description 23
- 229910052802 copper Inorganic materials 0.000 claims abstract description 18
- 239000008393 encapsulating agent Substances 0.000 claims abstract 4
- 238000007789 sealing Methods 0.000 claims description 130
- 229920005989 resin Polymers 0.000 claims description 58
- 239000011347 resin Substances 0.000 claims description 58
- 239000000725 suspension Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 9
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims 2
- 230000008878 coupling Effects 0.000 abstract description 55
- 238000010168 coupling process Methods 0.000 abstract description 55
- 238000005859 coupling reaction Methods 0.000 abstract description 55
- 239000000463 material Substances 0.000 description 25
- 230000008569 process Effects 0.000 description 25
- 230000004048 modification Effects 0.000 description 21
- 238000012986 modification Methods 0.000 description 21
- 230000035882 stress Effects 0.000 description 21
- 230000000694 effects Effects 0.000 description 9
- 238000012360 testing method Methods 0.000 description 8
- 230000008602 contraction Effects 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000011231 conductive filler Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 101700004678 SLIT3 Proteins 0.000 description 1
- 102100027339 Slit homolog 3 protein Human genes 0.000 description 1
- 229910020830 Sn-Bi Inorganic materials 0.000 description 1
- 229910020888 Sn-Cu Inorganic materials 0.000 description 1
- 229910018728 Sn—Bi Inorganic materials 0.000 description 1
- 229910019204 Sn—Cu Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49544—Deformation absorbing parts in the lead frame plane, e.g. meanderline shape
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- H01L23/49838—Geometry or layout
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- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
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- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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Abstract
本公开涉及半导体装置及其制造方法。半导体装置包括:管芯焊盘;形成有接合焊盘的半导体芯片;引线,引线的一个端部位于半导体芯片附近;连接电极和引线的耦接导线;以及密封体,密封体将半导体芯片、耦接导线、引线的一部分和管芯焊盘的一部分密封。管芯焊盘的下表面从密封体的下表面露出,管芯焊盘和耦接导线包括铜,并且半导体芯片的厚度大于管芯焊盘的厚度与从半导体芯片的上表面到密封体的上表面的厚度之和。
Description
相关申请的交叉引用
通过引用将2016年1月27日提交的日本专利申请No.2016-013151的公开(包括说明书、附图和摘要)整体地并入本文中。
技术领域
本发明涉及一种有效应用于例如其中管芯焊盘从密封体露出的树脂密封型的半导体装置的技术和一种半导体装置的制造方法。
背景技术
在日本未经审查的专利申请公开No.2010-165777和日本未经审查的专利申请公开No.H06-252318中的每个中,公开了一种半导体装置,该半导体装置具有其上安装有半导体芯片的管芯焊盘并且管芯焊盘从密封体的背表面露出。
在日本未经审查的专利申请公开No.2010-165777的摘要中,公开了一种技术,用于布置总线1d以使得内引线1a与总线1d之间的间隔至少变为总线1d与密封体3的安装表面3b之间的间隔,从而使管芯焊盘从密封体露出。
在日本未经审查的专利申请公开No.H06-252318的摘要中,公开了一种技术,用于提供从载物台2的圆周边缘上的位置倾斜向上延伸的锚臂22和22A以及锚和压臂23、23A、24和24A,从而防止载物台从树脂封装体剥离。
发明内容
现在,存在随着半导体芯片的功能升级和速度加快,从半导体芯片产生的大量的热量(半导体芯片的热值)也增加的趋势。因此,上述的其中管芯焊盘从密封体露出的半导体装置的结构被研究作为用于散热的措施。
根据本申请的发明人和其他人进行的研究,在管芯焊盘从密封体露出的半导体装置中,已经发现由于半导体芯片与管芯焊盘、管芯焊盘与密封树脂、半导体芯片的表面与密封树脂等之间发生的界面剥离,在半导体芯片或密封体中产生裂纹,并且半导体芯片的可靠性降低。
也就是说,需要改善其中管芯焊盘从密封体露出的树脂密封型的半导体装置的可靠性。
本发明的其它主题和新颖特征将从本说明书的描述和附图而变得明显。
根据本发明的一个实施例,提供了一种半导体装置,该半导体装置包括芯片安装部、半导体芯片、引线和导线,芯片安装部包括第一上表面和位于第一上表面的相对侧的第一下表面,半导体芯片包括形成有电极的第二上表面和位于第二上表面的相对侧的第二下表面,引线在第一方向上延伸并且引线的一个端部位于半导体芯片附近,以及导线将半导体芯片的电极和引线连接。此外,半导体装置包括密封体,该密封体包括第三上表面和位于第三上表面的相对侧的第三下表面,并且密封体将半导体芯片、导线、引线的一部分和芯片安装部的一部分密封。于是,芯片安装部的第一下表面从密封体的第三下表面露出,芯片安装部和导线包括铜,并且半导体芯片的厚度大于芯片安装部的厚度与从半导体芯片的第二上表面到密封体的第三上表面的厚度之和。
根据本发明的一个实施例,可以改善半导体装置的可靠性。
附图说明
图1是示出根据本发明的第一实施例的半导体装置的一个示例的透视图。
图2是示出根据第一实施例的半导体装置的一个示例的平面图。
图3是沿着图2中的A-A'线得到的截面图。
图4是沿着图2中的B-B'线得到的截面图。
图5A是示出经历制造工艺的根据第一实施例的半导体装置的一个示例的截面图。
图5B是示出经历制造工艺的根据第一实施例的半导体装置的一个示例的截面图。
图5C是示出经历制造工艺的根据第一实施例的半导体装置的一个示例的截面图。
图5D是示出经历制造工艺的根据第一实施例的半导体装置的一个示例的截面图。
图5E是示出经历制造工艺的根据第一实施例的半导体装置的一个示例的截面图。
图6是示出经历制造工艺的根据第一实施例的半导体装置的引线框的一个示例的平面图。
图7是示出经历制造工艺的根据第一实施例的半导体装置的一个示例的截面图。
图8是示出经历图7的工艺后的制造工艺的半导体装置的一个示例的截面图。
图9是示出根据第二实施例的半导体装置的一个示例的截面图。
图10是示出根据第三实施例的半导体装置的一个示例的截面图。
图11是示出根据第四实施例的半导体装置的一个示例的平面图。
图12是沿着图11中的C-C'线得到的截面图。
图13是示出根据第一变形例的半导体装置的一个示例的平面图。
图14是沿着图13中的D-D'线得到的截面图。
图15是示出根据第二变形例的半导体装置的一个示例的平面图。
图16是示出发明人和其他人已经研究的半导体装置的一个示例的截面图。
具体实施方式
尽管在以下实施例中,当需要为了方便而进行划分时,将描述划分为多个部分或实施例,但是这些并非彼此无关,而是它们彼此相关使得一个部分或实施例覆盖另一个部分或实施例的变形例、详细解释、补充解释等的一些或全部,除非特别另有明确说明。
此外,在以下实施例中,在涉及构成元件的数目等(包括单元数、数值、量/质量、范围等等)的情况中,这并不限于特定数量并且可以至少和/或不多于特定数量,除非特别另有明确说明,除非另外在原理上绝对地限于特定数量。
此外,在以下实施例中,不言而喻,实施例的构成元件(还包括元件步骤等)不一定是必需的,除非特别另有明确说明,除非另外认为在原理上是明显必需的。
同样的,在以下实施例中,当涉及构成元件等的形状、它们之间的位置关系等时,应当包括基本上与这些形状等近似或类似的那些形状等,除非特别另有明确说明,并且除非另外明确认为它们在原则上不近似或不类似。这同样适用于上述的数值和范围。
此外,在示出来描述实施例的所有附图中,相同附图标号原则上指定给相同部件,并且省略其重复描述。顺便提及,为了容易示出附图,存在甚至在平面图中添加阴影线的情况。
<第一实施例>
首先,将描述本申请的发明人和其他人关于本申请的发明人和其他人已经研究的SOP(小外形封装)型半导体装置(半导体封装)阐明的主题。
以上提及的半导体装置用作例如车辆的电子组件。在车辆领域中,混合动力车辆、插电式混合动力车辆和电动车辆迅速普及,并且对于小型化以及燃料效率和引擎性能的改善的需求越来越多。然后,为了应对这些需求,已经大大改善了PCU(功率控制单元)的功率密度、电机驱动电池等。随着PCU的功率密度和电机驱动电池等的改善,存在车辆的电子组件在比以往更严酷(高温)的使用环境中使用的趋势。因此,在作为车辆的电子组件的半导体封装中,其中管芯焊盘从密封体的背表面露出的结构变为主流以改善散热性。
此外,要求车辆的半导体装置经受在比以往更严酷的条件(从约-65℃到约150℃的温度范围)下执行的温度循环测试,以保证在严酷的使用环境中的操作。在此,温度循环测试是在半导体装置的开发阶段要执行的可靠性评估测试。
图16是示出本申请的发明人和其他人已经研究的半导体装置的一个示例的截面图。顺便提及,图16示出了已经在半导体装置中发生翘曲(warping)的状态的一个示例。如图16所示,半导体装置包括半导体芯片7、已经形成在半导体芯片7的主表面上的多个管芯接合焊盘7e、已经经由耦接导线8连接到管芯接合焊盘7e的多个引线2、在其上经由管芯接合材料9安装半导体芯片7的管芯焊盘3以及将半导体芯片7密封的密封体1。然后,管芯焊盘3从密封体1露出,用于将半导体芯片7产生的热量辐射到外部。密封体1是固化的密封树脂。
根据本申请的发明人和其他人已经进行的研究,由于在制造半导体装置时(例如,在树脂密封工艺或温度循环测试中)或者在半导体装置已经安装之后,上述半导体装置经历高温和低温热应力,因此在半导体装置中发生半导体装置的中心部分向下或向上凸出的翘曲。然后,引起沿着半导体芯片7与管芯焊盘3、管芯焊盘3与密封树脂、半导体芯片7的主表面与密封树脂等之间的各界面的剥离的应力起作用,从而发生界面剥离并且导致在半导体芯片7或密封体1中产生裂纹。此外,在已经安装半导体装置之后,翘曲变为使得半导体装置与安装基板的耦接的可靠性变差的主要原因。顺便提及,尽管在图16中示出了半导体装置的中心部分向下翘曲的情况,但是半导体装置翘曲的方向取决于管芯焊盘3与密封体1的体积比率和树脂材料的组成。
在上述半导体装置中,由于管芯焊盘3从密封体1的背表面露出,因此半导体装置具有半导体芯片7位于密封体1的下方的结构(换句话说,在低于要与耦接导线8连接的内引线2a的耦接表面的一侧),并且在半导体芯片7的主表面上存在比较厚的密封树脂。然后,半导体芯片7的厚度小于半导体装置的厚度的1/3。此外,与半导体芯片7的厚度或半导体芯片7的主表面上的密封树脂的厚度相比,位于半导体芯片7的下方的管芯焊盘3的厚度非常薄。顺便提及,半导体装置的各组件的厚度如下。半导体装置(换句话说,半导体封装)的厚度为约1mm,半导体芯片7上的密封体1(密封树脂)的厚度L1为约0.575mm,半导体芯片7的厚度L2为约0.28mm,管芯焊盘3(和引线2)的厚度L3为约0.125mm,并且管芯接合材料9的厚度为约0.02mm,并且建立以下关系表达式(公式1)。
L1+L3>L2…(公式1)
另外,构成密封体1的密封树脂是含有诸如二氧化硅等添加剂的环氧树脂,并且密封树脂的热膨胀系数为约8ppm/K,由铜(Cu)板构成的管芯焊盘3的热膨胀系数为约17ppm/K,以及包括硅(Si)的半导体芯片7的热膨胀系数为约3.5ppm/K。
也就是说,例如,在半导体装置的厚度(高度)方向上,半导体装置具有如下结构:在热膨胀系数比较大的管芯焊盘3的上方布置热膨胀系数和膜厚度比较小的半导体芯片7,在半导体芯片7的上方布置热膨胀系数和膜厚度比较大的密封树脂,并且位于半导体芯片7上的密封树脂(密封体1的一部分)的厚度L1与管芯焊盘3的厚度L3之和大于半导体芯片7的厚度L2。因此,当半导体装置由于经历高温和低温应力而膨胀或收缩时,产生对半导体装置的中心部分向上或向下凸出起作用的应力(当中心部分向下凸出时,例如,产生图16所示的应力F1),并且因此在半导体装置中发生翘曲。换句话说,由于半导体芯片7的厚度与半导体装置的厚度的比率小(例如,小于1/3)并且半导体芯片7位于半导体装置的下侧,因此发生翘曲。
接下来,将描述被构成为解决上述主题的根据第一实施例的半导体装置的结构。
<半导体装置的结构>
图1是示出根据第一实施例的半导体装置的一个示例的透视图。图2是示出根据第一实施例的半导体装置的一个示例的平面图。图3是沿着图2中的A-A'线得到的截面图。图4是沿着图2中的B-B'线得到的截面图。如图1所示,根据第一实施例的半导体装置SD包括密封体1、多个引线2等。密封体1是矩形平行六面体(大致为矩形平行六面体),并且包括面对的主表面(上表面)1a和背表面(下表面)1b以及将主表面1a和背表面1b结合在一起的四个侧表面1s。主表面1a和背表面1b均包括具有长边和短边的矩形长方形形状(rectangularoblong shape),并且多个引线2在与长边正交的方向上分别从两个长边侧表面1s伸出。作为每个引线2的从密封体1露出的一部分的外引线(外侧部分)2b被成形为鸥翼状并且由第一部分、第二部分和第三部分构成,第一部分在远离密封体1的方向上延伸,第二部分从第一部分朝向密封体1的背表面1b侧延伸,以及第三部分连接到第二部分并在远离密封体1的方向上延伸。于是,第一部分和第三部分与密封体1的主表面1a或背表面1b大致平行。另外,第三部分与背表面1b几乎齐平。另外,每个悬置引线4在各短边侧表面1s处终止。引线2仅布置在两个长边侧表面1s上,而不布置在两个短边侧表面1s上。
如图2所示,半导体装置SD包括半导体芯片7、管芯焊盘(芯片安装部、桶(tub))3、悬置引线4、多个引线2、密封体1等。
半导体芯片7布置在半导体装置SD的中心部分上。半导体芯片7包括硅(Si),并且尽管未示出,但是在半导体芯片7的矩形长方形主表面7a上形成有多个半导体元件。此外,主表面7a上形成有已经与半导体元件电连接的多个接合焊盘(电极、外提取电极)7e。每个接合焊盘7e由包含铝(Al)或铜(Cu)作为主导体的导体膜构成,并且经由每个耦接导线8连接到每个引线2。
半导体芯片7安装(接合)在矩形长方形管芯焊盘(桶)3的主表面3a上。矩形长方形管芯焊盘3具有两个面对的长边3d和两个面对的短边3c,并且悬置引线4连接到两个短边3c的中心部分。悬置引线4在作为密封体1的长边方向的X方向上延伸,每个悬置引线4的一个端部连接到管芯焊盘3,并且每个悬置引线4的另一个端部到达密封体1的每个短边侧表面1s。另外,每个悬置引线4的所述一个端部侧设置有偏移部分4a。
多个引线2在与密封体1的长边正交的Y方向上延伸,由密封体1密封,并且由位于密封体1中的内引线2a和从密封体1露出并位于密封体1的外部的外引线2b构成。每个引线2的一个端部位于密封体中并且在半导体芯片7周围,并且每个引线2的另一个端部在密封体1的外部处终止。每个耦接导线8连接到每个引线2的一个端部,并且每个耦接导线8连接每个引线2和每个接合焊盘7e。引线2、管芯焊盘3和悬置引线4各自由膜厚度约为0.125mm(125μm)的铜(Cu)板(铜箔)构成。每个耦接导线8是直径为约30μm至约35μm的铜导线。
密封体1包括含有诸如二氧化硅等添加剂的环氧树脂,并且将半导体芯片7、耦接导线8、管芯焊盘3、悬置引线4和多个内引线2a密封。
如图3所示,半导体芯片7经由管芯接合材料9安装(接合)在管芯焊盘3的主表面3a上。管芯接合材料9是复合物的导电膏,在其中有机粘合剂中含有诸如银粉、铜粉等的导电填料。在管芯焊盘3的背表面3b从密封体1的背表面1b露出的结构的情况下,为了改善散热性,使用导电膏是有利的。然而,也可以使用绝缘膏。
已经形成在半导体芯片7的主表面7a上的接合焊盘7e经由耦接导线8连接到相应的引线2。在导线接合工艺中,首先,在每个耦接导线8的一个端部已经连接到每个接合焊盘7e之后,每个耦接导线8的另一个端部侧连接到每个内引线2a,并且之后切断耦接导线8,照原样保留其耦接部。也就是说,接合焊盘7e侧是第一接合点,而内引线2a侧是第二接合点。由于执行导线接合的上述顺序,半导体装置SD具有以下特征。
已经连接到每个接合焊盘7e的每个耦接导线8绘制如下的导线环线:从第一接合点远离半导体芯片7的主表面7a向上行进达到最高点,并且之后向下行进到每个内引线2a并连接到每个内引线2a。该导线环线的最高点被称为例如导线顶。导线顶位于半导体芯片7的正上方,换句话说,位于每个接合焊盘7e的正上方。
另外,在第一接合点处,在每个耦接导线8的一个端部上形成有球形部分8a,并且该球形部分8a连接到各接合焊盘7e。由于每个球形部分8a的直径大于每个耦接导线8的直径,所以如图3所示,每个球形部分8a的宽度大于(宽于)每个耦接导线8的宽度(直径)。另一方面,在第二接合点处,由于每个耦接导线8被压靠到每个内引线2a并与每个内引线2a连接,因此不存在球形部分8a。
另外,在第一接合点处,每个耦接导线8的延伸方向相对于半导体芯片7的主表面7a形成的角度θ1几乎为直角,并且保持在约80度≤θ1≤约110度的范围内。另外,在第二接合点处,每个耦接导线8的延伸方向相对于每个内引线2a形成的角度θ2通常保持在0度<θ2≤约60度的范围内,并且建立θ1>θ2的关系。
另外,如图3所示,在第一实施例中,使半导体芯片7的厚度L2a大于上述研究示例中的厚度L2(L2a>L2),并且使半导体芯片7的主表面7a上的密封树脂的厚度L1a小于上述研究示例中的厚度L1(L1a<L1)。半导体装置SD的厚度和管芯焊盘3的厚度L3a等于研究示例中的厚度L3(L3a=L3)。顺便提及,厚度L1a、L2a和L3a被设为使得L1a=约0.355mm、L2a=约0.5mm并且L3a=约0.125mm。因此,在第一实施例中,建立以下关系表达式(公式2)。
L1a+L3a≤L2a...(公式2)
通过使得半导体芯片7的厚度L2a厚(大)并且通过使半导体芯片7的主表面7a上的密封树脂的厚度L1a薄(小),以这种方式,根据第一实施例的半导体装置已经被结构化为使得设置在半导体芯片7的主表面7a上并且热膨胀系数比较大的密封树脂(密封体1的部分)的厚度L1a与热膨胀系数大的管芯焊盘3的厚度L3a之和在半导体装置SD的厚度(高度)方向上变得不大于半导体芯片7的厚度L2a。换句话说,通过使半导体芯片7的厚度与半导体装置SD的厚度的比率大(例如,至少1/3),防止了半导体装置SD的翘曲。在这种情况下,由于每个引线2在半导体装置SD的厚度(高度)方向上被布置在中心,所以半导体芯片7的主表面7a高于其上连接有各耦接导线8的各内引线2a的表面。
此外,优选使半导体芯片7的主表面7a上的密封树脂的厚度L1a薄到使得耦接导线8完全被隐藏的程度。也就是说,耦接导线8没有从主表面1a露出。当耦接导线8从密封体1的主表面1a露出时,担心由于(一个或多个)耦接导线8的断裂等可能降低半导体装置SD的可靠性。此外,还担心由于水通过每个耦接导线8和密封树脂之间的界面侵入到装置中,可能降低半导体装置SD的可靠性。
另外,如图2和图3所示,已经连接到每个接合焊盘7e并且由铜导线构成的每个耦接导线8越过半导体芯片7的主表面7a,并且连接到在平面图中位于半导体芯片7的外部的每个内引线2a。也就是说,半导体装置SD具有以下结构:由铜材料构成的多个耦接导线8覆盖半导体芯片7的主表面7a并且向下延伸到内引线2a,由铜材料构成的多个耦接导线8b布置在半导体芯片7的主表面7a侧,并且由铜材料构成的管芯焊盘3布置在半导体芯片7的背表面7b侧。由于以这种方式在半导体芯片7的主表面7a和背表面7b上的铜材料的布置,主表面7a侧和背表面7b侧上的膨胀率变得彼此接近,实现应力平衡,从而可以防止半导体装置SD翘曲。
如图4所示,管芯焊盘3的背表面3b从密封体1的背表面1b露出。然后,悬置引线4连接到管芯焊盘3,并且悬置引线4向上延伸到密封体1的侧表面1s并在侧表面1s处终止。悬置引线4各自包括相对于密封体1的背表面1b以角度θ3倾斜的偏移部分4a。有利地,每个偏移部分4a的倾斜角度θ3保持在约30度≤θ3≤约45度的范围内。这是因为,当倾斜角度θ3较浅时,所涉及的偏移部分4a不会经受塑性变形,并且管芯焊盘3的高度不稳定。当管芯焊盘3的高度变得不稳定时,可能发生以下不利影响:在后面描述的树脂密封工艺中,密封树脂移动(goes round)并侵入管芯焊盘3的背表面3b,并且管芯焊盘3的露出可能变得不充分。顺便提及,在图4中,虚线部分是管芯焊盘3与每个悬置引线4之间的边界。因此,位于每个偏移部分4a与管芯焊盘3之间的每个悬置引线4的一部分从密封体1露出。
<半导体装置的制造方法>
图5A至图5E都是示出经历制造工艺的根据第一实施例的半导体装置SD的一个示例的截面图。也就是说,图5A至图5E各自示出经历制造工艺的图3所示的半导体装置SD的截面的截面图。图6是示出经历制造工艺的根据第一实施例的半导体装置SD的引线框的一个示例的平面图。图7是示出经历制造工艺的根据第一实施例的半导体装置SD的一个示例的截面图。图8是示出经历图7的工艺后的制造工艺的根据第一实施例的半导体装置SD的一个示例的截面图。
首先,图5A示出了制备引线框LF的工艺的一个示例。如图5A和图6所示,包含铜(Cu)的引线框LF包括在X方向上延伸的一对外框6a和在Y方向上延伸的一对外框6b,在Y方向上延伸的多个引线2连接到外框6a,并且连接到管芯焊盘3并在X方向上延伸的悬置引线4连接到外框6b。另外,偏移部分4a形成在悬置引线4上,并且管芯焊盘3位于每个引线2的表面以下。在Y方向上延伸的多个引线2通过在X方向上延伸的汇流条5联系在一起并且连接到外框6b。每个引线2的位于管芯焊盘3侧上的一部分构成每个内引线2a,并且每个引线2的位于外框6a侧上的一部分构成每个外引线2b,其中每个汇流条5被设为边界。
在图6中,由外框6a和6b围绕并由虚线表示的区域是图2所示的半导体装置SD的形成区域。例如,一对外框6a在X方向上延伸,并且多个形成区域被布置在一对外框6a之间。也就是说,多个形成区域设置在引线框LF中。
接下来,图5B示出了管芯接合工艺的一个示例。通过使用管芯接合材料9将在主表面7a上形成有多个接合焊盘7e的半导体芯片7连接到管芯焊盘3上。将复合物的导电膏用作管芯接合材料9,其中在包含环氧系热固性树脂的有机粘合剂中含有诸如银粉、铜粉等的导电填料。顺便提及,还可以将称为DAF(管芯附接膜)的双面接合剂用作管芯接合材料9。
接下来,图5C示出了导线接合工艺的一个示例。首先,将由铜导线构成的各导线的一个端部连接到各管芯接合焊盘7e,并且之后连接到各引线2。然后,通过切断铜导线,照原样保留其耦接部来形成各耦接导线8。预先在引线2侧的铜导线耦接部的一部分上形成镀银层是有利的。另外,通过使用超声波接合与热压接合的组合来执行导线接合工艺是有利的。
接下来,图5D示出了树脂密封工艺和镀敷工艺的示例。通过使用例如由包含球形二氧化硅颗粒的热固性环氧树脂等构成的密封树脂,将半导体芯片7、内引线2、耦接导线8和管芯焊盘3密封来形成密封体1。不言而喻,管芯焊盘3的背表面3b从密封体1露出。
在树脂密封工艺中,首先,如图7所示,将其上已经执行了导线接合工艺的每个引线框LF放置在模具10的上模10a与下模10b之间。在这种情况下,半导体芯片7和耦接导线8安置在由上模10a和下模10b构成的空腔10cv1和10cv2中的每个中。在模具10中形成作为将密封树脂注入到空腔10cv1中的入口的浇口部分(gate part)10g、作为空腔10cv1与10cv2之间密封树脂的路径的贯穿浇口部分(through-gate part)10tg、流道(runner)10r和剔除部(cull)10cu。另外,在罐状部分(pot part)10pt的柱塞(plunger)10p上布置有作为密封树脂使用的片剂(tablet)11。
在上模10a和下模10b已经夹持在一起以将引线框LF夹在它们之间之后,柱塞10p向上移动,并且片剂11被送入到剔除部10cu,如图8所示。在这种情况下,由于模具10被加热到例如约175℃的高温,片剂11被熔化成流化树脂12。然后,利用柱塞10p的推力,使得流化树脂12从剔除部10cu穿过流道10r顺序地注入到空腔10cv1和10cv2中。
然后,将已经经历树脂密封工艺的每个引线框LF从模具10中取出,并使其温度返回到室温。然后,当使用热固性树脂作为密封树脂时,通过将已经经历了树脂密封工艺的每个引线框LF放入已经被加热到约175℃的干燥箱保持约6至7小时,对每个引线框LF执行固化加速工艺,然后将每个引线框LF从干燥箱中取出,并且使其温度返回到室温以增大树脂12的硬度(称为“固化烘烤工艺”)。也就是说,使在树脂密封工艺中被加热至高温的半导体芯片7、管芯焊盘3和树脂12(即,密封体1)冷却至室温,并在固化烘烤工艺中再次加热至高温,然后再次冷却至室温的这些工艺是翘曲的原因。然而,由于在第一实施例中,已经使半导体芯片7的厚度变厚,并且半导体芯片7的主表面7a上的密封树脂的厚度变薄,因此变得可以减少翘曲,并且变得可以防止半导体芯片7和/或密封体1破裂。
在完成树脂密封工艺的执行之后,相邻引线2之间以及每个引线2与每个外框6b之间的汇流条5被切断。然后,在各外引线2b的表面上形成焊料镀膜(未示出)。焊料镀膜由纯Sn材料、基于Sn-Bi的材料或基于Sn-Cu的材料构成。到目前为止已经描述的工艺在引线框LF的状态下执行。
图5E示出了引线形成工艺的一个示例。在完成镀敷工艺的执行之后,每个外引线2b与每个外框6a分离开。然后,将每个外引线2b形成为鸥翼状。此后,将每个悬置引线4从每个外框6b切开。以这种方式完成半导体装置SD。顺便提及,在一些情况下,对完成的半导体装置SD执行上述温度循环测试以确认安装可靠性。
在已经在图3所示的结构的半导体装置SD上施加高温和低温(诸如在温度循环测试中所假定的高温和低温)的热应力的情况下,反复发生半导体芯片7、密封体1和管芯焊盘3的膨胀和收缩,并且膨胀和收缩的反复发生导致半导体装置SD的翘曲。然而,在第一实施例中,由于已经使半导体芯片7的厚度变厚,并且半导体芯片7的主表面7a上的密封树脂的厚度变薄,因此可以减小半导体装置SD的翘曲。由此,由于可以减少引起沿着半导体芯片7与管芯焊盘3、管芯焊盘3与密封树脂、半导体芯片7的主表面7a与密封树脂等之间的相应界面的剥离的应力,因此可以防止半导体芯片7与管芯焊盘3之间的管芯接合材料9的破坏(块体破坏)和/或防止由密封体1的破裂引起的耦接导线8的破损。
<主要特征和有益效果>
半导体装置SD结构化为使得半导体芯片7上的密封树脂(密封体1的部分)的厚度L1a与管芯焊盘3的厚度L3a之和变为不大于半导体芯片7在半导体装置SD的厚度(高度)方向上的厚度L2a。
由此,即使已经在半导体装置SD上施加了高温和低温(诸如在树脂密封工艺或温度循环测试中所假定的高温和低温)的热应力,也可以减小引起沿着半导体芯片7与管芯焊盘3、管芯焊盘3与密封树脂、半导体芯片7的主表面7a与密封树脂等之间的相应界面的剥离的应力,并且可以抑制由界面剥离引起的半导体芯片7和/或密封体1的破裂。这里,通过考虑例如半导体装置SD的安装温度或者操作半导体装置SD时的温度来设定“诸如在温度循环测试中所假定的高温和低温”。也就是说,由于上述结构,当安装和/或操作半导体装置SD时,可以改善半导体装置SD的可靠性。
此外,由于可以减少由半导体装置SD的热膨胀和收缩引起的半导体装置SD的翘曲,因此施加到安装基板的安装部分(焊接部分)上的应力被释放并且可以改善半导体装置SD的可靠性,其中半导体装置SD的热膨胀和收缩与半导体芯片7的操作和半导体装置SD已经安装在安装基板上之后的环境温度的改变相关联地发生。
(第二实施例)
图9是示出根据第二实施例的半导体装置的一个示例的截面图。第二实施例是第一实施例的变形例。在根据第二实施例的半导体装置中,使管芯焊盘的厚度变薄并且使半导体芯片的厚度变厚。其它部分与第一实施例中的相同,并且相同的附图标号指定给这些部分。
在根据第二实施例的半导体装置SD1中,与根据第一实施例的半导体装置SD相比,管芯焊盘31的厚度L3b比厚度L3a薄(L3b<L3a),半导体芯片71的厚度L2b比厚度L2a厚(L2b>L2a),并且半导体芯片71的主表面71a上的密封树脂的厚度L1b等于厚度L1a(L1b=L1a)。也就是说,半导体芯片71的厚度增厚了管芯焊盘31变薄的量。也就是说,在根据第二实施例的半导体装置SD1中,也建立了与第一实施例的情况一样的以下关系表达式(公式3)。
L1b+L3b≤L2b…(公式3)
由于在第二实施例中,与第一实施例相比,管芯焊盘31的厚度(L3b)比厚度L3a薄,并且半导体芯片71的厚度(L2b)比厚度L2a厚,因此可以增加半导体芯片71的厚度与半导体装置SD1的厚度的比率,并且增加防止半导体装置SD1翘曲的效果。
另外,在第二实施例2中,半导体芯片71的主表面71a高于连接有各耦接导线8的各内引线2a的表面。但是,在管芯焊盘31的厚度比管芯接合材料9的厚度薄的情况下,主表面71a变得与连接有各耦接导线8的各内引线2a的表面齐平或者比连接有各耦接导线8的各内引线2a的表面低。
顺便提及,在第二实施例中,管芯焊盘31的厚度比每个内引线2a或每个外引线2b的厚度薄,即,使用薄型管芯焊盘。由于管芯焊盘31与由未示出的安装基板的金属形成的散热图案连接,并且半导体芯片71产生的热量经由散热图案传递,因此通过使用薄型管芯焊盘31来减少从半导体芯片71经由散热图案到安装基板的距离,并且可以改善半导体芯片71的散热性。
(第三实施例)
图10是示出根据第三实施例的半导体装置的一个示例的截面图。第三实施例是第一实施例的变形例,并且与第一实施例的不同之处在于连接每个耦接导线的顺序。也就是说,内引线2a侧是第一接合点,而接合焊盘7e侧是第二接合焊盘(例如,称为“反向接合”)。其它部分与第一实施例中的相同,并且将与第一实施例中相同的附图标号指定给这些部分。
在根据第三实施例的半导体装置SD2中,与根据第一实施例的半导体装置SD相比,半导体芯片7的主表面7a上的密封树脂的厚度L1c比厚度L1a薄(L1c<L1a)。半导体芯片7的厚度L2c和管芯焊盘3的厚度L3c分别等于厚度L2a(L2c=L2a)和厚度L3a(L3c=L3a)。也就是说,尽管半导体装置SD2的厚度减小了半导体芯片7的主表面7a上的密封树脂的厚度(L1c)减小的量,但是也在根据第三实施例的半导体装置SD2中建立以下关系表达式(公式4)。
L1c+L3c≤L2c…(公式4)
由于在第三实施例中,与第一实施例相比,半导体芯片7的主表面7a上的密封树脂的厚度(L1c)更薄并且相应地半导体装置SD2的厚度也更薄,因此可以增加半导体芯片7的厚度与半导体装置SD2的厚度的比率,并且增加防止半导体装置SD2翘曲的效果。
此外,尽管每个耦接导线81将每个内引线2a和半导体芯片7的每个接合焊盘7e连接,但是每个内引线2a和每个接合焊盘7e通过反向接合来连接,因此以上提及的导线顶位于每个内引线2a的正上方。此外,已经在每个耦接导线81的一个端部上形成的每个球形部分81a连接到每个内引线2a,并且每个耦接导线81的另一个端部经由每个凸起电极13连接到每个接合焊盘7e。凸起电极13例如是包括铜(Cu)的金属导体层。
由于内引线2a侧是第一接合点而接合焊盘7e侧是第二接合点,所以,在第一接合点处,每个耦接导线81的延伸方向相对于每个内引线2a的主表面(每个耦接导线81已经连接的表面)形成的角度为上述角度θ1(即,在约80度≤θ1≤约110度的范围内)。另外,在第二接合点处,每个耦接导线81的延伸方向相对于半导体芯片7的主表面7a形成的角度θ4保持在约0度≤θ4≤约30度的范围内,并且建立θ1>θ4的关系。另外,由于可以通过减小角度θ4来减小半导体芯片7上的密封树脂的厚度(L1c),因此在可能的范围内减小角度θ4是有利的。
顺便提及,在第三实施例中,通过应用根据第二实施例的薄型管芯焊盘,使半导体芯片7增厚了管芯焊盘变薄的量。此外,可以减小半导体芯片7的主表面7a上的密封树脂的厚度,并且进一步增加防止半导体装置SD2翘曲的效果。
(第四实施例)
图11是示出根据第四实施例的半导体装置的一个示例的平面图。图12是沿着图11中的C-C'线得到的截面图。第四实施例是第一实施例的变形例,并且与第一实施例的不同在于管芯焊盘的形状。其它部分与第一实施例中的相同,并且将与第一实施例中相同的附图标号指定给这些部分。
如图11所示,根据第四实施例的半导体装置SD3包括由芯片安装区域3m以及弯曲部分3v1和3v2构成的管芯焊盘32。在图11中,用虚线围绕的区域是芯片安装区域3m。芯片安装区域3m在平面图中为矩形长方形区域,并且具有在X方向和Y方向上比安装在其上的半导体7大的外形。
弯曲部分3v1和3v2分别沿着芯片安装区域3m的长边和短边设置。沿着芯片安装区域3m的每个长边设置的每个弯曲部分3v1形成在每个长边的整个长度上方,并且沿着每个短边设置的弯曲部分3v2形成在每个悬置引线4的两侧。尽管弯曲部分3v2设置在每个短边的几乎整个长度上方,但是有利的是将弯曲部分3v2与每个悬置引线4分离开。沿着芯片安装区域3m的每个长边设置的每个弯曲部分3v1和沿芯片安装区域3m的每个短边设置的每个弯曲部分3v2在芯片安装区域3m的每个角部处彼此分离开。另外,沿着芯片安装区域3m的每个短边设置的弯曲部分3v2与每个悬置引线4分离开。凹形部分3e形成在每个弯曲部分3v1与每个弯曲部分3v2之间以及每个弯曲部分3v2与每个悬置引线4之间,并且凹形部分3e到达芯片安装区域3m。
如图12所示,管芯焊盘32的芯片安装区域3m从密封体1的背表面1b露出,并且各弯曲部分3v1进入密封体1中。虽然在附图中未示出,但各弯曲部分3v2也进入密封体1中。图11中的虚线是芯片安装区域3m与弯曲部分3v1和3v2之间的边界。每个弯曲部分3v1(还有3v2)从图11中虚线部分上的芯片安装区域3m弯曲,并且相对于密封体1的背表面1b具有倾斜角度θ5。考虑到前面提及的塑性变形,将倾斜角度θ5保持在约30度≤θ5≤约60度的范围内将是有利的。由于弯曲部分3v1和3v2进入密封体1中,因此可以防止管芯焊盘32由于锚固效应(anchor effect)而从密封体1剥离。
通过使用芯片安装区域3m以及弯曲部分3v1和3v2来构成管芯焊盘32,可以将管芯焊盘32膨胀和收缩时施加的应力分散成在水平方向上起作用的应力F2以及在弯曲部分3v1和3v2延伸的方向上起作用的应力F3。因此,可以释放由于半导体芯片7与管芯焊盘32之间的热膨胀系数的差异引起的施加到管芯接合材料9上的应力。因此,可以防止裂纹扩展到管芯接合材料9中。此外,可以防止半导体芯片7从管芯焊盘32剥离。在引线2延伸的方向上和在悬置引线4延伸的方向上都形成弯曲部分3v1和3v2是重要的。由此,可以释放由于管芯焊盘32在引线2延伸的方向上和在悬置引线4延伸的方向上的热膨胀和收缩而引起的应力。
另外,由于弯曲部分3v1与弯曲部分3v2分离开,因此容易对弯曲部分3v1和3v2进行折叠,并且还改善了折叠精度。另外,由于各弯曲部分3v2与各悬置引线4分离开,因此各弯曲部分3v2的热膨胀和收缩不会对各悬置引线4产生影响,并且可以避免管芯焊盘32的高度变化。
另外,由铜材料构成的多个耦接导线8布置在半导体芯片7的主表面7a侧上,并且由铜材料构成的管芯焊盘32布置在半导体芯片7的背表面7b侧上。此外,多个耦接导线8倾斜,以便从半导体芯片7的上方朝着相应的内引线2a向下行进。另一方面,管芯焊盘32的弯曲部分3v1倾斜,以便从芯片安装区域3m朝向相应的内引线2a向上行进。如图12所示,耦接导线8和弯曲部分3v1相对于图12所示的穿过左右内引线2a的虚拟线X-X'在线对称的方向上延伸。由于由铜材料构成的多个耦接导线8布置在半导体芯片7的主表面7a侧上,由铜材料构成的管芯焊盘32布置在半导体芯片7的背表面7b侧上,并且耦接导线8延伸的方向相对于弯曲部分3v1延伸的方向线对称,以这种方式,可以保持施加到半导体芯片7的主表面7a与背表面7b上的应力之间的平衡,并且可以防止半导体装置SD3翘曲。
另外,根据第四实施例的半导体装置SD3的结构满足上述关系表达式(公式2)。这里,管芯焊盘32的厚度L3a对应于芯片安装区域3m的厚度。
另外,在第四实施例中,可以应用上述第二实施例、第三实施例或第二和第三实施例两者。
<第一变形例>
图13是示出根据第一变形例的半导体装置的一个示例的平面图。图14是沿着图13的D-D'线得到的截面图。第一变形例是第四实施例的变形例并且是管芯焊盘的变形例。其它部分与第一实施例中的相同,并且将与第一实施例中相同的附图标号指定给这些部分。
如图13所示,根据第一变形例的半导体装置SD4包括由芯片安装区域3m、弯曲部分3v1和3v2以及平坦部分3f构成的管芯焊盘33,并且在每个平坦部分3f中形成狭缝3s。根据第一变形例的芯片安装区域3m以及弯曲部分3v1和3v2在结构上与第四实施例中的相同,并且在第一变形例中,在弯曲部分3v1和3v2中每个的末端上设置其中形成有每个狭缝3s的每个平坦部分3f。
如图14所示,管芯焊盘33的芯片安装区域3m从密封体1的背表面1b露出,并且弯曲部分3v1和平坦部分3f进入密封体1中。尽管在附图中未示出,但是弯曲部分3v2也进入密封体1中。图13中的虚线表示芯片安装区域3m与弯曲部分3v1和3v2之间的边界,并且图13中的单点划线表示弯曲部分3v1和3v2与平坦部分3f之间的边界。平坦部分3f从弯曲部分3v1和3v2在远离芯片安装区域3m的方向上与密封体1的背表面1b平行地延伸。然后,在平坦部分3f中形成沿着芯片安装区域3m(或半导体芯片7)的长边或短边延伸的狭缝3s。密封树脂被充入狭缝3s中。
通过使用芯片安装区域3m、弯曲部分3v1和3v2以及平坦部分3f构成管芯焊盘33,可以将管芯焊盘33膨胀和收缩时施加的应力分散为在水平方向上起作用的应力F4、在弯曲部分3v1和3v2延伸的方向上起作用的应力F5以及在平坦部分3f延伸的方向上起作用的应力F6。因此,可以释放由于半导体芯片7与管芯焊盘33之间的热膨胀系数的差异引起的施加到管芯接合材料9上的应力。
另外,由于在相应的平坦部分3f中形成狭缝3s并将密封树脂充入狭缝3s中,因此可以抑制由于锚固效应引起的管芯焊盘33的膨胀和收缩,并且可以进一步释放施加到管芯接合材料9上的应力。
使得每个平坦部分3f的区域中的每个狭缝3s处于关闭状态是重要的。这是因为,当每个狭缝3s延伸跨过(string over)弯曲部分3v1和3v2以及每个平坦部分3f形成时,变得难以执行稳定的形成。
此外,狭缝3s的形成不是必须的,并且还可以在平坦部分3f中没有形成狭缝3s的情况下获得释放应力的效果。
<第二变形例>
图15是示出根据第二变形例的半导体装置的一个示例的平面图。第二变形例是第四实施例的变形例,并且是管芯焊盘的变形例。其它部分与第一实施例中的相同,并且将与第一实施例中相同的附图标号指定给这些部分。顺便提及,省略了安置在半导体芯片7下方的耦接导线8的图示。
如图15所示,根据第二变形例的半导体装置SD5包括由芯片安装区域3m以及弯曲部分3v1和3v2构成的管芯焊盘34。在图15中,用虚线围绕的区域是芯片安装区域3m。芯片安装区域3m在平面图中是矩形长方形区域,并且具有在X和Y方向上比安装在其上的半导体芯片7大的外形。
弯曲部分3v1和3v2分别沿着芯片安装区域3m的长边和短边设置。多个凹形部分3e分别设置在弯曲部分3v1和3v2中,并且多个凸形部分3p分别设置在弯曲部分3v1和3v2的末端上。每个凸形部分3p的末端(远离半导体芯片7的一侧)的宽度(W1)比每个凸形部分3p的内侧(更接近半导体芯片7的一侧)的宽度(W2)宽(W1>W2)。另一方面,每个凹形部分3e的末端的宽度比每个凹形部分3e的内侧的宽度窄,并且密封树脂被充入每个凹形部分3e中。
借助于这样形成的凹形部分3e和凸形部分3p的形状,锚固效应增加,从而可以减小管芯焊盘34的热膨胀和收缩。
虽然在第二变形例中,半导体装置SD5具有每个凹形部分3e没有到达芯片安装区域3m的结构,但是半导体装置SD5可以具有每个凹形部分3e到达芯片安装区域3m的结构。在任一种情况下,每个悬置引线4与每个凸形部分3p之间的每个凹形部分3e到达芯片安装区域3m将是有利的。
尽管如上所述,已经根据本发明的优选实施例具体描述了本申请的发明人和其他人做出的本发明,但是不用说,本发明不限于上述实施例并且可以在不偏离其要旨的范围内以各种方式进行改变和修改。例如,尽管已经通过使用SOP型半导体装置描述了上述实施例,但是本发明也适用于QFP(四方扁平封装)型半导体装置。
Claims (17)
1.一种半导体装置,包括:
芯片安装部,所述芯片安装部包括第一上表面和位于所述第一上表面的相对侧的第一下表面;
半导体芯片,所述半导体芯片包括第二上表面、形成在所述第二上表面上方的电极以及位于所述第二上表面的相对侧的第二下表面,并且所述半导体芯片安装在所述第一上表面上方;
引线;
导线,所述导线将所述半导体芯片的所述电极与所述引线连接;以及
密封体,所述密封体包括第三上表面和位于所述第三上表面的相对侧的第三下表面,并且将所述半导体芯片、所述导线、所述引线的一部分和所述芯片安装部的一部分密封,
其中所述芯片安装部的所述第一下表面从所述密封体的所述第三下表面露出,
其中所述芯片安装部和所述导线包括铜,并且
其中所述半导体芯片的厚度大于所述芯片安装部的厚度与从所述半导体芯片的所述第二上表面到所述密封体的所述第三上表面的厚度之和。
2.根据权利要求1所述的半导体装置,
其中所述引线在平面图中在第一方向上延伸,
其中所述芯片安装部包括安装所述半导体芯片的芯片安装区域,以及在所述第一方向上从所述芯片安装区域延伸的弯曲部分,
其中所述芯片安装部的所述第一下表面从所述密封体露出,并且
其中所述弯曲部分位于所述密封体中。
3.根据权利要求1所述的半导体装置,
其中所述导线的一个端部连接到所述电极,并且所述导线的另一个端部连接到所述引线的一个端部,以及
其中在垂直于所述第二下表面并且从所述第二下表面朝向所述第二上表面取向的方向上,所述导线的最远离所述第二上表面的一部分位于所述半导体芯片的正上方。
4.根据权利要求1所述的半导体装置,
其中所述芯片安装部的厚度比所述引线的厚度薄。
5.根据权利要求1所述的半导体装置,
其中在垂直于所述第二下表面并且从所述第二下表面朝向所述第二上表面取向的方向上,所述导线的最远离所述引线的一部分位于所述引线的正上方。
6.一种半导体装置,包括:
管芯焊盘,所述管芯焊盘包括第一上表面和在平面图中位于所述第一上表面的相对侧的第一下表面,所述第一上表面包括芯片安装区域和第一弯曲部分;
半导体芯片,所述半导体芯片安装在所述芯片安装区域中并且包括第二上表面、位于所述第二上表面的相对侧的第二下表面以及形成在所述第二上表面上方的电极;
密封体,所述密封体包括第三上表面和位于所述第三上表面的相对侧的第三下表面,并且将所述半导体芯片和所述管芯焊盘的所述第一上表面密封;
引线,所述引线的一个端部位于所述密封体中,并且所述引线的另一个端部位于所述密封体以外;以及
导线,所述导线位于所述密封体中并且将所述半导体芯片的所述电极与所述引线的一个端部连接,
其中所述管芯焊盘的所述第一下表面从所述密封体的所述第三下表面露出,
其中所述第一弯曲部分位于所述密封体中,
其中所述第一弯曲部分在第一方向上从所述芯片安装区域延伸,并且
其中所述半导体芯片的厚度大于所述芯片安装区域的厚度与从所述半导体芯片的所述第二上表面到所述密封体的所述第三上表面的厚度之和。
7.根据权利要求6所述的半导体装置,
其中所述引线在平面图中在所述第一方向上延伸,
其中所述管芯焊盘包括在与所述第一方向正交的第二方向上从所述芯片安装区域延伸的第二弯曲部分,
其中所述第二弯曲部分位于所述密封体中,并且
其中所述第一弯曲部分和所述第二弯曲部分被到达所述芯片安装区域的第一凹形部分分离开。
8.根据权利要求7所述的半导体装置,还包括:
悬置引线,所述悬置引线在所述第二方向上从所述芯片安装区域延伸,
其中所述第二弯曲部分和所述悬置引线被到达所述芯片安装区域的第二凹形部分分离开。
9.根据权利要求6所述的半导体装置,
其中所述第一弯曲部分包括在所述第一方向上从所述芯片安装区域突出的第一凸形部分和第二凸形部分。
10.根据权利要求9所述的半导体装置,
其中在所述第一凸形部分和所述第二凸形部分之间布置了第三凹形部分,并且
其中所述第三凹形部分到达所述芯片安装区域。
11.根据权利要求9所述的半导体装置,
其中更接近所述芯片安装区域的一侧的所述第一凸形部分的宽度比远离所述芯片安装区域的一侧的所述第一凸形部分的宽度窄。
12.根据权利要求6所述的半导体装置,
其中所述管芯焊盘包括在所述第一方向上从所述第一弯曲部分连续延伸的平坦部分,并且
其中所述平坦部分在与所述第三下表面平行的方向上延伸。
13.根据权利要求12所述的半导体装置,
其中在所述平坦部分中形成从所述第一上表面延伸并且到达所述第一下表面的狭缝。
14.一种半导体装置的制造方法,包括以下步骤:
(a):制备引线框,所述引线框包括芯片安装部和引线,并且包括铜,所述芯片安装部包括第一上表面和位于所述第一上表面的相对侧的第一下表面;
(b):将半导体芯片安装到所述芯片安装部上方,所述半导体芯片包括包含电极的第二上表面和位于所述第二上表面的相对侧的第二下表面,其中所述第二下表面和所述第一上表面彼此面对;
(c):通过包括铜的导线将所述引线与所述半导体芯片的所述电极连接;以及
(d):利用已经被加热并熔化的密封树脂将所述引线的一部分、所述芯片安装部的一部分、所述半导体芯片和所述导线密封,并形成密封体,
其中所述密封体包括第三上表面和位于所述第三上表面的相对侧的第三下表面,
其中所述芯片安装部的所述第一下表面从所述第三下表面露出,并且
其中在步骤(d)之后,从所述第二下表面到所述第二上表面的高度大于从所述第一下表面到所述第一上表面的高度与从所述第二上表面到所述第三上表面的高度之和。
15.根据权利要求14所述的半导体装置的制造方法,
其中所述引线在第一方向上朝向所述芯片安装部延伸,
其中所述芯片安装部包括要安装所述半导体芯片的芯片安装区域和在所述第一方向上从所述芯片安装区域延伸的弯曲部分,
其中在步骤(d)中,所述芯片安装部的所述第一下表面从所述密封体露出,以及
其中用所述密封树脂将所述弯曲部分密封。
16.根据权利要求14所述的半导体装置的制造方法,
其中在步骤(c)中,在连接到所述引线之后将所述导线连接到所述电极。
17.根据权利要求14所述的半导体装置的制造方法,
其中在步骤(a)中,制备所述芯片安装部的厚度比所述引线的厚度薄的引线框。
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