JP7156141B2 - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
- Publication number
- JP7156141B2 JP7156141B2 JP2019070785A JP2019070785A JP7156141B2 JP 7156141 B2 JP7156141 B2 JP 7156141B2 JP 2019070785 A JP2019070785 A JP 2019070785A JP 2019070785 A JP2019070785 A JP 2019070785A JP 7156141 B2 JP7156141 B2 JP 7156141B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor chip
- solder layer
- central portion
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Die Bonding (AREA)
Description
20 :リードフレーム
30 :金属ブロック
40 :半導体チップ
40d :中央部
50 :リードフレーム
52 :凸部
52a :中央側側面
52b :外側側面
60 :絶縁樹脂
80 :はんだ層
82 :はんだ層
84 :はんだ層
Claims (2)
- 半導体モジュールであって、
リードフレームと、
前記リードフレームの表面の一部に対してはんだ層を介して接続された半導体チップと、
前記半導体チップの周囲の前記リードフレームの前記表面を覆い、前記リードフレームよりも低い線膨張係数を有する絶縁樹脂、
を有し、
前記リードフレームが、前記リードフレームの前記表面から突出する凸部を有しており、
前記凸部が、前記半導体チップと前記リードフレームの積層方向に沿って見たときに、前記半導体チップと前記リードフレームが重なる範囲に配置されており、
前記凸部が、前記半導体チップと前記リードフレームの積層方向に沿って見たときに、前記半導体チップの中央部の周囲に配置されており、
前記凸部が、前記はんだ層に覆われており、
前記凸部の前記中央部側の第1側面の傾斜角度が、前記凸部の前記第1側面とは反対側に位置する第2側面の傾斜角度よりも大きい、
半導体モジュール。 - 前記半導体チップと前記リードフレームの積層方向に沿って見たときに、前記凸部が、前記中央部の周囲を囲むように伸びている、請求項1の半導体モジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019070785A JP7156141B2 (ja) | 2019-04-02 | 2019-04-02 | 半導体モジュール |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019070785A JP7156141B2 (ja) | 2019-04-02 | 2019-04-02 | 半導体モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020170774A JP2020170774A (ja) | 2020-10-15 |
JP7156141B2 true JP7156141B2 (ja) | 2022-10-19 |
Family
ID=72746782
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2019070785A Active JP7156141B2 (ja) | 2019-04-02 | 2019-04-02 | 半導体モジュール |
Country Status (1)
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JP (1) | JP7156141B2 (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003318348A (ja) | 2002-04-19 | 2003-11-07 | Denso Corp | 樹脂封止型電子装置 |
JP2006019346A (ja) | 2004-06-30 | 2006-01-19 | Mitsubishi Materials Corp | 構造体と、パワーモジュール基板と、その基板を用いたパワーモジュール、及び、それらの製造方法 |
JP2010103350A (ja) | 2008-10-24 | 2010-05-06 | Denso Corp | 半導体装置 |
JP2012209347A (ja) | 2011-03-29 | 2012-10-25 | Dainippon Printing Co Ltd | 半導体装置および半導体装置の製造方法 |
JP2017135230A (ja) | 2016-01-27 | 2017-08-03 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60128624A (ja) * | 1983-12-15 | 1985-07-09 | Fuji Electric Co Ltd | 半導体装置 |
-
2019
- 2019-04-02 JP JP2019070785A patent/JP7156141B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003318348A (ja) | 2002-04-19 | 2003-11-07 | Denso Corp | 樹脂封止型電子装置 |
JP2006019346A (ja) | 2004-06-30 | 2006-01-19 | Mitsubishi Materials Corp | 構造体と、パワーモジュール基板と、その基板を用いたパワーモジュール、及び、それらの製造方法 |
JP2010103350A (ja) | 2008-10-24 | 2010-05-06 | Denso Corp | 半導体装置 |
JP2012209347A (ja) | 2011-03-29 | 2012-10-25 | Dainippon Printing Co Ltd | 半導体装置および半導体装置の製造方法 |
JP2017135230A (ja) | 2016-01-27 | 2017-08-03 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
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JP2020170774A (ja) | 2020-10-15 |
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