CN106960814A - 像素结构的制造方法 - Google Patents

像素结构的制造方法 Download PDF

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CN106960814A
CN106960814A CN201610012509.7A CN201610012509A CN106960814A CN 106960814 A CN106960814 A CN 106960814A CN 201610012509 A CN201610012509 A CN 201610012509A CN 106960814 A CN106960814 A CN 106960814A
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layer
transparency electrode
manufacture method
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substrate
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张锡明
黄彦余
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Chunghwa Picture Tubes Ltd
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Chunghwa Picture Tubes Ltd
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Abstract

本发明提供一种像素结构的制造方法。该制造方法包括：于基板上形成栅极及覆盖栅极的栅绝缘层。于栅绝缘层上形成信道层，信道层的材料包括第一金属氧化物半导体材料。于信道层的相对两侧上形成源极与漏极。于基板上形成覆盖源极、漏极及信道层的绝缘层，其具有暴露出漏极的开口。于基板上依序形成第一及第二透明电极材料层，其中第一透明电极材料层的材料包括第二金属氧化物半导体材料，第二透明电极材料层的材料包括金属氧化物导电材料。利用同一掩模图案化第一及第二透明电极材料层，以形成第一及第二透明电极层，其中第一透明电极层通过开口与漏极接触。本发明的制造方法所制得的像素结构具有良好的电性表现以及可靠度。

Description

像素结构的制造方法
技术领域
本发明提供一种电子组件的制造方法，尤其涉及一种像素结构的制造方法。
背景技术
近年来，已有研究指出金属氧化物半导体材料具有高电子迁移率，故适合将其应用于像素结构中的薄膜晶体管作为信道层使用。在已知制造包括金属氧化物半导体薄膜晶体管的像素结构的方法中，通常是在基板上形成金属氧化物半导体薄膜晶体管后，才形成像素电极。一般而言，所述像素电极通常是选用溅镀法所形成的非晶型氧化铟锡，其中所使用的制程气体包括水或氢气。然而，对于金属氧化物半导体薄膜晶体管而言，进行非晶型氧化铟锡镀膜时使用的水或氢气会改变金属氧化物半导体材料层的特性，使得原本具有半导体特性的金属氧化物半导体材料层转成具导体特性的金属氧化物半导体材料层，进而造成薄膜晶体管的信道层的导通，并影响薄膜晶体管的电性表现以及可靠度。
发明内容
本发明提供一种像素结构的制造方法，其使得像素结构具有良好的电性表现以及可靠度。
本发明的像素结构的制造方法包括以下步骤。于基板上形成栅极。于基板上形成栅绝缘层，以覆盖栅极。于栅绝缘层上形成信道层，其中信道层的材料包括第一金属氧化物半导体材料。于信道层的相对两侧上形成源极与漏极。于基板上形成绝缘层，以覆盖源极、漏极及信道层，其中绝缘层具有暴露出漏极的开口。于基板上依序形成第一透明电极材料层及第二透明电极材料层，其中第一透明电极材料层的材料包括第二金属氧化物半导体材料，第二透明电极材料层的材料包括金属氧化物导电材料。利用同一掩模图案化第一透明电极材料层及第二透明电极材料层，以形成第一透明电极层及第二透明电极层，其中第一透明电极层通过开口与漏极接触。
基于上述，在本发明的像素结构的制造方法中，通过在形成绝缘层之后，依序形成材料包括金属氧化物半导体材料的第一透明电极材料层及材料包括金属氧化物导电材料的第二透明电极材料层，藉此使得材料包括金属氧化物半导体材料的信道层不会受到水或氢气的影响而特性改变。如此一来，由本发明的像素结构的制造方法所制得的像素结构具有良好的电性表现以及可靠度。
为让本发明的上述特征和优点能更明显易懂，下文特举实施方式，并配合附图作详细说明如下。
附图说明
图1A至图1G是依照本发明一实施方式的像素结构的制造方法的剖面示意图。
附图标记：
10：像素结构
100：基板
102：绝缘层
104：第一透明电极材料层
106：第二透明电极材料层
108：第一透明电极层
110：第二透明电极层
CH：信道层
D：漏极
G：栅极
GI：栅绝缘层
OP：开口
PE：像素电极
S：源极
TFT：薄膜晶体管
具体实施方式
图1A至图1G是依照本发明一实施方式的像素结构的制造方法的剖面示意图。
首先，请参照图1A，提供基板100。就光学特性而言，基板100可为透光基板或不透光/反射基板。透光基板的材质可选自玻璃、石英、有机聚合物、其他适当材料或其组合。不透光/反射基板的材质可选自导电材料、金属、晶圆、陶瓷、其他适当材料或其组合。需说明的是，基板100若选用导电材料时，则需在基板100搭载构件之前，于基板100上形成一绝缘层(未显示)，以避免基板100与构件之间发生短路的问题。
接着，于基板100上形成栅极G。详细而言，在本实施方式中，形成栅极G的方法包括：于基板100上使用溅镀制程形成一栅极材料层(未显示)后，对所述栅极材料层进行第一道微影蚀刻制程，其中微影蚀刻制程包括光阻涂布(photo resist coat)、曝光(exposure)、显影(develop)、蚀刻(etch)、剥膜(strip)等步骤。另外，在本实施方式中，基于导电性的考虑，栅极G的材料为金属材料，所述金属材料例如是钼、铝、钛、上述金属的合金或是上述至少二者材料的堆栈层。然而，本发明不限于此。在其他实施方式中，栅极G亦可以使用其他导电材料(例如：金属氮化物、金属氧化物、金属氮氧化物等)或是金属与其它导电材料的堆栈层。
接着，请参照图1B，于基板100上形成栅绝缘层GI，以覆盖栅极G。在本实施方式中，栅绝缘层GI可利用物理气相沉积法(physics vapor deposition，PVD)或化学气相沉积法(plasma enhanced chemical vapor deposition，CVD)全面性地沉积在基板100上，其中化学气相沉积法例如是等离子体辅助化学气相沉积法(plasma-enhanced chemical vapor deposition，PECVD)。另外，栅绝缘层GI的材料例如包括二氧化硅(SiO2)、氧化氮(SiNx)或其堆栈层。在本实施方式中，虽栅绝缘层GI是全面性覆盖栅极G与基板100，然本发明不限于此。
接着，请参照图1C，于栅绝缘层GI上形成信道层CH，其中信道层CH的材料包括金属氧化物半导体材料。详细而言，在本实施方式中，形成信道层CH的方法包括以下步骤：首先，于栅绝缘层GI上形成一信道材料层(未显示)，其中信道材料层的材料包括金属氧化物半导体材料，所述金属氧化物半导体材料例如是氧化铟镓锌(Indium-Gallium-Zinc Oxide，IGZO)或三氧化二铟(In2O3)，以及形成信道材料层的方法包括溅镀制程或涂布制程。接着，对所述信道材料层进行第二道微影蚀刻制程，其中微影蚀刻制程包括光阻涂布、曝光、显影、蚀刻、剥膜等步骤。
接着，请参照图1D，于信道层CH的相对两侧上形成源极S与漏极D。详细而言，源极S与漏极D彼此相分离且暴露出部分的信道层CH。
在本实施方式中，形成源极S与漏极D的方法包括：于基板100上使用溅镀制程形成一导电材料层(未显示)后，对所述导电材料层进行第三道微影蚀刻制程，其中微影蚀刻制程包括光阻涂布、曝光、显影、蚀刻、剥膜等步骤。另外，在本实施方式中，基于导电性的考虑，源极S与漏极D的材料为金属材料，所述金属材料例如是钼、铝、钛、上述金属的合金或是上述至少二者材料的堆栈层。然而，本发明不限于此。在其他实施方式中，源极S与漏极D亦可以使用其他导电材料(例如：金属氮化物、金属氧化物、金属氮氧化物等)或是金属与其它导电材料的堆栈层。
另外一提的是，在本实施方式中，栅极G、栅绝缘层GI、信道层CH、源极S与漏极D构成了一个薄膜晶体管TFT。具体而言，在本实施方式中，由于信道层CH的材料包括金属氧化物半导体材料，故薄膜晶体管TFT即为金属氧化物半导体薄膜晶体管。从另一观点而言，在本实施方式中，薄膜晶体管TFT属于背信道蚀刻型态。
接着，请参照图1E，于基板100上形成绝缘层102，以覆盖源极S、漏极D及信道层CH，其中绝缘层102具有开口OP，暴露出漏极D。详细而言，在本实施方式中，形成绝缘层102的方法包括以下步骤：首先，于基板100上全面性地形成一绝缘材料层(未显示)，其中绝缘材料层的材料包括二氧化硅或其他适合的绝缘材料，以及绝缘材料层可通过等离子体辅助化学气相沉积(PECVD)形成。接着，对所述绝缘材料层进行第四道微影蚀刻制程，以形成前述开口OP，其中微影蚀刻制程包括光阻涂布、曝光、显影、蚀刻、剥膜等步骤。另外，在本实施方式中，绝缘层102的厚度例如是介于至之间。
接着，请参照图1F，于基板100上依序形成第一透明电极材料层104及第二透明电极材料层106。详细而言，在本实施方式中，形成第一透明电极材料层104的方法包括溅镀制程或涂布制程，第一透明电极材料层104的材料包括金属氧化物半导体材料，所述金属氧化物半导体材料例如是氧化铟镓锌(IGZO)或三氧化二铟(In2O3)，以及第一透明电极材料层104的厚度介于至之间。更详细而言，当使用溅镀制程形成第一透明电极材料层104时，制程气体为氩气或氩气与氧气的混合气体。
值得说明的是，如前文所述，当使用溅镀制程形成第一透明电极材料层104时，制程气体只会用到氩气或氩气与氧气的混合气体，而不会用到水或是氢气。如此一来，不论是使用溅镀制程还是涂布制程来形成第一透明电极材料层104，过程中都不会存在会改变信道层CH(即金属氧化物半导体材料)的特性的水等离子体或是氢气等离子体。
另外，在本实施方式中，形成第二透明电极材料层106的方法包括溅镀制程，而第二透明电极材料层106的材料包括金属氧化物导电材料，所述金属氧化物导电材料例如是非晶型氧化铟锡(amorphous indium-tin oxide，a-ITO)。具体而言，当使用溅镀制程形成第二透明电极材料层106时，制程气体除了使用氩气或氩气与氧气的混合气体外，还使用了水或是氢气。
值得说明的是，如前文所述，虽然在使用溅镀制程形成第二透明电极材料层106的过程中会产生水等离子体或氢气等离子体，但由于第二透明电极材料层106是在第一透明电极材料层104之后形成，且第一透明电极材料层104与信道层CH之间至少还存在有绝缘层102，因此能够有效避免水等离子体或氢气等离子体对信道层CH(即金属氧化物半导体材料)造成影响，使得薄膜晶体管TFT不会有电性漂移的问题而具有良好的电性表现以及可靠度。另外一提的是，形成第二透明电极材料层106过程中所产生的水等离子体或氢气等离子体能够使第一透明电极材料层104中的金属氧化物半导体材料进行导体化，进而提升第一透明电极材料层104的导电能力。也就是说，通过形成第二透明电极材料层106过程中所产生的水等离子体或氢气等离子体，使得原本具有半导体特性的第一透明电极材料层104得以转成具导体特性的第一透明电极材料层104。
接着，请参照图1G，利用同一掩模图案化第一透明电极材料层104及第二透明电极材料层106，以形成第一透明电极108层及第二透明电极层110，其中第一透明电极层108通过开口OP与漏极D接触。详细而言，在本实施方式中，形成第一透明电极108层及第二透明电极层110的方法包括：对第一透明电极材料层104及第二透明电极材料层106进行第五道微影蚀刻制程，所述第五道微影蚀刻制程包括光阻涂布、曝光、显影、蚀刻、剥膜等步骤，其中光阻是涂布在第二透明电极材料层106上，曝光步骤是使用第五道掩模对涂布在第二透明电极材料层106上的光阻进行曝光，蚀刻步骤是一并对第一透明电极材料层104及第二透明电极材料层106进行蚀刻，且蚀刻液例如是草酸。
进一步而言，在本实施方式中，第一透明电极层108与第二透明电极层110是直接接触的，以及由于第一透明电极层108与第二透明电极层110是通过使用同一张掩模(即第五道掩模)而形成，故第一透明电极层108与第二透明电极层110具有相同的图案。换言之，在本实施方式中，第二透明电极层110完全覆盖第一透明电极层108。
另外，在本实施方式中，第一透明电极层108与第二透明电极层110一起构成与漏极D电性连接的像素电极PE。值得一提的是，如前文所述，形成第二透明电极材料层106过程中所产生的水等离子体或氢气等离子体能够使原本具有半导体特性的第一透明电极材料层104进行导体化，藉此提升了第一透明电极层108的导电能力，因而使得由第一透明电极层108与第二透明电极层110构成的像素电极PE具有良好的导电能力。
接着，在形成第一透明电极层108及第二透明电极层110后，还包括对第二透明电极层110进行结晶化制程。在本实施方式中，结晶化制程包括进行一高温处理，所述高温处理的温度约为150℃至300℃。详细而言，在本实施方式中，通过对第二透明电极层110进行结晶化制程，使得第二透明电极层110的结晶性更加良好，因而进一步提升第二透明电极层110的导电能力。另外，在本实施方式中，虽然在形成第一透明电极108层及第二透明电极层110后，有对第二透明电极层110进行结晶化制程，但本发明并不限于此。
基于上述，藉由进行上述所有步骤(图1A至图1G)后，便可完成本实施方式的像素结构10的制作。在上述实施方式中，像素结构10藉由五道微影蚀刻制程即可完成制作。值得说明的是，如前文所述，通过在形成绝缘层102之后，先形成制造过程中不会产生水等离子体或是氢气等离子体的第一透明电极材料层104，使得即使形成第二透明电极材料层106的过程中会产生水等离子体或氢气等离子体，仍能够有效避免水等离子体或氢气等离子体对信道层CH(即金属氧化物半导体材料)造成影响，进而使得薄膜晶体管TFT避免产生电性漂移的问题。如此一来，与已知像素结构相比，像素结构10能够具有良好的电性表现以及可靠度。
综上所述，在本发明的像素结构的制造方法中，通过在形成绝缘层之后，依序形成材料包括金属氧化物半导体材料的第一透明电极材料层及材料包括金属氧化物导电材料的第二透明电极材料层，藉此使得材料包括金属氧化物半导体材料的信道层不会受到水或氢气的影响而特性改变。如此一来，由本发明的像素结构的制造方法所制得的像素结构具有良好的电性表现以及可靠度。
虽然本发明已以实施方式揭示如上，然其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作些许的变动与润饰，故本发明的保护范围当视所附权利要求书界定的范围为准。

Claims (8)

1.一种像素结构的制造方法，其特征在于，包括：
于一基板上形成一栅极；
于所述基板上形成一栅绝缘层，以覆盖所述栅极；
于所述栅绝缘层上形成一信道层，其中所述信道层的材料包括第一金属氧化物半导体材料；
于所述信道层的相对两侧上形成一源极与一漏极；
于所述基板上形成一绝缘层，以覆盖所述源极、所述漏极及所述信道层，其中所述绝缘层具有一开口，所述开口暴露出所述漏极；
于所述基板上依序形成一第一透明电极材料层及一第二透明电极材料层，其中所述第一透明电极材料层的材料包括第二金属氧化物半导体材料，所述第二透明电极材料层的材料包括金属氧化物导电材料，形成所述第一透明电极材料层的方法包括溅镀制程或涂布制程，形成所述第二透明电极材料层的方法包括溅镀制程，且其中利用溅镀制程形成所述第一透明电极材料层时，制程气体为氩气或氩气与氧气的混合气体；以及
利用同一掩模图案化所述第一透明电极材料层及所述第二透明电极材料层，以形成一第一透明电极层及一第二透明电极层，其中所述第一透明电极层通过所述开口与所述漏极接触。
2.根据权利要求1所述的像素结构的制造方法，其特征在于，所述第一金属氧化物半导材料包括氧化铟镓锌或三氧化二铟。
3.根据权利要求1所述的像素结构的制造方法，其特征在于，所述第二金属氧化物半导材料包括氧化铟镓锌或三氧化二铟。
4.根据权利要求1所述的像素结构的制造方法，其特征在于，所述金属氧化物导电材料包括非晶型氧化铟锡。
5.根据权利要求1所述的像素结构的制造方法，其特征在于，所述第一透明电极层及所述第二透明电极层具有相同图案。
6.根据权利要求1所述的像素结构的制造方法，其特征在于，所述第一透明电极层与所述第二透明电极层直接接触。
7.根据权利要求1所述的像素结构的制造方法，其特征在于，还包括对第二透明电极层进行结晶化制程。
8.根据权利要求1所述的像素结构的制造方法，其特征在于，所述绝缘层的厚度介于至之间，所述第一透明电极材料层的厚度介于至之间。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102486917A (zh) * 2010-12-02 2012-06-06 三星电子株式会社 显示装置及其制造方法
CN104934447A (zh) * 2009-08-07 2015-09-23 株式会社半导体能源研究所 半导体装置及其制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US5429685A (en) * 1992-11-16 1995-07-04 Canon Kabushiki Kaisha Photoelectric conversion element and power generation system using the same
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KR101921164B1 (ko) * 2011-07-27 2018-11-23 엘지디스플레이 주식회사 횡전계방식 액정표시장치용 어레이기판의 제조방법
TWI469194B (zh) 2012-05-16 2015-01-11 Au Optronics Corp 有機電致發光裝置之畫素結構

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934447A (zh) * 2009-08-07 2015-09-23 株式会社半导体能源研究所 半导体装置及其制造方法
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