CN106915958B - 积层电子陶瓷元件及其无压共烧结制法 - Google Patents
积层电子陶瓷元件及其无压共烧结制法 Download PDFInfo
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Abstract
本发明公开了一种积层电子陶瓷元件及其无压共烧结制法,主要是将介电常数(k值)大于1500以上高介电常数陶瓷结层,及介电常数(k值)小于100的低介电常数陶瓷结构层交错积层形成积层电子陶瓷元件,并将积层电子陶瓷元件进行高温共烧处理。经烧结温度1150℃至1350℃和还原气氛(氧分压:10‑6~10‑12atm)环境下,所制作得的积层电子陶瓷元件,可具有高电容值、低介电损耗、高绝缘电阻、高绝缘破坏电压、温度稳定性佳与低扭曲特性的目的。
Description
技术领域
本发明涉及一种将高介电常数陶瓷材料(High permittivity dielectrics)与低介电常数陶瓷材料(Low permittivity dielectrics)于还原气氛下进行无压共烧结处理方式,尤指一种可得到理想的共烧匹配性与反应性,并减少组件电致伸缩性的积层电子陶瓷元件及其无压共烧结制法。
背景技术
由于不同材料系统具有其不同的本质特性,如何在将个别优势整合于组件特性上,将不同材料系统通过“共烧”方式(Co-firing)进行结合,便成为一重要的关键技术。
如中国台湾专利563271中,即利用磁性材料(氧化铁)及非磁性材料(玻璃)共烧,藉由不同材料的电性提供共模滤波器不同部分的电性需求,改善不同滤波器型式的电气特性。
美国专利4746557中,则将磁性生胚薄带(Magnetic Green Sheet)所形成的电感及介电生胚薄带(Dielectric Green Sheet)所形成的电容同时设计于一组件中,于800℃~1000℃温度下将具电感与电容特性的材料共烧结,整合出一兼具电感(Inductor)及电容(Capacitor)特性的组件。
中国台湾专利I367504中,则提到一高度整合的芯片压敏电阻器制作方式,该电阻器主要系将功能性薄片制作于绝缘陶瓷基体上,其中所提及的功能性薄片包含介电陶瓷材料、压电陶瓷材料、磁性陶瓷材料半导体材料等,利用绝缘陶瓷基体进行抛光以形成复数沟槽来增进界面处的接合强度,提升异质陶瓷共烧的效果。
除了前述提及不同组成与特性的陶瓷材料间的共烧专利技术外,强调具低温共烧特性(共烧温度<950℃)的专利亦相当多,例如美国专利5144526中,使用了以低介电陶瓷材料为主的结构设计,并于组件结构中插入一层高介电陶瓷材料进行低温共烧(LTCC)所实现的电容器组件。中国台湾专利428300,是藉由低介电陶瓷材料包覆高介电陶瓷材料搭配不同电极型式的设计来制作被动组件。
而美国杜邦公司也采用不同高、低介电陶瓷材料的概念来进行共烧,并提出一系列专利,在其美国专利6827800及中国台湾专利I226319中,主要带(Primary Tape)中加入内部局限带(Constraining Layer),同时在表层某一端加入一释放层(Release Layer)已产生能使x、y方向的收缩互相抑制的结构,其中主要带的介电常数介于6~10之间,而内部局限带介电常数则介于10~5000之间。
此外,其美国专利7068492、7067026及中国台湾专利I277512、I308106、I280955中,使用高介电材料的介电常数大于8以上,而低介电材料则为低于8以下,且将主要带的介电常数修正至7~9之间,并说明同时采用三个或三个以上不同介电材料薄带来达到平坦、无畸变、零收缩的陶瓷组件或复合物或模块或封装的制作方法。该公司于美国专利20060162844及中国台湾专利I278879中,再进一步针对使用的介电材料特性进行修正,于前述设计的主要带与内部局限带中插入一高介电常数带结构进行电容器的共烧,其中所采用的高介电常数带的介电常数至少要20,所使用的高、低介电材料的k值范围均低于250以下,上述杜邦公司专利均采用低温共烧的方式进行,即烧结温度低于950℃。美国专利7141129中,则提到采用介电材料的k值范围大于2000,且低介电材料的K值范围依然小于20的共烧技术,但该专利依然是属于低温共烧的技术范畴。
然而,考虑现今积层电子陶瓷组件(如积层陶瓷电容器)的制造技术与材料成本,高温式(>1100℃)的还原气氛烧结制程仍属主流。故,如何将上述共烧概念导入现行的烧结制程中,使得所制作的组件具有更多元特性,即为本领域所欲解决的课题。
发明内容
为解决上述公知技术中存在的问题,本发明的目的之一是在于提供一种将高介电常数陶瓷材料与低介电常数陶瓷材料于还原气氛下进行无加压共烧结(Non-constrainedsintering)处理方式,以得到理想的共烧匹配性与反应性的积层电子陶瓷元件及其无压共烧结制法。
为解决上述公知技术中存在的问题,本发明的另一目的是在于提供一种可保持高介电常数陶瓷材料的高电容值介电特性,并利用低介电常数陶瓷材料的低压电与低散逸系数特性的优点,同时减少元件电致伸缩性的积层电子陶瓷元件及其无压共烧结制法。
为解决上述公知技术中存在的问题,本发明的又一目的是在于提供一种具低介电损耗、高绝缘电阻、高绝缘破坏电压及温度稳定性佳的积层电子陶瓷元件及其无压共烧结制法。
为达成上述目的,本发明积层电子陶瓷元件及其无压共烧结制法通过材料组成结构的选择与共烧制程参数控制,使得高/低介电常数陶瓷材料,可于还原气氛下(氧分压:10-12~10-20atm)进行无压共烧制作,工作温度大于等于1150℃。
其中,高介电常数陶瓷材料的k值>1500;低介电常数陶瓷材料的K值<100。同时,透过交错积层设计,使用高介电常数陶瓷材料或低介电常数陶瓷材料,作为积层电子陶瓷元件的反应层或覆盖层结构,形成同时具有高介电常数陶瓷材料及低介电常数陶瓷材料的积层电子陶瓷元件,其结构内部电极则采用镍金属。
本发明的积层电子陶瓷元件及其无压共烧结制法,提供一种可于还原气氛下高温无压共烧的介电陶瓷组成物与制法,是利用钙钛矿结构(Perovskite)材料系间彼此晶格结构形貌相近,高温作用下交互反应性较佳,形成反应结构,提高不同材料组成物间共烧的异质介面的束缚性。
其中,高介电常数陶瓷材料主要为钛酸钡基(BaTiO3-based)的强介电性材料为主体,其Ba/Ti的摩尔比介于0.99~1.06之间,粉体粒径大小(D50)范围则在0.1至0.5μm之间,并加入多种氧化物添加剂,使得此材料组成物可于还原气氛下烧结,烧结后材料介电常数大于1000。
氧化物添加剂组成,以主相钛酸钡使用重量为100重量%为基础,其包含:0.32~2.70wt%碳酸钡(BaCO3)、0~0.06wt%三氧化钼(MoO3)、0.20~0.55wt%二氧化硅(SiO2)、0.17~0.72wt%氧化钇(Y2O3)、0.04~0.34wt%氧化镁(MgO)、0~0.07wt%五氧化二铌(Nb2O5)、0.11~0.28wt%碳酸锰(MnCO3)、0~1.61wt%氧化镱(Yb2O3)、0~0.51wt%氧化铝(Al2O3)、0~0.50wt%碳酸钙(CaCO3)、0~0.21wt%二氧化锆(ZrO2)、0~0.05wt%三氧化二钐(Sm2O3)、0~0.28wt%氧化镝(Dy2O3)、0~0.10wt%二氧化钛(TiO2)、0~0.04wt%五氧化二钒(V2O5)、0~0.13wt%碳酸锶(SrCO3)及0~0.23wt%一氧化锡(SnO)。并可利用上述氧化物添加剂组态与主相粉体粒径大小,控制介电特性及其所需的共烧结温度与气氛环境。
较佳者,上述氧化物添加剂组成,其包含:0.32~2.70wt%碳酸钡(BaCO3)、0.001~0.06wt%三氧化钼(MoO3)、0.20~0.55wt%二氧化硅(SiO2)、0.17~0.72wt%氧化钇(Y2O3)、0.04~0.34wt%氧化镁(MgO)、0.001~0.07wt%五氧化二铌(Nb2O5)、0.11~0.28wt%碳酸锰(MnCO3)、0.001~1.61wt%氧化镱(Yb2O3)、0.001~0.51wt%氧化铝(Al2O3)、0.001~0.50wt%碳酸钙(CaCO3)、0.001~0.21wt%二氧化锆(ZrO2)、0.001~0.05wt%三氧化二钐(Sm2O3)、0.001~0.28wt%氧化镝(Dy2O3)、0.001~0.10wt%二氧化钛(TiO2)、0.001~0.04wt%五氧化二钒(V2O5)、0.001~0.13wt%碳酸锶(SrCO3)及0.001~0.23wt%一氧化锡(SnO)。
其中,低介电常数陶瓷材料均是以常介电陶瓷材料为主体,介电常数低于100,但具优越低介电损耗(Low Dissipation Factor,DF<0.1%)及稳定的温度介电特性(Temperature-Capacitance Coefficient,△C/C≦1000ppm in-55℃~125℃),为使得此材料具有可还原气氛下烧结特性,并加入适当添加剂成份。
低介电常数陶瓷材料粉体粒径大小(D50)范围则在0.3至0.6μm之间,包含:21.42~35.85wt%碳酸钙(CaCO3)、0~21.31wt%碳酸锶(SrCO3)、0~7.97wt%碳酸钡(BaCO3)、0~11.20wt%氧化镁(MgO)、1.36~14.86wt%二氧化钛(TiO2)、6.74~51.30wt%二氧化锆(ZrO2)、0~5.83wt%氧化锌(ZnO)、0~1.30wt%碳酸锰(MnCO3)、0.59~26.58wt%二氧化硅(SiO2)、0.16~1.53wt%二氧化铪(HfO2)、0~0.11wt%五氧化二钽(Ta2O5)、0~0.12wt%氧化钇(Y2O3)及0~0.18wt%氧化铝(Al2O3)。并可通过上述材料组成变化与粉体粒径大小,调整介电特性、烧结温度与所适合的烧结气氛环境条件。
较佳者,上述低介电常数陶瓷材料,其包含:21.42~35.85wt%碳酸钙(CaCO3)、0.001~21.31wt%碳酸锶(SrCO3)、0.001~7.97wt%碳酸钡(BaCO3)、0.001~11.20wt%氧化镁(MgO)、1.36~14.86wt%二氧化钛(TiO2)、6.74~51.30wt%二氧化锆(ZrO2)、0.001~5.83wt%氧化锌(ZnO)、0.001~1.30wt%碳酸锰(MnCO3)、0.59~26.58wt%二氧化硅(SiO2)、0.16~1.53wt%二氧化铪(HfO2)、0.001~0.11wt%五氧化二钽(Ta2O5)、0.001~0.12wt%氧化钇(Y2O3)及0.001~0.18wt%氧化铝(Al2O3)。
接着,以高介电常数陶瓷材料及低介电常数陶瓷材料作为基础,以镍金属或其合金作为电极,分别制作成高介电常数陶瓷层、高介电常数电极层(即已涂布金属电极的高介电常数陶瓷层)、低介电常数陶瓷层与低介电常数电极层(即已涂布金属电极低介电常数陶瓷层)。
接着,藉由高介电常数陶瓷结构层与低介电常数陶瓷结构层组成元件内部反应层,此两种结构层的交错积层设计可为对称式或非对称式。此反应层中,高介电常数陶瓷结构层与低介电常数陶瓷结构层至少存在一种。
上述高介电常数陶瓷层及高介电常数电极层是组成有高介电常数陶瓷结构层,上述的低介电常数陶瓷层及低介电常数电极层是组成有低介电常数陶瓷结构层。
其中,高介电常数陶瓷结构层中通过高介电常数电极层的交错积层设计,达到电容特性。并利用电极间交错面积大小,与控制电极间高介电常数陶瓷层厚度,进而达到调控电容值的目的。其中,电极图样形式可为连续式、非连续式或浮动式等。高介电常数陶瓷结构层,亦可全为陶瓷层。在此高介电常数陶瓷层与高介电常数电极层的高介电常数陶瓷基材,可为在单一烧结条件下处理的相同或相近组成物成分。
其中,低介电常数陶瓷结构层中通过低介电常数电极层的交错积层设计,达到电容特性。并利用电极间交错面积大小,与控制电极间低介电常数陶瓷层厚度,进而达到调控电容值的目的。其中,电极图样形式可为连续式、非连续式或浮动式等。此低介电常数陶瓷结构层,亦可全为陶瓷层。在此低介电常数陶瓷层与低介电常数电极层的低介电常数陶瓷基材,可为在单一烧结条件下处理的相同或相近组成物成分。
其中,高介电常数陶瓷层、高介电常数电极层、低介电常数陶瓷层与低介电常数电极层,可为相同或不相同的厚度尺寸。
其中,高介电常数陶瓷结构层中电极厚度与低介电常数陶瓷结构层中电极层的电极厚度,亦可为相同或不相同的厚度尺寸,且各电极层厚度皆需小于或等于对应的高介电常数陶瓷结构层与低介电常数陶瓷结构层厚度。
上述覆盖层结构为低介电常数陶瓷层或高介电常数陶瓷层中至少一种,上及下两面覆盖层的厚度与组成上,可为相同或不相同,所述覆盖层的厚度至少大于30μm。且覆盖层的陶瓷材料组成与反应层的陶瓷材料组成,可为相同或不相同。
又,上述各结构层间的结合区,可通过相同或不同的陶瓷层,或陶瓷层与电极层相互接合进行烧结,作为共烧反应结合界面。
此外,本发明是通过下述方式进行无压共烧结制作,进而将两种或两种以上材料系统于还原气氛下共烧,并实现于元件制作。此共烧结制法流程如下:
首先,将根据前述完成积层结构的电容器元件本体,以温度T1进行预烧除制程;其后将预烧除后的电容器元件本体,以高于温度T1的温度T2进行烧除制程,上述气氛控制在10-6~10-12atm氧分压;接着,持续将温度升高至T3,同时通入湿气(水蒸气)、氢或氮混合气,控制于还原气氛(10-12~10-20atm氧分压)下,进行异质材料间的烧结(Sintering)制程;最终,将烧结温度调降至温度T4,并通入湿气(水蒸气)、氮与氧混合气,控制于氧分压10-7~10-15atm下,以进行再氧化(Re-oxidation)制程,其中T3>T4>T2≥T1,且此高温共烧曲线可于还原气氛下进行。其中,前述所提及的预烧除及烧除制程的温度T1和T2是以200℃~900℃的温度进行,预烧除及烧除制程可分别或合并进行;烧结制程的温度T3范围则是在1150℃~1350℃间;而再氧化制程的温度T4范围则落在950℃~1150℃之间。同时各制程的升、降温速率需控制在1.5℃/min~15℃/min范围内。
附图说明
图1A为本发明高介电常数陶瓷结构层的无压共烧结制法的流程图;
图1B为步骤S02的详细流程图;
图2为本发明高介电常数陶瓷结构层的示意图;
图3为本发明低介电常数陶瓷结构层的示意图;
图4为本发明积层电子陶瓷元件的示意图;
图5A为镍金属电极层连续印刷示意图;
图5B为镍金属电极层不连续印刷示意图;
图5C为镍金属电极层浮动印刷示意图。
其中:S01~S02为无压共烧结制法的步骤流程;S021~S024为步骤S02的步骤流程;100-第一覆盖层;200-第二覆盖层;300-反应层;400-镍金属电极层;500-介电常数陶瓷结构层;501-高介电常数陶瓷层;502-高介电常数电极层;600-低介电常数陶瓷结构层;601-低介电常数陶瓷层;602-低介电常数电极层。
具体实施方式
以下将描述具体实施例以说明本发明的实施态样,但其并不能用以限制本发明所要保护的范畴。
请参阅图1A~1B,本发明积层电子陶瓷元件的无压共烧结制法,其流程包括:
S01:将k值(介电常数)大于1500以上高介电常数陶瓷结构层及k值小于100的低介电常数陶瓷结构层交错积层形成积层电子陶瓷元件;
S02:将积层电子陶瓷元件于还原气氛10-6~10-20atm环境下进行温度1150℃~1350℃无压烧结。
其中,将积层电子陶瓷元件于还原气氛10-6~10-20atm环境下进行烧结,其流程包括:
S021:将积层电子陶瓷元件以200℃~900℃进行预烧除;
S022:将预烧除后的积层电子陶瓷元件于还原气氛10-6~10-12atm环境,并高于预烧除的温度进行烧除;
S023:将温度提高至1150℃~1350℃,同时通入湿气(水蒸气)、氮及氢混合气,并于还原气氛10-12~10-20atm环境下,进行异质材质间的烧结制作;
S024:将温度调降至950℃~1150℃,并通入湿气(水蒸气)、氮及氢混合气,于还原气氛10-7~10-15atm环境下进行再氧化制程。
上述高介电常数陶瓷结构层是利用高介电常数陶瓷材料制作而成,以下举例说明高介电常数陶瓷材料的组成及高介电常数陶瓷结构层的制作方法:
实施例1-1:高介电常数陶瓷材料的组成包括主相材料与氧化物添加剂,介电常数(以下称为k值)为4500。主相材料为BaTiO3,Ba/Ti的摩尔比=0.99,粉体粒径大小(D50)为0.5μm,氧化物添加剂组成(以主相BaTiO3使用重量为100重量%为基础),包括:BaCO3(碳酸钡):1.22重量%、MoO3(三氧化钼):0.05重量%、SiO2(二氧化硅):0.46重量%、Y2O3(氧化钇):0.34重量%、MgO(氧化镁):0.2重量%、Nb2O5(五氧化二铌):0.05重量%、MnCO3(碳酸锰):0.13重量%、Al2O3(氧化铝):0.22重量%、ZrO2(二氧化锆):0.04重量%。
将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出厚度为2~5μm的高介电常数陶瓷层,接着,再于高介电常数陶瓷层上印刷镍金属电极以形成高介电常数陶瓷电极层。
实施例1-2:高介电常数陶瓷材料的组成包括主相材料与氧化物添加剂,k值为2200。主相材料为BaTiO3,Ba/Ti的摩尔比为1.03,粉体粒径大小(D50)为0.3μm,氧化物添加剂组成(以主相BaTiO3使用重量为100重量%为基础),包括:BaCO3(碳酸钡):2.27重量%、MoO3(三氧化钼):0.05重量%、SiO2(二氧化硅):0.55重量%、Y2O3(氧化钇):0.3重量%、MgO(氧化镁):0.2重量%、Nb2O5(五氧化二铌):0.07重量%、MnCO3(碳酸锰):0.11重量%、Yb2O3(氧化镱):0.49重量%、Sm2O3(三氧化二钐):0.03重量%、Dy2O3(氧化镝):0.18重量%。
将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出厚度为2~5μm的高介电常数陶瓷层,接着,再于高介电常数陶瓷层上印刷镍金属电极以形成高介电常数陶瓷电极层。
实施例1-3:高介电常数陶瓷材料的组成包括主相材料与氧化物添加剂,k值为4000。主相材料为BaTiO3,Ba/Ti的摩尔比=1.03,粉体粒径大小(D50)为0.4μm,氧化物添加剂组成(以主相BaTiO3使用重量为100重量%为基础),包括:BaCO3(碳酸钡):0.99重量%、MoO3(三氧化钼):0.06重量%、SiO2(二氧化硅):0.49重量%、Y2O3(氧化钇):0.67重量%、MgO(氧化镁):0.2重量%、Nb2O5(五氧化二铌):0.06重量%、MnCO3(碳酸锰):0.13重量%、Yb2O3(氧化镱):0~0.33重量%、Al2O3(氧化铝):0.42重量%、ZrO2(二氧化锆):0.15重量%、Dy2O3(氧化镝):0.12重量%、TiO2(二氧化钛):0.1重量%。
将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出厚度为2~5μm的高介电常数陶瓷层,接着,再于高介电常数陶瓷层上印刷镍金属电极以形成高介电常数陶瓷电极层。
实施例1-4:高介电常数陶瓷材料的组成包括主相材料与氧化物添加剂,k值为3300。主相材料为BaTiO3,Ba/Ti的摩尔比=1.05,粉体粒径大小(D50)为0.35μm,氧化物添加剂组成(以主相BaTiO3使用重量为100重量%为基础),包括:BaCO3(碳酸钡):0.82重量%、MoO3(三氧化钼):0.03重量%、SiO2(二氧化硅):0.22重量%、Y2O3(氧化钇):0.17重量%、MgO(氧化镁):0.04重量%、MnCO3(碳酸锰):0.28重量%、Yb2O3(氧化镱):0.82重量%、Al2O3(氧化铝):0.17重量%。
将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出厚度为2~5μm的高介电常数陶瓷层,接着,再于高介电常数陶瓷层上印刷镍金属电极以形成高介电常数陶瓷电极层。
实施例1-5:高介电常数陶瓷材料的组成包括主相材料与氧化物添加剂,k值为2500。主相材料为BaTiO3,Ba/Ti的摩尔比=0.99,粉体粒径大小(D50)为0.25μm,氧化物添加剂组成(以主相BaTiO3使用重量为100重量%为基础),包括:BaCO3(碳酸钡):1.81重量%、MoO3(三氧化钼):0.04重量%、SiO2(二氧化硅):0.43重量%、Y2O3(氧化钇):0.44重量%、MgO(氧化镁):0.08重量%、Nb2O5(五氧化二铌):0.06重量%、MnCO3(碳酸锰):0.27重量%、Yb2O3(氧化镱):1.6重量%、Al2O3(氧化铝):0.22重量%、CaCO3(碳酸钙):0.12重量%、ZrO2(二氧化锆):0.15重量%。
将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出厚度为2~5μm的高介电常数陶瓷层,接着,再于高介电常数陶瓷层上印刷镍金属电极以形成高介电常数陶瓷电极层。
实施例1-6:高介电常数陶瓷材料的组成包括主相材料与氧化物添加剂,k值为2000。主相材料为BaTiO3,Ba/Ti的摩尔比=1.03,粉体粒径大小(D50)为0.15μm,氧化物添加剂组成(以主相BaTiO3使用重量为100重量%为基础),包括:BaCO3(碳酸钡):1.19重量%、MoO3(三氧化钼):0.06重量%、SiO2(二氧化硅):0.48重量%、Y2O3(氧化钇):0.44重量%、MgO(氧化镁):0.2重量%、Nb2O5(五氧化二铌):0.06重量%、MnCO3(碳酸锰):0.13重量%、Yb2O3(氧化镱):1.03重量%、Al2O3(氧化铝):0.51重量%、CaCO3(碳酸钙):0.5重量%。
将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出厚度为2~5μm的高介电常数陶瓷层,接着,再于高介电常数陶瓷层上印刷镍金属电极以形成高介电常数陶瓷电极层。
实施例1-7:高介电常数陶瓷材料的组成包括主相材料与氧化物添加剂,k值为3500。主相材料为BaTiO3,Ba/Ti的摩尔比=1.06,粉体粒径大小(D50)为0.35μm,氧化物添加剂组成(以主相BaTiO3使用重量为100重量%为基础),包括:BaCO3(碳酸钡):1.06重量%、MoO3(三氧化钼):0.03重量%、SiO2(二氧化硅):0.25重量%、Y2O3(氧化钇):0.72重量%、MgO(氧化镁):0.34重量%、Nb2O5(五氧化二铌):0.05重量%、MnCO3(碳酸锰):0.19重量%、Al2O3(氧化铝):0.2重量%、ZrO2(二氧化锆):0.21重量%、V2O5(五氧化二钒):0.04重量%、SrCO3(碳酸锶):0.12重量%。
将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出厚度为2~5μm的高介电常数陶瓷层,接着,再于高介电常数陶瓷层上印刷镍金属电极以形成高介电常数陶瓷电极层。
实施例1-8:高介电常数陶瓷材料的组成包括主相材料与氧化物添加剂,k值为2400。主相材料为BaTiO3,Ba/Ti的摩尔比=1.06,粉体粒径大小(D50)为0.25μm,氧化物添加剂组成(以主相BaTiO3使用重量为100重量%为基础),包括:BaCO3(碳酸钡):0.32重量%、SiO2(二氧化硅):0.2重量%、Y2O3(氧化钇):0.23重量%、MgO(氧化镁):0.13重量%、Nb2O5 (五氧化二铌):0.02重量%、MnCO3(碳酸锰):0.19重量%、Yb2O3(氧化镱):1.31重量%、Al2O3(氧化铝):0.21重量%、SnO(一氧化锡):0.23重量%。
将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出厚度为2~5μm的高介电常数陶瓷层,接着,再于高介电常数陶瓷层上印刷镍金属电极以形成高介电常数陶瓷电极层。
实施例1-9:高介电常数陶瓷材料的组成包括主相材料与氧化物添加剂,k值为3400。主相材料为BaTiO3,Ba/Ti的摩尔比=1.06,粉体粒径大小(D50)为0.35μm,氧化物添加剂组成(以主相BaTiO3使用重量为100重量%为基础),包括:BaCO3(碳酸钡):0.74重量%、MoO3(三氧化钼):0.02重量%、SiO2(二氧化硅):0.25重量%、Y2O3(氧化钇):0.23重量%、MgO(氧化镁):0.1重量%、Nb2O5(五氧化二铌):0.03重量%、MnCO3(碳酸锰):0.25重量%、Yb2O3(氧化镱):0.17重量%、Al2O3(氧化铝):0.21重量%、ZrO2(二氧化锆):0.12重量%、SrCO3(碳酸锶):0.13重量%。
将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出厚度为2~5μm的高介电常数陶瓷层,接着,再于高介电常数陶瓷层上印刷镍金属电极以形成高介电常数陶瓷电极层。
实施例1-10:高介电常数陶瓷材料的组成包括主相材料与氧化物添加剂,k值为2950。主相材料为BaTiO3,Ba/Ti的摩尔比=1.01,粉体粒径大小(D50)为0.45μm,氧化物添加剂组成(以主相BaTiO3使用重量为100重量%为基础),包括:BaCO3(碳酸钡):2.70重量%、MoO3(三氧化钼):0.04重量%、SiO2(二氧化硅):0.48重量%、Y2O3(氧化钇):0.54重量%、MgO(氧化镁):0.04重量%、MnCO3(碳酸锰):0.25重量%、Sm2O3(三氧化二钐):0.05重量%、Dy2O3(氧化镝):0.28重量%。
将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出厚度为2~5μm的高介电常数陶瓷层,接着,再于高介电常数陶瓷层上印刷镍金属电极以形成高介电常数陶瓷电极层。
上述之高介电常数陶瓷结构层是利用高介电常数陶瓷材料制作而成,以下举例说明低介电常数陶瓷材料的组成及低介电常数陶瓷结构层的制作方法:
实施例2-1:低介电常数陶瓷材料的组成包括共同相材料与其他氧化物添加剂,k值为10,将低介电常数陶瓷材料总重量订为100重量%,先将共同相材料:CaCO3(碳酸钙):11.38重量%、MgO(氧化镁):0.05重量%、TiO2(二氧化钛):10.07重量%、ZrO2(二氧化锆):6.74重量%、HfO2(二氧化铪):0.15重量%,加入于水中并添加分散剂,充分搅拌后干燥,再于1100℃~1350℃下煅烧成相,共同相材料的粉体粒径大小(D50)范围控制在0.33μm。并于共同相材料中添加其他氧化物添加剂,氧化物添加剂成份如下:BaCO3(碳酸钡):7.97重量%、CaCO3(碳酸钙):19.65重量%、MgO(氧化镁):11.15重量%、ZnO(氧化锌):5.83重量%、SiO2(二氧化硅):26.58重量%、Al2O3(氧化铝):0.18重量%。将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出低介电常数陶瓷层,低介电常数陶瓷层厚度为3~6μm。
实施例2-2:低介电常数陶瓷材料的组成包括共同相材料与氧化物添加剂,k值为30,将低介电常数陶瓷材料总重量订为100重量%,先将共同相材料:CaCO3(碳酸钙):22.05重量%、SrCO3(碳酸锶):20.4重量%、MgO(氧化镁):0.07重量%、TiO2(二氧化钛):1.36重量%、ZrO2(二氧化锆):51.3重量%、HfO2(二氧化铪):1.53重量%,加入于水中并添加分散剂,充分搅拌后干燥,再于1100℃~1350℃下煅烧成相,共同相材料的粉体粒径大小(D50)范围控制在0.34μm。并于共同相材料中添加氧化物添加剂,氧化物添加剂成份如下:BaCO3(碳酸钡):1.21重量%、MnCO3(碳酸锰):0.67重量%、SiO2(二氧化硅):1.41重量%。将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出低介电常数陶瓷层,低介电常数陶瓷层厚度为3~6μm。
实施例2-3:低介电常数陶瓷材料的组成包括共同相材料与氧化物添加剂,k值为31,将低介电常数陶瓷材料总重量订为100重量%,先将共同相材料:CaCO3(碳酸钙):21.42重量%、SrCO3(碳酸锶):21.31重量%、MgO(氧化镁):0.91重量%、TiO2(二氧化钛):1.69重量%、ZrO2(二氧化锆):50.15重量%、HfO2(二氧化铪):1.23重量%,加入于水中并添加分散剂,充分搅拌后干燥,再于1100℃~1350℃下煅烧成相,共同相材料的粉体粒径大小(D50)范围控制在0.41μm。并于共同相材料中添加氧化物添加剂,氧化物添加剂成份如下:MnCO3(碳酸锰):0.9重量%、SiO2(二氧化硅):1.91重量%、Ta2O5(五氧化二钽):0.11重量%、Y2O3(氧化钇):0.1重量%。将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出低介电常数陶瓷层,低介电常数陶瓷层厚度为3~6μm。
实施例2-4:低介电常数陶瓷材料的组成包括共同相材料与氧化物添加剂,k值为65,将低介电常数陶瓷材料总重量订为100重量%,先将共同相材料:CaCO3(碳酸钙):21.97重量%、SrCO3(碳酸锶):20.32重量%、TiO2(二氧化钛):11.16重量%、ZrO2(二氧化锆):43.5重量%、HfO2(二氧化铪):0.97重量%,加入于水中并添加分散剂,充分搅拌后干燥,再于1100℃~1350℃下煅烧成相,共同相材料的粉体粒径大小(D50)范围控制在0.51μm。并于共同相材料中添加氧化物添加剂,氧化物添加剂成份如下:MnCO3(碳酸锰):1.14重量%、SiO2(二氧化硅):0.94重量%。将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出低介电常数陶瓷层,低介电常数陶瓷层厚度为3~6μm。
实施例2-5:低介电常数陶瓷材料的组成包括共同相材料与氧化物添加剂,k值为70,将低介电常数陶瓷材料总重量订为100重量%,先将共同相材料:CaCO3(碳酸钙):35.85重量%、MgO(氧化镁):0.15重量%、TiO2(二氧化钛):14.86重量%、ZrO2(二氧化锆):45.98重量%、HfO2(二氧化铪):1.15重量%,加入于水中并添加分散剂,充分搅拌后干燥,再于1100℃~1350℃下煅烧成相,共同相材料的粉体粒径大小(D50)范围控制在0.54μm。并于共同相材料中添加氧化物添加剂,氧化物添加剂成份如下:MnCO3(碳酸锰):1.3重量%、SiO2(二氧化硅):0.59重量%、Y2O3(氧化钇):0.12重量%。将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出低介电常数陶瓷层,低介电常数陶瓷层厚度为3~6μm。
实施例2-6:低介电常数陶瓷材料的组成包括共同相材料与氧化物添加剂,k值为81,将低介电常数陶瓷材料总重量订为100重量%,先将共同相材料:CaCO3(碳酸钙):23.21重量%、SrCO3(碳酸锶):20.98重量%、TiO2(二氧化钛):14.15重量%、ZrO2(二氧化锆):38.16重量%、HfO2(二氧化铪):1.02重量%,加入于水中并添加分散剂,充分搅拌后干燥,再于1100℃~1350℃下煅烧成相,共同相材料的粉体粒径大小(D50)范围控制在0.56μm。并于共同相材料中添加氧化物添加剂,氧化物添加剂成份如下:MnCO3(碳酸锰):1.29重量%、SiO2(二氧化硅):1.19重量%。将上述组成物于有机溶剂(甲苯与醇类混和溶剂)中搭配适量分散剂(阴离子型界面活性剂),经研磨分散后,加入黏结剂(聚乙烯醇缩丁醛类树脂)与塑化剂(邻苯二甲酸酯类或磷酸酯类)充分搅拌形成陶瓷浆料,经涂布成型制作出低介电常数陶瓷层,低介电常数陶瓷层厚度为3~6μm。
此外,以上所述仅为本发明较佳的实施态样,并不能用以限定本发明的实施范围,凡依本发明申请专利范围及发明说明书内容所揭示的技术思想而为之简单的等效变化与修饰,皆应仍属本发明专利涵盖范围内,如BaO的起始物可为BaCO3,BaC2O4、Ba(C2H5OO)2等;Mn2CO3的起始物可为MnO2等。
接着,将上述制作方式所得到高介电常数陶瓷层、高介电常数电极层、低介电常数陶瓷层与低介电常数电极层,利用不同交错积层组合来制作积层电子陶瓷元件其中包括:至少一覆盖层、至少一反应层及至少一镍金属电极层。其中,覆盖层为高介电常数陶瓷层或低介电常数陶瓷层,反应层交错积层于覆盖层之间或覆盖层一侧,反应层为高介电常数陶瓷结构层或低介电常数陶瓷结构层,镍金属电极层位于反应层交错积层位置。
请参阅图2~5C,上述积层电子陶瓷元件主要包括第一覆盖层100、第二覆盖层200、交错积层于第一覆盖层100与第二覆盖层200间的反应层300以及位于反应层300交错积层位置的镍金属电极层400,第一覆盖层100为高介电常数陶瓷层501或低介电常数陶瓷层601,第二覆盖层为高介电常数陶瓷层501或低介电常数陶瓷层601,反应层300为高介电常数陶瓷结构层500、低介电常数陶瓷结构层600或包含高介电常数陶瓷结构层500及低介电常数陶瓷结构层600。
表一
请配合参阅表一,为积层电子陶瓷元件之第一覆盖层、第二覆盖层及反应层之交错积层结构类型表,其中,高介电常数陶瓷结构层500包括高介电常数陶瓷层501及高介电常数电极层502,低介电常数陶瓷结构层600包括低介电常数陶瓷层601及低介电常数电极层602,高介电常数电极层502为表面印刷有镍金属电极层400的高介电常数陶瓷层501,低介电常数电极层602为表面印刷有镍金属电极层400的低介电常数陶瓷层601,且镍金属电极层601为连续、不连续或浮动印刷。
其中,叠层型式X型的结构是第一覆盖层100及第二覆盖层200为高介电常数陶瓷层501,反应层300为交错积层的高介电常数陶瓷结构层500。
其中,叠层型式A型的结构是第一覆盖层100为高介电常数陶瓷层501,第二覆盖层200为低介电常数陶瓷层601,反应层300为交错积层的高介电常数陶瓷结构层500。
其中,叠层型式B型的结构是第一覆盖层100及第二覆盖层200为低介电常数陶瓷层600,反应层300为交错积层的高介电常数陶瓷结构层500。
其中,叠层型式C型及D型的结构是第一覆盖层100及第二覆盖层200为低介电常数陶瓷层600,反应层300为高介电常数陶瓷结构层500与低介电常数陶瓷结构层600交错积层。
上述第一覆盖层100、第二覆盖层200及反应层300的交错积层后,通过端电极膏沾附(Dipping)、烧附(Curing)、电镀(Plating)等制程完成元件端电极,并量测元件特性差异,通过不同介电材料成份与元件交错积层结构,经烧结所得到的电性所示。相较于单一材料的积层电容元件(见表二-叠层形式为X者),整合不同两种材料的积层电容元件,在电气特性上,除可维持相同的电容值水准外,在散逸系数、绝缘电阻、破坏电压与压电特性(电致伸缩性)上,通过不同的叠层设计,皆有明显的提升。并将经由共烧结制作的元件通过超音波显微镜(Scanning Acoustic Microscopy)分析(如表二所示),以每组条件3000颗元件取样数进行元件结构缺陷观察,结果发现皆无内部缺陷存在,故通过本发明将两种或两种以上材料系统于还原气氛下共烧,并可完全实现于电子陶瓷元件制作。
共烧结温度(℃) | 叠层形式 | 电容值(uF) | 散逸系数(%) | 绝缘电阻(G) | 破坏电压(V) | 缺陷比例(%) | 元件电致伸缩性(um) |
1300 | X | 10.2 | 4.5 | 2.8 | 400 | 0 | 0.1 |
1295 | A | 10.2 | 4.4 | 2.8 | 401 | 0 | 0.09 |
B | 9.9 | 4.2 | 2.9 | 405 | 0 | 0.08 | |
C | 9.1 | 3.1 | 3.1 | 410 | 0 | 0.06 | |
1305 | B | 10.2 | 4.6 | 2.7 | 395 | 0 | 0.07 |
C | 10.1 | 4.4 | 3 | 401 | 0 | 0.06 | |
D | 10.2 | 4.5 | 2.9 | 395 | 0 | 0.09 | |
1240 | X | 5.1 | 2.8 | 4.5 | 375 | 0 | 0.06 |
1235 | D | 4.7 | 2.3 | 4.8 | 380 | 0 | 0.05 |
1245 | B | 5.1 | 2.8 | 4.5 | 378 | 0 | 0.04 |
1290 | X | 8.2 | 4.3 | 3.3 | 360 | 0 | 0.09 |
1285 | A | 8.2 | 4.3 | 3.3 | 358 | 0 | 0.08 |
B | 8.1 | 4.1 | 3.6 | 367 | 0 | 0.07 | |
D | 8.2 | 4.2 | 3.3 | 356 | 0 | 0.08 | |
1300 | C | 8 | 4 | 3.8 | 364 | 0 | 0.06 |
D | 8.2 | 4.3 | 3.3 | 360 | 0 | 0.08 | |
1230 | X | 6.6 | 2.6 | 4.3 | 386 | 0 | 0.08 |
1225 | C | 6.2 | 2.3 | 4.8 | 387 | 0 | 0.05 |
D | 6.4 | 2.5 | 4.6 | 389 | 0 | 0.07 | |
1240 | B | 6.4 | 2.5 | 4.5 | 388 | 0 | 0.06 |
C | 6.3 | 2.3 | 4.7 | 390 | 0 | 0.05 | |
1230 | X | 5.5 | 1.9 | 4.9 | 375 | 0 | 0.07 |
1220 | D | 5.2 | 1.7 | 4.8 | 385 | 0 | 0.06 |
1240 | C | 5.1 | 1.6 | 4.6 | 378 | 0 | 0.04 |
D | 5.4 | 1.8 | 4.8 | 383 | 0 | 0.06 | |
1230 | X | 4.2 | 1.5 | 4.8 | 410 | 0 | 0.05 |
1220 | B | 4.1 | 1.4 | 4.9 | 415 | 0 | 0.03 |
1240 | C | 3.8 | 1.2 | 4.5 | 420 | 0 | 0.02 |
D | 4 | 1.2 | 4.6 | 418 | 0 | 0.03 | |
1285 | X | 7 | 2.8 | 3.9 | 360 | 0 | 0.08 |
1280 | B | 6.8 | 2.6 | 4 | 365 | 0 | 0.06 |
C | 6.6 | 2.3 | 4.1 | 363 | 0 | 0.05 | |
1290 | C | 6.7 | 2.3 | 4.1 | 365 | 0 | 0.05 |
D | 6.9 | 2.6 | 4.1 | 366 | 0 | 0.06 | |
1235 | X | 5.5 | 2.2 | 5.3 | 411 | 0 | 0.06 |
1225 | B | 5.3 | 2 | 5.4 | 414 | 0 | 0.05 |
1245 | B | 5.3 | 2 | 5.5 | 417 | 0 | 0.05 |
C | 5 | 1.7 | 5.4 | 417 | 0 | 0.04 | |
1295 | X | 6.8 | 2.1 | 4 | 374 | 0 | 0.08 |
1290 | C | 5.9 | 1.6 | 4.2 | 381 | 0 | 0.06 |
D | 6 | 1.7 | 4.2 | 383 | 0 | 0.07 | |
1300 | C | 6.2 | 1.7 | 4.2 | 382 | 0 | 0.06 |
1300 | X | 5.7 | 5.2 | 6.1 | 355 | 0 | 0.07 |
1295 | C | 5.2 | 4.6 | 6.2 | 367 | 0 | 0.05 |
D | 5.4 | 5 | 6.1 | 365 | 0 | 0.06 | |
1300 | B | 5.6 | 5.2 | 6.3 | 360 | 0 | 0.07 |
C | 5.3 | 4.6 | 6.5 | 361 | 0 | 0.05 |
表二
综上所述,本案不仅于技术思想上确属创新,并具备常规传统结构所不及的功效,已充分符合新颖性及进步性的相关要求,故依法提出申请,恳请贵局核准本专利申请案,以励创作,至感德便。
Claims (10)
1.一种积层电子陶瓷元件的无压共烧结制法,其特征在于:该制法包括如下步骤:
(a)将介电常数k值大于1500以上高介电常数钙钛矿结构陶瓷结构层及k值小于100的低介电常数钙钛矿结构陶瓷结构层交错积层形成积层电子陶瓷元件;及
(b)将积层电子陶瓷元件于1150℃~1350℃,同时通入湿气、氮及氢混合气,并于还原气氛10-6~10-20atm环境下进行共烧结制作。
2.根据权利要求1的制法制得的积层电子陶瓷元件,其特征在于:该积层电子陶瓷元件包括:
(a)至少一覆盖层,该覆盖层为高介电常数陶瓷层或低介电常数陶瓷层;
(b)至少一反应层,该反应层交错积层于该覆盖层之间或该覆盖层一侧,该反应层为高介电常数陶瓷结构层或低介电常数陶瓷结构层;及
(c)至少一镍金属电极层,该镍金属电极层位于反应层交错积层位置。
3.如权利要求2所述的积层电子陶瓷元件,其特征在于:所述高介电常数陶瓷结构层包括高介电常数陶瓷层及高介电常数电极层,低介电常数陶瓷结构层包括低介电常数陶瓷层及低介电常数电极层。
4.如权利要求3所述的积层电子陶瓷元件,其特征在于:所述高介电常数电极层为表面施以镍金属或镍金属合金电极图形的高介电常数陶瓷层,低介电常数电极层为表面施以镍金属或镍金属合金电极图形的低介电常数陶瓷层。
5.如权利要求3或4所述的积层电子陶瓷元件,其特征在于:所述镍金属电极图形为连续、不连续或浮动式图样。
6.如权利要求2所述的积层电子陶瓷元件,其特征在于:所述高介电常数陶瓷层的组成包含主相材料及氧化物添加剂,该主相材料为BaxTiyO3,其中Ba与Ti的摩尔比x/y为0.99~1.06之间,该主相材料的粉体平均粒径大小D50范围在0.1至0.5μm之间。
7.如权利要求6所述的积层电子陶瓷元件,其特征在于:以BaTiO3(钛酸钡)重量100%为基础,其中氧化物添加剂的组成包括:0.32~2.70wt%碳酸钡(BaCO3)、0~0.06wt%三氧化钼(MoO3)、0.20~0.55wt%二氧化硅(SiO2)、0.17~0.72wt%氧化钇(Y2O3)、0.04~0.34wt%氧化镁(MgO)、0~0.07wt%五氧化二铌(Nb2O5)、0.11~0.28wt%碳酸锰(MnCO3)、0~1.61wt%氧化镱(Yb2O3)、0~0.51wt%氧化铝(Al2O3)、0~0.50wt%碳酸钙(CaCO3)、0~0.21wt%二氧化锆(ZrO2)、0~0.05wt%三氧化二钐(Sm2O3)、0~0.28wt%氧化镝(Dy2O3)、0~0.10wt%二氧化钛(TiO2)、0~0.04wt%五氧化二钒(V2O5)、0~0.13wt%碳酸锶(SrCO3)及0~0.23wt%一氧化锡(SnO)。
8.如权利要求2所述的积层电子陶瓷元件,其特征在于:所述低介电常数陶瓷层的组成包括共同相材料与氧化物添加剂,该共同相材料结构式为[(CaxSr1-x-yMgy)O]m[(TiwZr1-w- zHfz)O2],其中,各元素摩尔比为:0.65<x≤1,0≤y<0.05,0<w<0.74,0<z<0.02,0.95≤m≤1.15,该共同相材料的粉体平均粒径大小D50范围在0.3至0.6μm之间。
9.如权利要求8所述的积层电子陶瓷元件,其特征在于:所述低介电常数陶瓷层的组成是选自于由碳酸钙(CaCO3)、碳酸锶(SrCO3)、碳酸钡(BaCO3)、氧化镁(MgO)、二氧化钛(TiO2)、二氧化锆(ZrO2)、氧化锌(ZnO)、碳酸锰(MnCO3)、二氧化硅(SiO2)、二氧化铪(HfO2)、五氧化二钽(Ta2O5)、氧化钇(Y2O3)及氧化铝(Al2O3)所构成材料群组中的至少一种材料。
10.如权利要求8所述的积层电子陶瓷元件,其特征在于:所述低介电常数陶瓷层的组成为:21.42~35.85wt%碳酸钙(CaCO3)、0~21.31wt%碳酸锶(SrCO3)、0~7.97wt%碳酸钡(BaCO3)、0~11.20wt%氧化镁(MgO)、1.36~14.86wt%二氧化钛(TiO2)、6.74~51.30wt%二氧化锆(ZrO2)、0~5.83wt%氧化锌(ZnO)、0~1.30wt%碳酸锰(MnCO3)、0.59~26.58wt%二氧化硅(SiO2)、0.16~1.53wt%二氧化铪(HfO2)、0~0.11wt%五氧化二钽(Ta2O5)、0~0.12wt%氧化钇(Y2O3)及0~0.18wt%氧化铝(Al2O3)。
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