CN106887519A - A kind of preparation method of the resistance-variable storing device for realizing multilevel storage - Google Patents
A kind of preparation method of the resistance-variable storing device for realizing multilevel storage Download PDFInfo
- Publication number
- CN106887519A CN106887519A CN201710167921.0A CN201710167921A CN106887519A CN 106887519 A CN106887519 A CN 106887519A CN 201710167921 A CN201710167921 A CN 201710167921A CN 106887519 A CN106887519 A CN 106887519A
- Authority
- CN
- China
- Prior art keywords
- preparation
- resistance
- storing device
- functional layer
- variable storing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 26
- 238000003860 storage Methods 0.000 title claims abstract description 23
- 239000002346 layers by function Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 230000008569 process Effects 0.000 claims description 15
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 238000004549 pulsed laser deposition Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 239000007772 electrode material Substances 0.000 claims description 6
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 229910004166 TaN Inorganic materials 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 229910003070 TaOx Inorganic materials 0.000 claims description 3
- 229910003087 TiOx Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 238000010894 electron beam technology Methods 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims description 2
- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 7
- 230000010354 integration Effects 0.000 abstract 1
- 238000004377 microelectronic Methods 0.000 abstract 1
- 239000013528 metallic particle Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
Landscapes
- Semiconductor Memories (AREA)
Abstract
The present invention relates to microelectronic component and memory technology field, a kind of resistance-variable storing device preparation method for realizing multilevel storage is disclosed.The method includes：In grown above silicon bottom electrode, then functional layer material is grown thereon, ion implanting then is carried out to functional layer, finally grow Top electrode.Resistance-variable storing device of the invention can realize multilevel storage, and big switch resistance ratio, homogeneity is good, and simple structure the advantages of easy of integration, is conducive to wide popularization and application of the invention.
Description
Technical field
The invention belongs to ic manufacturing technology field, and in particular to a kind of resistance-variable storing device system for realizing multilevel storage
Preparation Method.
Background technology
Whether semiconductor memory, storage information can be kept according to its power down, can be divided into two classes：Volatile storage
And non-volatility memorizer.With the popularization of portable electric appts, share of the nonvolatile memory in storage market
It is increasing.Although current FLASH technologies are the main flows in nonvolatile memory market, with pushing away for semiconductor technology node
Enter, FLASH technologies are just running into a series of bottleneck problem such as operating voltage greatly, and size cannot reduce, and the retention time falls short of
Deng.It has been reported that the limit of FLASH technologies is look for one kind and can substitute FLASH in 16nm or so, scientific circles and industrial quarters
Non-volatility memorizer of future generation.Resistance-variable storing device (RRAM) is because operating voltage is low, non-destructive reads, service speed is fast
Research emphasis of the advantages of being easily integrated with simple structure as new non-volatility memorizer.Wherein resistance-variable storing device can be more
The ability (multilevel storage) changed between individual Resistance states is such that memory capacity is greatly increased so that resistance-variable storing device is closed extensively
Note.Realize that the mode of multilevel storage mainly there are two kinds at present：One kind is during SET (programming makes devices transition to low resistance state)
Realized by different limitation electric currents, another kind is by difference during RESET (programming makes devices transition to high-impedance state)
Voltage magnitude or voltage-duration obtain different resistance states.Obtained by the method for regulating and controlling RESET voltage amplitude or pulsewidth
There is bigger window between multiple resistance states, be conducive to simplifying periphery read/write circuit.But, second method requirement device
RESET processes gradually change, and the homogeneity of RESET voltage is preferable, and RRAM device prepared by conventional method is difficult to meet
Above-mentioned requirements.
The content of the invention
(1) technical problem to be solved
The invention provides a kind of preparation method of the resistance-variable storing device for realizing multilevel storage, the resistance-change memory utensil of preparation
There are uniform gradual RESET processes, multilevel storage can be realized in crossed array by controlling RESET voltage amplitude.
(2) technical scheme
The present invention is achieved by the following technical solutions：
A kind of resistance-variable storing device preparation method for realizing multilevel storage, comprises the following steps：
S1：Bottom electrode is formed on substrate, and forms functional layer on the bottom electrode；
S2：Ion implanting is carried out to functional layer；
S3：Top electrode is formed on a functional.
Preferably, the lower electrode material includes Pt, W, Ru, Al, TiN, TaN, IrO2, ITO or IZO.
Preferably, the functional layer material includes SiO2、HfO2、Al2O3、TaOxOr TiOx。
Preferably, the Ion Implanted for being used in the step S2 includes Ag, Cu, Cr or W.
Preferably, functional layer is formed using magnetron sputtering, pulsed laser deposition or Atomic layer deposition method on the bottom electrode.
Preferably, the upper electrode material is Pt, W, Ru, Al, TiN, TaN, IrO2, at least one of ITO, IZO.
Preferably, in the step S1, bottom electrode is deposited on substrate by photoetching, stripping.
Preferably, in the step S3, Top electrode is deposited by photoetching, stripping on a functional.
Preferably, the Top electrode and bottom electrode pass through electron beam evaporation, chemical vapor deposition, pulsed laser deposition, original
One kind in sublayer deposition or sputtering method prepares completion.
Preferably, the substrate is silicon chip.
(3) beneficial effect
From the point of view of above-mentioned technical proposal, the present invention has following beneficial effect：
1st, using the present invention, it is possible to achieve gradual RESET processes, be conducive to by regulate and control RESET voltage realize it is single
The multilevel storage of device, greatly improves storage density.
2nd, using the present invention, have by the control of RESET blanking voltages, between each resistance state of multilevel storage of acquisition larger
Memory window, be conducive to simplify periphery read/write circuit design difficulty.
Brief description of the drawings
Fig. 1 is the preparation method flow chart of resistance-variable storing device provided in an embodiment of the present invention；
Fig. 2 is that resistance-variable storing device provided in an embodiment of the present invention prepares bottom electrode process schematic；
Fig. 3 is the preparation functional layer process schematic of resistance-variable storing device provided in an embodiment of the present invention；
Fig. 4 is the ion implantation process schematic diagram of resistance-variable storing device provided in an embodiment of the present invention；
Fig. 5 is the preparation Top electrode process schematic of resistance-variable storing device provided in an embodiment of the present invention；
Fig. 6 is the I-V curve measurement result figure of resistance-variable storing device provided in an embodiment of the present invention；
Fig. 7 is that resistance-variable storing device provided in an embodiment of the present invention realizes different resistance states using different pulse RESET amplitudes,
So as to realize the tolerance measured drawing of multilevel storage.
Specific embodiment
To make the object, technical solutions and advantages of the present invention become more apparent, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in further detail.
The present invention is described more fully in reference implementation example below in association with being shown in, the present invention is provided and is preferable to carry out
Example, but should not be considered limited to embodiment set forth herein.In figure, in order to clearly be exaggerated the thickness of layer and region,
But should not be considered as strictly reflecting the proportionate relationship of physical dimension as schematic diagram.
It is herein the schematic diagram of idealized embodiments of the invention with reference to figure, the embodiment shown in the present invention should not be recognized
It is the given shape in region being only limitted to shown in figure, but including resulting shape, such as manufactures the deviation for causing.Fig. 1
It show the preparation method flow chart of resistance-variable storing device provided in an embodiment of the present invention.Meanwhile, this is illustrated by Fig. 2 to Fig. 5
The preparation process of resistance-variable storing device each several part, describes the preparation method of the resistance-variable storing device in detail below in conjunction with Fig. 2 to Fig. 5.
Step S1：Bottom electrode is formed on substrate, and forms functional layer on the bottom electrode.
Sub-step S11：Bottom electrode is formed on substrate.
Fig. 2 is that resistance-variable storing device provided in an embodiment of the present invention prepares bottom electrode process schematic, as shown in Fig. 2 should
Step is specifically included：Bottom electrode is deposited on silicon chip by photoetching, stripping.The bottom electrode can use Pt, W, Ru, Al, lead
Electric metal compound TiN, TaN, IrO2, at least one of ITO, IZO constitute.The lower electrode material can be steamed by electron beam
One kind in hair, chemical vapor deposition, pulsed laser deposition, ald, sputtering method prepares completion.
Sub-step S12：Surface forms functional layer on the bottom electrode.
Fig. 3 is the preparation functional layer process schematic of resistance-variable storing device provided in an embodiment of the present invention, as shown in figure 3,
In the step, deposit functional layers on the bottom electrode, wherein functional layer can use SiO2、HfO2、Al2O3、TaOx、TiOxDeng.Can
Functional layer is prepared with by methods such as magnetron sputtering, pulsed laser deposition, alds.
Step S2：Ion implanting is carried out to functional layer.
Fig. 4 is the ion implantation process schematic diagram of resistance-variable storing device provided in an embodiment of the present invention, as shown in figure 4, the step
In rapid, ion implanting is carried out to functional layer, injection material can be using Ag, Cu, Cr, W etc..
Step S3：Top electrode is formed on a functional.
Fig. 5 is the preparation Top electrode process schematic of resistance-variable storing device provided in an embodiment of the present invention, as shown in figure 5, should
Step is specifically included：Top electrode is deposited by photoetching, stripping on a functional.The Top electrode can use Pt, W, Ru, Al,
Conductive metallic compound TiN, TaN, IrO2, at least one of ITO, IZO constitute.The upper electrode material can be by electron beam
One kind in evaporation, chemical vapor deposition, pulsed laser deposition, ald, sputtering method prepares completion.
Fig. 6 illustrates the I-V curve measurement result of the resistance-variable storing device.As can be seen from the figure：Voltage is started from scratch increasing
It is added to Vth, device is constantly in high-impedance state.Continue to increase voltage (＞ Vth), electric current is increased dramatically suddenly and with the increasing of voltage
Increase until V greatlyset.When magnitude of voltage continues to increase above VsetWhen, electric current decreases up to V with the increase of voltagemin, and
The resistance obtained in this section of interval can be remained in that in the case of power down, so as to realize gradually gradual RESET processes.
The generation of the phenomenon is that electronics is in different electricity due to foring a series of discontinuous metallic particles in ion implanting to functional layer
Pressure is captured and discharged by these metallic particles.As cut-in voltage V of the magnitude of voltage more than electronics tunnelling between these particlesthWhen,
Electronics is captured so as to be easier to transmit by tunnelling by metallic particles, causes electric current to increase suddenly.When voltage continues to increase (＞
Vth), sufficiently large voltage makes metallic particles discharge electronics causes electric current to reduce so as to realize gradual RESET.
Fig. 7 illustrates the resistance-variable storing device using different pulse RESET amplitudes to realize different resistance states, many-valued so as to realize
The tolerance measured drawing of storage.As can be seen from the figure：(1V/1ms pulses are used by device Set to low resistance state Ron, then apply not
Same RESET pulse (- 2V/0.2ms, -3V/0.2ms, -4V/0.2ms) can respectively obtain different resistance state Roff1, Roff2, Roff3.Should
Device can so apply pulses switch resistance more than 100 times.)
So far, can realize that the preparation method process of the resistance-variable storing device of multilevel storage is completed shown in Fig. 1.Using this hair
It is bright, ion implanting is carried out to functional layer so as to form a series of discontinuous metallic particles wherein, it is possible to achieve uniform gradual
RESET processes, be conducive to being realized by regulating and controlling RESET voltage the multilevel storage of individual devices, greatly improve storage density.It is logical
The control of RESET blanking voltages is crossed, there is larger memory window between each resistance state of multilevel storage of acquisition, be conducive to simplifying outer
Enclose the design difficulty of read/write circuit.
Many can also be constituted without departing from the spirit and scope of the present invention the embodiment of very big difference.Should
Work as understanding, except as defined by the appended claims, the invention is not restricted to specific embodiment described in the description.
Particular embodiments described above, has been carried out further in detail to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail bright, it should be understood that the foregoing is only specific embodiment of the invention, be not intended to limit the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc. should be included in protection of the invention
Within the scope of.
Claims (10)
1. a kind of resistance-variable storing device preparation method for realizing multilevel storage, it is characterised in that comprise the following steps：
S1：Bottom electrode is formed on substrate, and forms functional layer on the bottom electrode；
S2：Ion implanting is carried out to functional layer；
S3：Top electrode is formed on a functional.
2. preparation method as claimed in claim 1, it is characterised in that the lower electrode material include Pt, W, Ru, Al, TiN,
TaN、IrO2, ITO or IZO.
3. preparation method as claimed in claim 1, it is characterised in that the functional layer material includes SiO2、HfO2、Al2O3、
TaOxOr TiOx。
4. preparation method as claimed in claim 1, it is characterised in that the Ion Implanted used in the step S2 includes
Ag, Cu, Cr or W.
5. preparation method as claimed in claim 1, it is characterised in that using magnetron sputtering, pulsed laser deposition or atomic layer
Deposition process forms functional layer on the bottom electrode.
6. preparation method as claimed in claim 1, it is characterised in that the upper electrode material be Pt, W, Ru, Al, TiN,
TaN、IrO2, at least one of ITO, IZO.
7. preparation method as claimed in claim 1, it is characterised in that in the step S1, by photoetching, peels off in substrate
Upper deposition bottom electrode.
8. preparation method as claimed in claim 1, it is characterised in that in the step S3, by photoetching, peels off in function
Top electrode is deposited on layer.
9. preparation method as claimed in claim 7 or 8, it is characterised in that the Top electrode and bottom electrode are steamed by electron beam
One kind in hair, chemical vapor deposition, pulsed laser deposition, ald or sputtering method prepares completion.
10. preparation method as claimed in claim 1, it is characterised in that the substrate is silicon chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710167921.0A CN106887519B (en) | 2017-03-20 | 2017-03-20 | Preparation method of resistive random access memory for realizing multi-value storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710167921.0A CN106887519B (en) | 2017-03-20 | 2017-03-20 | Preparation method of resistive random access memory for realizing multi-value storage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106887519A true CN106887519A (en) | 2017-06-23 |
| CN106887519B CN106887519B (en) | 2020-07-21 |
Family
ID=59180810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710167921.0A Active CN106887519B (en) | 2017-03-20 | 2017-03-20 | Preparation method of resistive random access memory for realizing multi-value storage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106887519B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389964A (en) * | 2018-04-03 | 2018-08-10 | 集美大学 | The resistance-variable storing device preparation method of ion positioning injection is carried out with nanometer shielding layer |
| CN114171677A (en) * | 2021-11-10 | 2022-03-11 | 武汉理工大学 | Dielectric layer for realizing multi-value storage, resistive random access memory, and preparation method and application thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101281953A (en) * | 2008-04-29 | 2008-10-08 | 北京大学 | Material with steady resistance-vary feature as well as resistance-vary memory |
| US20090039337A1 (en) * | 2007-08-06 | 2009-02-12 | Sony Corporation | Memory element and memory device |
| CN101471421A (en) * | 2007-12-26 | 2009-07-01 | 中国科学院微电子研究所 | Dyadic transition group metallic oxide non-volatilization electric resistance transition type memory |
| CN102881824A (en) * | 2012-09-25 | 2013-01-16 | 北京大学 | Resistance change memory and preparation method thereof |
| CN103117359A (en) * | 2013-02-07 | 2013-05-22 | 北京大学 | High-reliability nonvolatile memory and preparation method thereof |
| CN103515534A (en) * | 2013-10-10 | 2014-01-15 | 北京大学 | Resistive random access memory with high uniformity and manufacturing method thereof |
-
2017
- 2017-03-20 CN CN201710167921.0A patent/CN106887519B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090039337A1 (en) * | 2007-08-06 | 2009-02-12 | Sony Corporation | Memory element and memory device |
| CN101471421A (en) * | 2007-12-26 | 2009-07-01 | 中国科学院微电子研究所 | Dyadic transition group metallic oxide non-volatilization electric resistance transition type memory |
| CN101281953A (en) * | 2008-04-29 | 2008-10-08 | 北京大学 | Material with steady resistance-vary feature as well as resistance-vary memory |
| CN102881824A (en) * | 2012-09-25 | 2013-01-16 | 北京大学 | Resistance change memory and preparation method thereof |
| CN103117359A (en) * | 2013-02-07 | 2013-05-22 | 北京大学 | High-reliability nonvolatile memory and preparation method thereof |
| CN103515534A (en) * | 2013-10-10 | 2014-01-15 | 北京大学 | Resistive random access memory with high uniformity and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| WENQING LI: "Design of high performance memristor cell using W-implanted SiO2 films", 《APPLIED PHYSICS LETTERS》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108389964A (en) * | 2018-04-03 | 2018-08-10 | 集美大学 | The resistance-variable storing device preparation method of ion positioning injection is carried out with nanometer shielding layer |
| CN108389964B (en) * | 2018-04-03 | 2021-05-25 | 集美大学 | Method for preparing resistive random access memory by using nano shielding layer to perform ion positioning injection |
| CN114171677A (en) * | 2021-11-10 | 2022-03-11 | 武汉理工大学 | Dielectric layer for realizing multi-value storage, resistive random access memory, and preparation method and application thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106887519B (en) | 2020-07-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Bousoulas et al. | Low-power and highly uniform 3-b multilevel switching in forming free TiO 2–x-based RRAM with embedded Pt nanocrystals | |
| TWI402980B (en) | Resistive memory structure with buffer layer | |
| CN101288187B (en) | Reproducible resistance variable insulating memory devices and methods for forming same | |
| US10236061B2 (en) | Resistive random access memory having charge trapping layer, manufacturing method thereof, and operation thereof | |
| TWI385790B (en) | Polysilicon plug bipolar transistor for phase change memory | |
| CN101192647A (en) | Nonvolatile memory device including amorphous alloy metal oxide layer | |
| TWI325164B (en) | Method for manufacturing a resistor random access memory with a self-aligned air gap insulator | |
| EP3602561B1 (en) | A switching resistor and method of making such a device | |
| JP2005340786A (en) | Formation method of pcmo thin film having memory resistance property and pcmo device | |
| CN111129299A (en) | Ferroelectric memristor based on two-dimensional material and preparation method thereof | |
| CN102623631A (en) | Resistance transformation type random access memory unit, memory, and preparation method | |
| CN101872836A (en) | Resistor-type nonvolatile storage device and manufacturing method thereof | |
| CN102074270A (en) | Multivalue storage method of primary programming memory | |
| CN107895757A (en) | A kind of nano dot contact of quantum conductance controlled properties | |
| Qi et al. | Oxygen Vacancy Kinetics Mechanism of the Negative Forming‐Free Process and Multilevel Resistance Based on Hafnium Oxide RRAM | |
| CN103633243B (en) | A kind of preparation method of resistor-type memory | |
| US20160155619A1 (en) | Forming memory using high power impulse magnetron sputtering | |
| CN106229407B (en) | A kind of high consistency resistance-variable storing device and preparation method thereof | |
| CN105932035A (en) | Gating device for resistive random access memory crossbar array and preparation method thereof | |
| CN106887519A (en) | A kind of preparation method of the resistance-variable storing device for realizing multilevel storage | |
| CN107204397B (en) | Selector and preparation method thereof for bipolar resistance transformation | |
| CN102593349A (en) | SixNy-based resistor-type memory and manufacturing method and application thereof | |
| CN101834274B (en) | Preparation method of variable resistance metal nitride materials | |
| US8742386B2 (en) | Oxide based memory with a controlled oxygen vacancy conduction path | |
| CN110752293A (en) | Bidirectional threshold switch selection device and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |