CN102593349A - SixNy-based resistor-type memory and manufacturing method and application thereof - Google Patents
SixNy-based resistor-type memory and manufacturing method and application thereof Download PDFInfo
- Publication number
- CN102593349A CN102593349A CN2011100054633A CN201110005463A CN102593349A CN 102593349 A CN102593349 A CN 102593349A CN 2011100054633 A CN2011100054633 A CN 2011100054633A CN 201110005463 A CN201110005463 A CN 201110005463A CN 102593349 A CN102593349 A CN 102593349A
- Authority
- CN
- China
- Prior art keywords
- resistance
- layer
- change memory
- memory
- bottom electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention relates to a SixNy-based resistor-type memory and a manufacturing method and application thereof, belonging to the technical field of microelectronics. The SixNy-based resistor-type memory comprises an upper electrode, an insulated dielectric layer, a resistance-variable storage layer and a lower electrode, wherein the insulated dielectric layer is arranged on the lower electrode; the lower electrode provided with the insulated dielectric layer is provided with a hole which penetrates through the insulated dielectric layer; the resistance-variable storage layer and the upper electrode are both positioned in the hole; and the resistance-variable storage layer is positioned between the upper electrode and the lower electrode, and the resistance-variable storage layer is made of a SixNy material, wherein y is less than x and more than 3/4. The SixNy-based resistor-type memory is completely compatible with a CMOS (Complementary Metal Oxide Semiconductor) process and has the characteristics of extralarge storage window, high speed and low power consumption.
Description
Technical field
The present invention relates to a kind of resistor-type memory, relate in particular to a kind of Si
xN
yBased resistance memory and its production and application, belong to microelectronics technology.
Background technology
Resistor-type nonvolatile storage (RRAM; Resistive random access memory) because it is simple in structure, with the CMOS process compatible; And have high speed, low-power consumption, high density, low cost and can break through the advantage of technology generation development restriction and cause widely and to pay close attention to, become The Study of Non-Volatile Memory focus of new generation gradually.Resistor-type memory is through action of electric signals, make storage medium high resistance state (High Resistance State, HRS) with low resistance (Low Resistance State, but LRS) inverse conversion takes place between the state, thereby the memory function of realization data.At present, material systems such as Mn oxide material, transition metal perovskite material, binary metal oxide material, high-molecular organic material and some sulfide as the resistance-change memory layer by extensive studies.But, also seldom be in the news for the research of adopting nitride material as the resistance-change memory layer.
In various nitride materials, silicon nitride material has high-k, high insulation resistance, electric leakage characteristics such as low, in modern times in the semiconductor CMOS technology by application widely and passivation, isolation and capacitor dielectric layer.Simultaneously, owing to have a large amount of defect states in the silicon nitride film, thereby be widely used in charge trap type nonvolatile storage as charge storage layer.Based on the above-mentioned advantage of silicon nitride material, the potential application of this material in resistor-type non-volatile memory field also will be by extensive research.
Summary of the invention
The present invention is directed to and also do not adopt the deficiency of the outstanding silicon nitride material of nitride material at present, a kind of Si is provided as the resistance-change memory layer
xN
yBased resistance memory.
The technical scheme that the present invention solves the problems of the technologies described above is following: a kind of Si
xN
yBased resistance memory comprises top electrode, insulating medium layer, resistance-change memory layer and bottom electrode; Said insulating medium layer is arranged on the bottom electrode; Have on the said bottom electrode that is provided with insulating medium layer one run through insulating medium layer hole; Said resistance-change memory layer and top electrode all are arranged in described hole, and said resistance-change memory layer is between top electrode and bottom electrode, and said resistance-change memory layer is by Si
xN
yMaterial is processed, wherein, and x/y＞3/4.
On the basis of technique scheme, the present invention can also do following improvement.
Further, the thickness of said top electrode is 1nm～500nm.
Further, said upper electrode material is processed by W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Si, TiN, TaN, IrO, ITO or IZO.
Further, said bottom electrode is processed by W.
Further, the thickness of said bottom electrode is 1nm～500nm.
Further, the thickness of said resistance-change memory layer is 1nm～500nm.
The present invention also provides a kind of technical scheme that solves the problems of the technologies described above following: a kind of Si
xN
yThe preparation method of based resistance memory may further comprise the steps:
Step a1: deposition forms insulating medium layer on bottom electrode, and said insulating medium layer is carried out perforate to expose bottom electrode;
Step b1: deposition forms the resistance-change memory layer on the bottom electrode of said exposure;
Step c1: on said resistance-change memory layer, form top electrode.
Further, form the resistance-change memory layer through PECVD, LPCVD or ALD technology among the said step b1.
Further, the resistance-change memory layer is processed by the SixNy material among the said step b1, and wherein, the ratio of Si and N is regulated through the condition of control PECVD, LPCVD or ALD technology, perhaps injects through follow-up Si ion and regulates.
The present invention also provides a kind of Si
xN
yThe application of based resistance memory in the aluminium interconnection process may further comprise the steps:
Step a2: the tungsten plug structure of using in the conventional aluminium interconnection structure is provided, and said tungsten plug structure is as Si
xN
yThe bottom electrode of based resistance memory;
Step b2: on said tungsten plug structure, form insulating medium layer, and said insulating medium layer is carried out perforate to expose the tungsten plug structure;
Step c2: on the tungsten plug structure of said exposure, deposit Si
xN
yMaterial forms the resistance-change memory layer, wherein, and x/y＞3/4;
Steps d 2: on said resistance-change memory layer, form top electrode;
Step e2: on said top electrode, deposit weld layer, interconnecting metal layer and anti-reflecting layer successively, the method composition through photoetching and etching forms aluminum interconnecting again.
The invention has the beneficial effects as follows: SixNy based resistance memory of the present invention and CMOS technology are compatible fully, can be integrated and the backend process of A1 interconnection, have very high practical value, and have the super large memory window, at a high speed, low in power consumption.
Description of drawings
Fig. 1 is embodiment of the invention Si
xN
yThe structural representation of based resistance memory;
Fig. 2 is embodiment of the invention Si
xN
yBased resistance memory is applied to the structural representation in the aluminium interconnection structure;
Fig. 3 is embodiment of the invention Si
xN
yThe flow chart of the application of based resistance memory in the aluminium interconnection process;
Fig. 4 is the current-voltage curve of device in the embodiment of the invention one;
Fig. 5 is the current-voltage curve of device in the embodiment of the invention two.
Embodiment
Below in conjunction with accompanying drawing principle of the present invention and characteristic are described, institute gives an actual example and only is used to explain the present invention, is not to be used to limit scope of the present invention.
Fig. 1 is embodiment of the invention Si
xN
yThe structural representation of based resistance memory.As shown in Figure 1, Si
xN
yBased resistance memory comprises top electrode 14, insulating medium layer 12, resistance-change memory layer 13 and bottom electrode 11.Insulating medium layer 12 is arranged on the bottom electrode 11.Be provided with have on the bottom electrode 11 of insulating medium layer 12 one run through insulating medium layer hole.Resistance-change memory layer 13 all is arranged in described hole with top electrode 11.Resistance-change memory layer 13 is between top electrode 14 and bottom electrode 11.Resistance-change memory layer 13 is by Si
xN
yMaterial is processed, wherein, and x/y＞3/4.
Fig. 2 is embodiment of the invention Si
xN
yBased resistance memory is applied to the structural representation in the aluminium interconnection structure, and Fig. 3 is embodiment of the invention Si
xN
yThe flow chart of the application of based resistance memory in the aluminium interconnection process.Shown in Fig. 2 and 3, said application may further comprise the steps:
Step a2: the first tungsten plug structure 101 and first insulating medium layer 201 that use in the conventional aluminium interconnection structure are provided, and the said first tungsten plug structure 101 is as Si
xN
yThe bottom electrode of based resistance memory;
Step b2: on the said first tungsten plug structure 101, form second insulating medium layer 202, and said second insulating medium layer 202 is carried out perforate to expose the first tungsten plug structure 101;
Step c2: on the tungsten plug structure 101 of said exposure, deposit Si
xN
yMaterial forms resistance-change memory layer 301, wherein, and x/y＞3/4;
Steps d 2: on said resistance-change memory layer 301, form top electrode 401;
Step e2: after forming the second tungsten plug structure 501 and the 3rd insulating medium layer 203 on the said top electrode 401, deposit weld layer, interconnecting metal layer and anti-reflecting layer more successively, the method composition through photoetching and etching forms aluminum interconnecting 601 again.
Embodiment one: at first, etch through hole at deposit 400nm is thick on the W embolism dielectric layer and with dielectric layer after graphical; Then, adopt PECVD or the thick Si of ALD technology deposit one deck 20nm
xN
yThin layer, and regulate Si through the process conditions of control PECVD or ALD
xN
yThe chemical composition proportioning of film makes Si: the N ratio is 2: 1; Then, adopt the thick Cu of magnetron sputtering deposit one deck 500nm, and the Cu electrode that adopts the method for CMP will exceed through hole polishes, make the RRAM device architecture fully in the through hole of dielectric layer as top electrode; Deposit weld layer, interconnecting metal layer, anti-reflecting layer at last successively, and accomplish the aluminum lead wiring through photoetching, lithographic method composition.
Fig. 4 has provided Cu/Si
xN
yThe current-voltage curve of/W device, this device have bipolarity electric resistance changing characteristic in the voltage scanning process, when the cut-off current of SET process during less than 1 μ A, the RESET process just can be accomplished under hundreds of nA electric current, and Cu/Si is described
xN
y/ W device has certain advantage in the low-power consumption application.Simultaneously, through pulse test, Cu/Si
xN
yThe electric resistance changing speed of/W device explains that less than 20ns this device also has the potentiality of application in the high speed storing field.
Embodiment two: this embodiment and embodiment one difference are that embodiment two adopts ion implantation technology to Si
xN
yThe chemical composition proportioning of film is regulated, and adopts the Ti metallic film to become the top electrode of device as resistance simultaneously.Fig. 5 has provided Ti/Si
xN
yThe current-voltage curve of/W, this device have unipolarity electric resistance changing characteristic in the voltage scanning process.The resistance-change memory device that one pole changes helps the integrated of 1D1R, has simplified the design difficulty of peripheral circuit simultaneously.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. Si
xN
yBased resistance memory; It is characterized in that comprise top electrode, insulating medium layer, resistance-change memory layer and bottom electrode, said insulating medium layer is arranged on the bottom electrode; Have on the said bottom electrode that is provided with insulating medium layer one run through insulating medium layer hole; Said resistance-change memory layer and top electrode all are arranged in described hole, and said resistance-change memory layer is between top electrode and bottom electrode, and said resistance-change memory layer is by Si
xN
yMaterial is processed, wherein, and x/y＞3/4.
2. Si according to claim 1
xN
yBased resistance memory is characterized in that, the thickness of said top electrode is 1nm～500nm.
3. Si according to claim 1
xN
yBased resistance memory is characterized in that, said upper electrode material is processed by W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Si, TiN, TaN, IrO, ITO or IZO.
4. Si according to claim 1
xN
yBased resistance memory is characterized in that, said bottom electrode is processed by W.
5. Si according to claim 1
xN
yBased resistance memory is characterized in that, the thickness of said bottom electrode is 1nm～500nm.
6. Si according to claim 1
xN
yBased resistance memory is characterized in that, the thickness of said resistance-change memory layer is 1nm～500nm.
7. Si
xN
yThe preparation method of based resistance memory is characterized in that, said preparation method may further comprise the steps:
Step a1: deposition forms insulating medium layer on bottom electrode, and said insulating medium layer is carried out perforate to expose bottom electrode;
Step b1: on the bottom electrode of said exposure, deposit Si
xN
yMaterial forms the resistance-change memory layer, wherein, and x/y＞3/4;
Step c1: on said resistance-change memory layer, form top electrode.
8. Si according to claim 7
xN
yThe preparation method of based resistance memory is characterized in that, forms the resistance-change memory layer through PECVD, LPCVD or ALD technology among the said step b1.
9. Si according to claim 7
xN
yThe preparation method of based resistance memory is characterized in that, the resistance-change memory layer is by Si among the said step b1
xN
yMaterial is processed, and wherein, the ratio of Si and N is regulated through the condition of control PECVD, LPCVD or ALD technology, perhaps injects through follow-up Si ion and regulates.
10. Si
xN
yThe application of based resistance memory in the aluminium interconnection process is characterized in that, said application may further comprise the steps:
Step a2: the tungsten plug structure of using in the conventional aluminium interconnection structure is provided, and said tungsten plug structure is as Si
xN
yThe bottom electrode of based resistance memory;
Step b2: on said tungsten plug structure, form insulating medium layer, and said insulating medium layer is carried out perforate to expose the tungsten plug structure;
Step c2: on the tungsten plug structure of said exposure, deposit Si
xN
yMaterial forms the resistance-change memory layer, wherein, and x/y＞3/4;
Steps d 2: on said resistance-change memory layer, form top electrode;
Step e2: on said top electrode, deposit weld layer, interconnecting metal layer and anti-reflecting layer successively, the method composition through photoetching and etching forms aluminum interconnecting again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100054633A CN102593349A (en) | 2011-01-12 | 2011-01-12 | SixNy-based resistor-type memory and manufacturing method and application thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100054633A CN102593349A (en) | 2011-01-12 | 2011-01-12 | SixNy-based resistor-type memory and manufacturing method and application thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102593349A true CN102593349A (en) | 2012-07-18 |
Family
ID=46481731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100054633A Pending CN102593349A (en) | 2011-01-12 | 2011-01-12 | SixNy-based resistor-type memory and manufacturing method and application thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102593349A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107732011A (en) * | 2017-09-29 | 2018-02-23 | 浙江师范大学 | A kind of new resistance-variable storing device and its manufacture method |
| CN111653666A (en) * | 2020-06-12 | 2020-09-11 | 北京大学 | Gating device, resistive random access memory and operation method thereof |
| CN111668253A (en) * | 2020-06-22 | 2020-09-15 | 中国科学院微电子研究所 | Resistive random access memory and preparation method thereof |
| CN112885869A (en) * | 2021-02-03 | 2021-06-01 | 湖北大学 | 1S1R device based on metallic intercalation and preparation method thereof |
| CN112885868A (en) * | 2021-02-03 | 2021-06-01 | 湖北大学 | 1S1R device based on niobium oxide gate tube and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1834288A (en) * | 2006-04-07 | 2006-09-20 | 中国科学院上海硅酸盐研究所 | Low temp chemical gaseous deposition for preparing silicon nitride thin film |
| US7402851B2 (en) * | 2003-02-24 | 2008-07-22 | Samsung Electronics Co., Ltd. | Phase changeable memory devices including nitrogen and/or silicon and methods for fabricating the same |
| CN101501852A (en) * | 2006-11-20 | 2009-08-05 | 松下电器产业株式会社 | Non-volatile storage element, non-volatile storage element array and method for manufacturing the same |
| CN101857206A (en) * | 2010-05-13 | 2010-10-13 | 复旦大学 | Metal nitride with resistance change nature and application thereof |
-
2011
- 2011-01-12 CN CN2011100054633A patent/CN102593349A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7402851B2 (en) * | 2003-02-24 | 2008-07-22 | Samsung Electronics Co., Ltd. | Phase changeable memory devices including nitrogen and/or silicon and methods for fabricating the same |
| CN1834288A (en) * | 2006-04-07 | 2006-09-20 | 中国科学院上海硅酸盐研究所 | Low temp chemical gaseous deposition for preparing silicon nitride thin film |
| CN101501852A (en) * | 2006-11-20 | 2009-08-05 | 松下电器产业株式会社 | Non-volatile storage element, non-volatile storage element array and method for manufacturing the same |
| CN101857206A (en) * | 2010-05-13 | 2010-10-13 | 复旦大学 | Metal nitride with resistance change nature and application thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107732011A (en) * | 2017-09-29 | 2018-02-23 | 浙江师范大学 | A kind of new resistance-variable storing device and its manufacture method |
| CN107732011B (en) * | 2017-09-29 | 2020-04-17 | 浙江师范大学 | Novel resistive random access memory and manufacturing method thereof |
| CN111653666A (en) * | 2020-06-12 | 2020-09-11 | 北京大学 | Gating device, resistive random access memory and operation method thereof |
| CN111668253A (en) * | 2020-06-22 | 2020-09-15 | 中国科学院微电子研究所 | Resistive random access memory and preparation method thereof |
| CN112885869A (en) * | 2021-02-03 | 2021-06-01 | 湖北大学 | 1S1R device based on metallic intercalation and preparation method thereof |
| CN112885868A (en) * | 2021-02-03 | 2021-06-01 | 湖北大学 | 1S1R device based on niobium oxide gate tube and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101064359B (en) | Non-volatile memory devices including variable resistance material | |
| KR102022744B1 (en) | Nonvolatile resistive memory element with an integrated oxygen isolation structure | |
| CN101097988B (en) | Variable resistance random access memory device containing n+ interface layer | |
| US9287502B2 (en) | Resistance variable memory cell structures and methods | |
| CN101106171B (en) | Non-volatile memory device including variable resistance material | |
| US8048755B2 (en) | Resistive memory and methods of processing resistive memory | |
| US9214629B2 (en) | Resistive memory and method for fabricating the same | |
| US8853046B2 (en) | Using TiON as electrodes and switching layers in ReRAM devices | |
| US20140124728A1 (en) | Resistive memory device, resistive memory array, and method of manufacturing resistive memory device | |
| US8716059B2 (en) | Combined conductive plug/conductive line memory arrays and methods of forming the same | |
| US20170330916A1 (en) | Complementary resistive switching memory device having three-dimensional crossbar-point vertical multi-layer structure | |
| CN109638153A (en) | A kind of gating tube material, gating tube device and preparation method thereof | |
| EP2930760B1 (en) | Method for forming memory device | |
| CN102593349A (en) | SixNy-based resistor-type memory and manufacturing method and application thereof | |
| US20200381479A1 (en) | Rram process integration scheme and cell structure with reduced masking operations | |
| US20130248806A1 (en) | Variable resistance memory device and method for fabricating the same | |
| CN105870321A (en) | Nonlinear self-rectifying resistive random access memory and preparation method therefor | |
| US9029829B1 (en) | Resistive switching memories | |
| US20130217199A1 (en) | Method for fabricating resistive memory device | |
| KR20080034310A (en) | Resistive ram having amorphous solid electrolyte and method of operating the same | |
| CN102694118A (en) | A resistance random access memory and a preparation method thereof | |
| US10297748B2 (en) | Three-terminal atomic switching device and method of manufacturing the same | |
| US20090103351A1 (en) | Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Memory Module | |
| US20220320429A1 (en) | Resistive switching memory devices and method(s) for forming the resistive switching memory devices | |
| CN106887519A (en) | A kind of preparation method of the resistance-variable storing device for realizing multilevel storage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120718 |