CN106887519B

CN106887519B - Preparation method of resistive random access memory for realizing multi-value storage

Info

Publication number: CN106887519B
Application number: CN201710167921.0A
Authority: CN
Inventors: 刘琦; 伍法才; 刘明; 龙世兵; 吕杭炳
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2017-03-20
Filing date: 2017-03-20
Publication date: 2020-07-21
Anticipated expiration: 2037-03-20
Also published as: CN106887519A

Abstract

The invention relates to the technical field of microelectronic devices and memories, and discloses a method for preparing a resistive random access memory for realizing multi-value storage. The method comprises the following steps: growing a lower electrode on a silicon wafer, growing a functional layer material on the lower electrode, then performing ion implantation on the functional layer, and finally growing an upper electrode. The resistive random access memory can realize multi-value storage, has the advantages of large on-off resistance ratio, good uniformity, simple structure, easy integration and the like, and is favorable for wide popularization and application.

Description

Preparation method of resistive random access memory for realizing multi-value storage

Technical Field

The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a resistive random access memory preparation method for realizing multi-value storage.

Background

Although the current F L ASH technology is the mainstream of the non-volatile memory market, as the progress of semiconductor process nodes, the F L ASH technology is encountering a series of bottleneck problems such as large operating voltage, inability to reduce size, insufficient retention time, etc. it is reported that the limit of the F L ASH technology is around 16nm, the scientific and industrial circles are looking for a next generation non-volatile memory that can replace the F L ASH.

Disclosure of Invention

Technical problem to be solved

The invention provides a preparation method of a resistive random access memory for realizing multi-value storage.

(II) technical scheme

The invention is realized by the following technical scheme:

a resistive random access memory preparation method for realizing multi-value storage comprises the following steps:

s1: forming a lower electrode on a substrate, and forming a functional layer on the lower electrode;

s2: performing ion implantation on the functional layer;

s3: an upper electrode is formed on the functional layer.

Preferably, the lower electrode material comprises Pt, W, Ru, Al, TiN, TaN, IrO₂ITO or IZO.

Preferably, the functional layer material comprises SiO₂、HfO₂、Al₂O₃、TaO_xOr TiO_x。

Preferably, the ion implantation material used in step S2 includes Ag, Cu, Cr, or W.

Preferably, the functional layer is formed on the lower electrode by magnetron sputtering, pulsed laser deposition or atomic layer deposition.

Preferably, the upper electrode material is Pt, W, Ru, Al, TiN, TaN, IrO₂At least one of ITO and IZO.

Preferably, in the step S1, the lower electrode is deposited on the substrate by photolithography and lift-off.

Preferably, in step S3, the upper electrode is deposited on the functional layer by photolithography and lift-off.

Preferably, the upper electrode and the lower electrode are prepared by one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or sputtering method.

Preferably, the substrate is a silicon wafer.

(III) advantageous effects

From the technical scheme, the invention has the following beneficial effects:

1. the invention can realize the gradual RESET process, is beneficial to realizing the multi-value storage of a single device by regulating and controlling the RESET voltage, and greatly improves the storage density.

2. By utilizing the invention, through the control of the RESET cut-off voltage, a larger storage window is formed between resistance states of the obtained multi-value storage, which is beneficial to simplifying the design difficulty of a peripheral read-write circuit.

Drawings

Fig. 1 is a flowchart of a method for manufacturing a resistive random access memory according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a lower electrode preparation process of a resistive random access memory provided in an embodiment of the present invention;

fig. 3 is a schematic diagram of a functional layer preparation process of a resistive random access memory according to an embodiment of the present invention;

fig. 4 is a schematic view of an ion implantation process of a resistive random access memory according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a process of preparing an upper electrode of a resistive random access memory according to an embodiment of the present invention;

fig. 6 is a graph of an I-V curve measurement result of the resistive random access memory provided by the embodiment of the present invention;

fig. 7 is a practical diagram of the resistance random access memory provided by the embodiment of the invention, which uses different pulse RESET amplitudes to realize different resistance states, thereby realizing the tolerance of multi-value storage.

Detailed Description

In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.

The present invention will be described more fully hereinafter in the reference to the accompanying drawings, which provide preferred embodiments of the invention, and which are not to be considered as limited to the embodiments set forth herein. In the figures, the thicknesses of layers and regions are exaggerated for clarity, but as a schematic illustration should not be considered to reflect strictly the geometric scaling.

Where reference is made to the drawings as a schematic illustration of an idealized embodiment of the present invention, the illustrated embodiment of the present invention should not be construed as limited to the particular shapes of regions illustrated in the drawings but are to include resultant shapes such as deviations caused by manufacturing. Fig. 1 is a flowchart of a method for manufacturing a resistive random access memory according to an embodiment of the present invention. Meanwhile, the manufacturing process of each part of the resistive random access memory is illustrated by fig. 2 to 5, and the method for manufacturing the resistive random access memory is described in detail below with reference to fig. 2 to 5.

Step S1: a lower electrode is formed on a substrate, and a functional layer is formed on the lower electrode.

Substep S11: a lower electrode is formed on a substrate.

Fig. 2 is a schematic diagram of a process for preparing a lower electrode of a resistive random access memory according to an embodiment of the present invention, and as shown in fig. 2, the step specifically includes: and depositing a lower electrode on the silicon wafer through photoetching and stripping. The lower electrode can adopt Pt, W, Ru, Al, conductive metal compounds TiN, TaN and IrO₂At least one of ITO and IZO. The lower electrode material can be prepared by one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition and sputtering methods.

Substep S12: a functional layer is formed on the upper surface of the lower electrode.

Fig. 3 is a schematic diagram of a process for preparing a functional layer of a resistive random access memory according to an embodiment of the present invention, as shown in fig. 3, in this step, a functional layer is deposited on a lower electrode, where the functional layer may be SiO₂、HfO₂、Al₂O₃、TaO_x、TiO_xAnd the like. The functional layer can be prepared by magnetron sputtering, pulsed laser deposition, atomic layer deposition and the like.

Step S2: and carrying out ion implantation on the functional layer.

Fig. 4 is a schematic view of an ion implantation process of the resistive random access memory according to the embodiment of the present invention, as shown in fig. 4, in this step, ion implantation is performed on the functional layer, and the implantation material may be Ag, Cu, Cr, W, or the like.

Step S3: an upper electrode is formed on the functional layer.

Fig. 5 is a schematic diagram of a process of preparing an upper electrode of a resistive random access memory according to an embodiment of the present invention, and as shown in fig. 5, the step specifically includes: and depositing an upper electrode on the functional layer by photoetching and stripping. The upper electrode can adopt Pt, W, Ru, Al, conductive metal compounds TiN, TaN and IrO₂At least one of ITO and IZO. The upper electrode material can be prepared by one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition and sputtering.

Fig. 6 shows the I-V curve measurement results of the resistance change memory. As can be seen from the figure: the voltage increases from zero to V_thThe device is always in the high resistance state. Continue to increase voltage (> V)_th) The current suddenly increases sharply and increases with increasing voltage up to V_set. When the voltage value continues to increase beyond V_setWhen the current decreases with increasing voltage up to V_minAnd the resistance obtained in the section can still be kept under the condition of power failure, so that the gradual and gradual RESET process is realized. This phenomenon occurs because ion implantation into the functional layer forms a series of discrete metal particles, and electrons are trapped and released by these metal particles at different voltages. When the voltage value is larger than the starting voltage V for the tunneling of electrons among the particles_thWhen electrons are trapped by metal particles by tunneling and thus more easily transported, a sudden increase in current is caused. As the voltage continues to increase (> V)_th) A sufficiently large voltage causes the metal particles to release electrons resulting in a reduction of the current and thus a graded RESET.

Fig. 7 shows a practical diagram of the resistance random access memory using different pulse RESET amplitudes to realize different resistance states, thereby realizing the tolerance of multi-value storage. As can be seen from the figure: (1V/1 ms pulse is used to Set the device to the low resistance state R_onThen applying a differenceRESET pulse (-2V/0.2ms, -3V/0.2ms, -4V/0.2ms) can respectively obtain different resistance states R_off1，R_off2，R_off3. The device can thus apply a pulse switching resistance more than 100 times. )

So far, the process of the preparation method of the resistive random access memory capable of realizing the multi-value storage shown in fig. 1 is completed. By utilizing the invention, the functional layer is subjected to ion implantation so as to form a series of discontinuous metal particles, the uniform and gradual RESET process can be realized, the multi-value storage of a single device can be realized by regulating and controlling the RESET voltage, and the storage density is greatly improved. Through the control of RESET cut-off voltage, a larger storage window is formed between resistance states of the obtained multi-value storage, and the design difficulty of a peripheral read-write circuit is facilitated to be simplified.

Many widely different embodiments may be made of the invention without departing from the spirit and scope thereof. It should be understood that the invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A resistive random access memory preparation method for realizing multi-value storage is characterized by comprising the following steps:

s2: carrying out ion implantation on the functional layer to form discontinuous metal particles in the functional layer;

s3: forming an upper electrode on the functional layer;

the lower electrode material comprises Ru, TaN and IrO₂ITO or IZO;

the functional layer material comprises Al₂O₃Or TiO_x；

The ion implantation material used in step S2 includes Ag, Cu, Cr, or W.

2. The method of claim 1, wherein the lower electrode material further comprises Pt, W, Al, or TiN.

3. The method of claim 1, wherein the functional layer material further comprises SiO₂、HfO₂Or TaO_x。

4. The production method according to claim 1, wherein the functional layer is formed on the lower electrode by magnetron sputtering, pulsed laser deposition, or atomic layer deposition.

5. The method according to claim 1, wherein the upper electrode material is Pt, W, Ru, Al, TiN, TaN, IrO₂At least one of ITO and IZO.

6. The method of claim 1, wherein in step S1, the lower electrode is deposited on the substrate by photolithography and lift-off.

7. The method of claim 1, wherein in step S3, the upper electrode is deposited on the functional layer by photolithography and lift-off.

8. The method of claim 6 or 7, wherein the upper and lower electrodes are fabricated by one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or sputtering.

9. The method of claim 1, wherein the substrate is a silicon wafer.