CN105932035A - Gating device for resistive random access memory crossbar array and preparation method thereof - Google Patents
Gating device for resistive random access memory crossbar array and preparation method thereof Download PDFInfo
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- CN105932035A CN105932035A CN201610275550.3A CN201610275550A CN105932035A CN 105932035 A CN105932035 A CN 105932035A CN 201610275550 A CN201610275550 A CN 201610275550A CN 105932035 A CN105932035 A CN 105932035A
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- oxide
- gating device
- solid dielectric
- electrode
- random access
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
Abstract
The invention discloses a gating device for a resistive random access memory crossbar array and a preparation method thereof. The gating device comprises a bottom-layer noble electrode, an oxide-based solid dielectric and a top-layer active electrode from the bottom up. According to the gating device, by selecting a resistive random access memory based on a metal conductive filament mechanism, by adjusting density and structure of the oxide-based solid dielectric and diffusivity of the active metal in the dielectric, the device forms a conductive filament channel under a forward voltage, and the device is in a low resistance state; after voltage releases, a conductive filament fuses spontaneously, the device returns to a high resistance state; and in the following negative voltage scanning process, the device keeps in the high resistance state. The device presents a behavior similar to rectification operation of a diode, and the gating device can be used for the resistive random access memory crossbar array. The gating device is good in compatibility with the resistive random access memory in preparation process, is simple in structure, large in rectification ratio and low in power consumption, and is capable of suppressing crosstalk in the resistive random access memory crossbar array structure effectively.
Description
Technical field
The invention belongs to microelectronics technology, be specifically related to a kind of for resistance variant memory crossover array
Gating device and preparation method thereof.
Background technology
Resistance-variable storing device (RRAM) has simple in construction, read or write speed is fast, it is low in energy consumption to operate, it is close to store
Spend big and existing CMOS technology technical compatibility, potentiality further scaled down are big, it is many to realize
The features such as value storage, therefore, it is the contenders of general-purpose storage of future generation.
In order to improve memory density further, cross array structure (Crossbar) is considered as a kind of letter
Single effective integration mode, and, by crossed array is carried out three-dimensional stacked, can increase exponentially
The memory density of device, maximum storage density is 4F in theory2/ N, (F is characterized live width, and N is heap
Lamination number).But, during the data stored in reading cross array structure, there is serious serial data
Disturb problem.As it is shown in figure 1, in simple 2 × 2 cross array structures, if variable-resistance memory unit
A is in high-impedance state and other three variable-resistance memory unit are in low resistance state, now, is reading high resistant
During the state of state unit A, electric current will be in the memory cell of low resistance state and form one along adjacent three
Bar leak channel, as shown in phantom in fig. 1 so that the resistance value read out is low resistance state, and not
It is the high-impedance state of unit A, the most so-called cross-interference issue.When array density is the biggest, cross-interference issue is then
Even more serious.For solving this problem, it usually needs by resistance-variable storing device and a gating device (crystal
Pipe, diode etc.) series connection, form one resistive device (1T1R) of a transistor, a diode
One resistive device (1D1R) structure.Wherein, 1D1R has higher memory density and is especially closed
Note.But, traditional diode technological temperature is higher, incompatible with the preparation technology of resistive device,
Further, the commutating ratio of conventional diode is the highest, and electric current density is relatively low.
Summary of the invention
It is an object of the invention to solve above-mentioned technical problem, it is provided that a kind of resistive that is used for is deposited
The gating device of reservoir crossed array.This gating device has similar with oxide-base resistance-variable storing device
Structure and preparation technology, thus splendid with the preparation technology compatibility of resistive device, and height can be obtained
Reach 107Commutating ratio.
For reaching above-mentioned purpose, operation principle based on metallic conduction filament mechanism, the present invention is used for hindering
The gating device of variant memory crossover array includes bottom inert electrode the most successively, is located at bottom
Oxide-base solid dielectric on inert electrode, the top layer active electrode being located on solid dielectric.
Described bottom inert electrode includes but are not limited to the one in Pt, W, Au, TiN, thickness
For 5nm～500nm.
Described oxide-base solid dielectric is hafnium oxide, titanium oxide, zirconium oxide, tungsten oxide, oxygen
Change in tantalum one or more, thickness is 5nm～200nm.
Described top layer active electrode includes but are not limited to the one in Ag, Cu, Ni, and thickness is
5nm～500nm.
As preferably, described bottom inert electrode is Pt bottom electrode, and oxide-base solid dielectric is
ZrO2Solid dielectric, top layer active electrode is Ag electrode.
In such scheme, the operation principle of gating device is as follows: top layer active electrode applies forward electricity
Pressure, and control current limliting, in anodizing formation metal ion implantation to solid dielectric, (formation is led
Electricity filament channel, device becomes low resistance state (by adjusting the density of oxide-base solid dielectric, knot
Structure and active metal diffusivity in the dielectric so that it is thin that device forms conduction under forward voltage
Silk passage)；And after release voltage, conductive filament is unstable and spontaneous melting occurs, device returns to height
Resistance state, in negative voltage scanning process subsequently, device keeps high-impedance state.Device presents similar two
The rectification behavior of pole pipe, can be used for the gating device of resistance variant memory crossover array.
In such scheme, forward voltage is in the range of 1～5V, and current limliting is in the range of 100nA～10mA.
Another object of the present invention is to provide a kind of gate for resistance variant memory crossover array
The preparation method of part, the method includes:
Step S1: forming bottom inert electrode in substrate top surface, bottom inert electrode can use electronics
Beam evaporation, chemical gaseous phase deposition (including PECVD, LPCVD, MOCVD etc.), pulsed laser deposition,
Ald (ALD) or magnetically controlled sputter method deposit, and depositing temperature is room temperature, thickness be 5nm～
500nm；
Step S2: by electron beam evaporation, chemical gaseous phase deposition, pulsed laser deposition, atomic layer deposition
Long-pending, spin coating or sputtering method, form oxide-base solid-state electricity at described bottom inert electrode upper surface and be situated between
Matter, thickness is 5nm～200nm；
Step S3: forming electrode in activity at described oxide-base solid dielectric upper surface, electrode can
Electron beam evaporation, chemical gaseous phase deposition (including PECVD, LPCVD, MOCVD etc.), pulse is used to swash
Light deposition, ald (ALD) or magnetically controlled sputter method deposit, and depositing temperature is room temperature, thick
Degree is 5nm～500nm.
Described substrate is silicon substrate or glass substrate or other flexible substrate.
The invention has the beneficial effects as follows:
A kind of gating device for resistance variant memory crossover array that the present invention proposes, mainly uses gold
Belonging to oxide material, its simple in construction, low cost of manufacture, preparation technology holds concurrently with the technique of resistive device
Capacitive is good, and device can under bigger current limliting steady operation, can effectively solve conventional diode with
A difficult problem for resistive device processing compatibility difference, the cross-interference issue in suppression crossed array.
Accompanying drawing explanation
Fig. 1 is cross-interference issue schematic diagram in resistance variant memory crossover array；
Fig. 2 is the knot of the gating device for resistance variant memory crossover array according to the embodiment of the present invention
Structure schematic diagram；
Fig. 3 is to make the gating device for resistance variant memory crossover array according to the embodiment of the present invention
Method flow diagram；
Fig. 4 is the Ag/ZrO according to the embodiment of the present invention2/ Pt gating device is under 100 μ A current limlitings
Current-voltage characteristic curve；
Fig. 5 is the Ag/ZrO according to the embodiment of the present invention2/ Pt gating device is in 10 μ A～10mA current limliting
In the range of current-voltage characteristic curve.
Detailed description of the invention
Below in conjunction with the accompanying drawings and embodiment, the detailed description of the invention of the present invention is carried out apparent, complete
Whole description.In order to clearly be exaggerated the thickness of layer and region, but should not be considered as schematic diagram
Strictly reflect the proportionate relationship of physical dimension.Described embodiment is served only for illustrating the present invention, at this not
The scope of protection of the invention should be limited.
Fig. 2 is the knot of the gating device for resistance variant memory crossover array according to the embodiment of the present invention
Structure schematic diagram, this gating device includes: substrate 100, and substrate 100 is preferably silicon substrate, it is possible to
To be glass or some flexible substrate.The bottom inert electrode 101 being formed on substrate 100；Bottom
Inert electrode 101 can be the one of Pt, W, Au, TiN, and thickness is 5nm～500nm.It is located at
Oxide-base solid dielectric 102 on bottom inert electrode；102 can be hafnium oxide, titanium oxide,
Zirconium oxide, tungsten oxide, tantalum oxide or their combination, thickness is 5nm～200nm.Oxide-base is solid
State electrolyte be by electron beam evaporation, chemical gaseous phase deposition, pulsed laser deposition, ald,
Prepared by the one in spin coating or sputtering method.The top layer active electrode 103 being located on solid dielectric.
103 can be the one of Ag, Cu, Ni, and thickness is 5nm～500nm.
As preferred embodiment, the gate for resistance variant memory crossover array that the present embodiment provides
Part includes Pt bottom electrode, ZrO2Solid dielectric, and Ag top layer active electrode.Below in conjunction with Fig. 3,
Describe the preparation technology flow process of this gating device in detail.
Step S1, forms inertia hearth electrode 101.As it is shown on figure 3, hearth electrode Pt uses electron beam
The method of evaporation is formed, and its thickness is 5nm～500nm.
Step S2, forms ZrO on hearth electrode 101 layers2Solid dielectric layer 102.In the present embodiment
The method using electron beam evaporation forms ZrO at ambient temperature2Solid dielectric layer, its thickness is 50
nm。
Step S3, at ZrO2Forming upper electrode layer 103 on solid dielectric layer, Ag electrode uses magnetic
The method of control sputtering is formed, and its thickness is 5nm～500nm.
Fig. 4 is the Ag/ZrO of the embodiment of the present invention2/ Pt gating device electric current under 100 μ A current limlitings
-voltage response.In test process, active electrode Ag electrode one end adds forward scan voltage, inertia
Electrode Pt ground connection, during voltage scanning, limits size of current and is set to 100 μ A, when sweeping
Retouching voltage when increasing to about 0.25V, device current increases suddenly, forms conductive filament, turn in device
Become low resistance state, but, this low resistance state can not stably keep, when voltage is gradually reduced, and device electricity
Flowing down fall, device is spontaneous returns to high-impedance state, shows volatile characteristic.In negative voltage subsequently
In scanning process, device remains high-impedance state.Therefore, Ag/ZrO based on conductive filament2/ Pt selects
The current-voltage characteristic curve of logical device is similar with the rectification curve of diode, this device ±
Commutating ratio under 0.1V voltage is 104.Therefore, can intersect for resistance-variable storing device as gating device
Array.
Fig. 5 is the Ag/ZrO according to the embodiment of the present invention2/ Pt gating device limits at 10 μ A～10mA
Current-voltage characteristic curve in the range of stream.Visible device, when up to 10mA current limliting, still shows
For volatile characteristic, commutating ratio can increase to 10 along with the increase of current limliting7。
The above is only presently preferred embodiments of the present invention, not the present invention is made any in form
Restriction.Therefore, for those skilled in the art, without departing from skill of the present invention
On the premise of art principle, to any simple modification made for any of the above embodiments, equivalent variations and modification,
All still fall within the range of technical solution of the present invention protection.
Claims (9)
1. the gating device for resistance variant memory crossover array, it is characterised in that depend on from bottom to top
The oxide-base solid dielectric of secondary include bottom inert electrode, being located on bottom inert electrode, be located at solid
Top layer active electrode on state electrolyte.
2. the preparation method of gating device as claimed in claim 1, it is characterised in that the method includes
Following steps:
Step S1: form bottom inert electrode in substrate top surface；
Step S2: form oxide-base solid dielectric at described bottom inert electrode upper surface；
Step S3: form electrode in activity at described oxide-base solid dielectric upper surface.
3. gating device as claimed in claim 1 or the method described in claim 2, its feature exists
Including but are not limited to the one in Pt, W, Au, TiN in described bottom inert electrode, thickness is
5nm～500nm.
4. gating device as claimed in claim 1 or the method described in claim 2, its feature exists
It is hafnium oxide, titanium oxide, zirconium oxide, tungsten oxide, tantalum oxide in described oxide-base solid dielectric
In one or more, thickness is 5nm～200nm.
5. gating device as claimed in claim 1 or the method described in claim 2, its feature exists
Include but are not limited to the one in Ag, Cu, Ni in described top layer active electrode, thickness be 5nm～
500nm。
6. gating device as claimed in claim 1, it is characterised in that top layer active electrode is just being applied
To voltage, and control current limliting, in anodizing formation metal ion implantation to solid dielectric, formed
Conductive filament passage, device becomes low resistance state, and after release voltage, conductive filament is unstable and occurs certainly
Sending out and melt, device returns to high-impedance state, and in negative voltage scanning process subsequently, device keeps high-impedance state,
Device presents the rectification behavior of similar diode.
7. gating device as claimed in claim 6, it is characterised in that forward voltage in the range of 1～5V,
Current limliting is in the range of 100nA～10mA.
8. method as claimed in claim 2, it is characterised in that described substrate is silicon substrate or glass
Substrate or other flexible substrate.
9. method as claimed in claim 2, it is characterised in that step S2 uses electron beam evaporation, change
Learn vapour deposition, pulsed laser deposition, ald, spin coating or sputtering method, form oxide-base
Solid dielectric.
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| CN201610275550.3A CN105932035A (en) | 2016-04-28 | 2016-04-28 | Gating device for resistive random access memory crossbar array and preparation method thereof |
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| CN201610275550.3A CN105932035A (en) | 2016-04-28 | 2016-04-28 | Gating device for resistive random access memory crossbar array and preparation method thereof |
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| CN113066928A (en) * | 2021-03-23 | 2021-07-02 | 南京工业大学 | Polymer gating device and preparation method thereof |
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| CN113224236A (en) * | 2021-05-11 | 2021-08-06 | 山东大学 | Transparent double-layer-structure memristor and preparation method thereof |
| CN114068781A (en) * | 2021-11-15 | 2022-02-18 | 扬州乾照光电有限公司 | Light emitting device |
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| CN113224236A (en) * | 2021-05-11 | 2021-08-06 | 山东大学 | Transparent double-layer-structure memristor and preparation method thereof |
| CN114068781A (en) * | 2021-11-15 | 2022-02-18 | 扬州乾照光电有限公司 | Light emitting device |
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