CN102903845B - Resistive random access memory and manufacture method thereof - Google Patents
Resistive random access memory and manufacture method thereof Download PDFInfo
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- CN102903845B CN102903845B CN201210333457.5A CN201210333457A CN102903845B CN 102903845 B CN102903845 B CN 102903845B CN 201210333457 A CN201210333457 A CN 201210333457A CN 102903845 B CN102903845 B CN 102903845B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of the switching material, e.g. layer deposition
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/041—Modification of the switching material, e.g. post-treatment, doping
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
Abstract
The invention provides a resistive random access memory having a leakage-restraining characteristic and a manufacture method thereof. The resistive random access memory can restrain Sneak current in a cross-shaped array of a large-scale resistive random access memory (RRAM). A memorizing unit forming the resistive random access memory comprises a lower electrode, a first semiconductor oxide layer, a resistive random access material layer, a second semiconductor oxide layer and an upper electrode which are stacked in sequence. A semiconductor oxide can be a semiconductor metallic oxide or semiconductor nonmetal oxide. The resistive random access memory can effectively reduce the Sneak current through a Schottky barrier formed by the semiconductor oxide and metal electrodes, is simple in manufacture process and can achieve high integration level of a device.
Description
Technical field
The invention belongs to nonvolatile memory (Nonvolatile memory) technical field in cmos vlsi (ULSI), be specifically related to a kind of to there is the resistance-variable storing device and preparation method thereof suppressing leakage current characteristic.
Background technology
Solid-state memory plays very important role in advanced information society, mostly has its existence in our electronic product used in everyday.Existing memory is mainly DRAM and FLASH, and along with the development of semi-conductor industry, device size constantly reduces, and memory will narrow down to its physics limit, after particularly entering into 22nm technology node, can not meet the demand storing development.Resistance-variable storing device (RRAM) because of its have structure simple, can High Density Integration, preparation temperature low, with the advantage such as CMOS rear end compatibility, high speed operation, low-power consumption and become that memory of future generation is strong to be competed.For the high-density city of RRAM, people tend to use cross array structure integrated, store can realize to make the super-high density of resistance-variable storing device three-dimensional.
Traditional cross array structure as shown in Figure 1, is the bottom electrode 13 (bit line) and N number of top electrode 11(wordline be parallel to each other that to be parallel to each other by M) square crossing and being formed, each mutual infall is a RRAM memory cell 12.Fig. 2 is the structural representation of RRAM memory cell in prior art, comprises electrode of metal 21, resistive material 22 and lower metal electrode 23.Its operation principle is: under initial condition, and resistive material is high-impedance state.When getting to certain voltage between two-plate, the electric current between pole plate sharply increases, and resistive material becomes low-resistance, and voltage is now called Vset.After institute's making alive is a certain value, the electric current between two-plate sharply diminishes again, and voltage is now called Vreset.Its 2 states storing information are high resistant (" 0 ") and low-resistance (" 1 ").Because it is add identical voltage to read the size of current flowing through this device and carry out determining device and be in high resistant or low resistance state that device resistance reads what mainly lean on.If a device in right-angled intersection array be in high value state and device around it is in low resistive state time, will impact the correct reading of this high value device resistance.When this is owing to reading high-resistance device, institute's making alive can be walked around this high resistant and form Sneak electric current on low resistance device, Sneak electric current on this low-resistance device will be far longer than the electric current flow through on high-resistance device, now, read the actual Sneak electric current for low resistance device around it of ohmically reading electric current, therefore, high resistance measurement device can be judged as low resistivity value resistor part, misreading and and misoperation of device can be caused.The further raising of this architecture array integration density of Sneak current limit in this array; And this electric current not only can cause misreading of device resistance state in array, and can increase the power consumption of array entirety.
At present, in order to address this problem, people propose to utilize 1D1R(1 diode to add a RRAM) structure to be to suppress the generation of Sneak electric current.Diode is mainly divided into silicon-based diode and metal oxide based diode.But silicon-based diode preparation temperature is high, and MOS diode easily changes RRAM into and loses its rectification characteristic.In addition, the drive current of diode is lower, can not meet the user demand of RRAM device, is therefore necessary to propose a kind of new structure to suppress Sneak electric current.
Summary of the invention
The object of the invention is to for the problems referred to above, propose a kind of to there is the resistance-variable storing device and preparation method thereof suppressing leakage current characteristic, the Sneak electric current in extensive RRAM right-angled intersection array can be suppressed.
For achieving the above object, the present invention adopts following technical scheme:
A kind of variable-resistance memory unit, comprises the bottom electrode, the first semi-conductor type oxide skin(coating), resistive material layer, the second semi-conductor type oxide skin(coating) and the top electrode that superpose successively.
Described semi-conductor type oxide can be semi-conductor type metal oxide, such as titanium oxide (TiOx), nickel oxide (NiOx), also can be semi-conductor type nonmetal oxide.
Described resistive material layer has the transition metal oxide of resistive characteristic, perovskite oxide, rare metal oxide or ferromagnetic material etc.
Described electrode is metal electrode or polysilicon electrode, and such as, top electrode is chosen as titanium nitride (TiN), and bottom electrode is chosen as platinum (Pt).
A kind of resistance-variable storing device, comprises multiple variable-resistance memory unit as above.
A preparation method for variable-resistance memory unit, its step comprises:
1) substrate is prepared;
2) at described substrate surface depositing metal bottom electrode;
3) deposit first semi-conductor type oxide skin(coating) on described bottom electrode;
4) deposit resistive material layer on described first semi-conductor type oxide skin(coating), and carry out annealing in process;
5) deposit second semi-conductor type oxide skin(coating) on described resistive material layer;
6) depositing metal top electrode on described second semi-conductor type oxide skin(coating).
Preferably, step 2) and step 6) adopt magnetically controlled sputter method carry out described deposit; Step 3) to step 5) uses reactive sputtering method to carry out described deposit.
The RRAM structure that the present invention proposes is consistent with capacity plate antenna structure, respectively at resistive material with add layer of semiconductor type oxide between top electrode and bottom electrode, can effectively reduce Sneak electric current by the Schottky barrier formed between semi-conductor type oxide and metal electrode.Its manufacture craft of RRAM structure of the present invention easily realizes, and bottom electrode and top electrode can be adopted to form the structure of square crossing (cross-bar), and the infall of each top electrode and hearth electrode forms RRAM memory cell, can realize the high integration of device.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of RRAM right-angled intersection array structure in prior art, wherein: 11. wordline; 12.RRAM unit; 13. bit lines.
Fig. 2 is the structural representation of RRAM memory cell in prior art, wherein: 21. electrode of metal; 22. resistive material layers; 23. lower metal electrode.
Fig. 3 is the structural representation of RRAM memory cell in the embodiment of the present invention, wherein: 31. electrode of metal; 32. first semi-conductor type metal oxide layers; 33. resistive materials; 34. second metal oxide semiconductors; 35. lower metal electrode.
Embodiment
Below by specific embodiment, and coordinate accompanying drawing, the present invention is described further.
Fig. 3 is the structural representation of the RRAM memory cell of resistance-variable storing device in the present embodiment, and this RRAM memory cell comprises electrode of metal 31; Semi-conductor type metal oxide 32; Resistive material 33; Metal oxide semiconductor 34; Lower metal electrode 35.Because semi-conductor type metal oxide is semi-conductor type, Schottky barrier can be formed between electrode of metal 31 and metal oxide semiconductor 32 and between metal oxide semiconductor 34 and lower metal electrode 35.When RRAM device is in low-resistance, due to the existence of Schottky barrier, the device current flow through is diminished, therefore effectively reduce the generation of Sneak electric current under less voltage.
Illustrate the preparation process of above-mentioned RRAM memory cell below.This RRAM memory cell is using TaOx as resistive material, and its device architecture is (TiN/TiOx/TaOx/TiOx/Pt):
1. substrate preparation: use Si(100) substrate, above by the SiO2 of oxidation growth thick layer about 1000 dust.
2. prepare bottom electrode: at the certain thickness photoresist of serrated substrate surface spin coating, exposure definition lower electrode arrangement figure.With magnetron sputtering depositing metal bottom electrode Pt(35 after development), thickness of electrode is 100-200nm.Then peel off and form platinum electrode.
3. deposit first semi-conductor type metal oxide layer: after bottom electrode completes, then at use reactive sputtering deposit TiOx(34 on SiO2 film), thickness is 5nm-10nm.
4. deposit resistive material: TiOx(34) complete after, then at use reactive sputtering deposit resistive thereon material TaOx(33), resistive material thickness is 10-60nm, and then at 400 DEG C, anneal in oxygen atmosphere 1h.
5. deposit second semi-conductor type metal oxide layer: TaOx(33) complete after, then at use reactive sputtering deposit TiOx(32 thereon), thickness is 5nm-10nm.
6. deposit top electrode: at TiOx(32) upper spin coating photoresist, exposure definition intermediate electrode structure figure.Magnetron sputtering apparatus depositing metal top electrode electrode TiN(31 is used after development), thickness of electrode is 100nm-200nm.Photoresist is removed with acetone.Then peel off and form TiN metal electrode.
Above-described embodiment is only illustrate for convenience of explanation, and protection scope of the present invention should be as the criterion with described in claims, but not is only limitted to above-described embodiment.
Claims (3)
1. a preparation method for variable-resistance memory unit, its step comprises:
1) substrate is prepared;
2) at described substrate surface depositing metal bottom electrode;
3) deposit first semi-conductor type oxide skin(coating) on described bottom electrode, forms Schottky barrier between described bottom electrode and described first semi-conductor type oxide skin(coating);
4) deposit resistive material layer on described first semi-conductor type oxide skin(coating), and carry out annealing in process;
5) deposit second semi-conductor type oxide skin(coating) on described resistive material layer;
6) depositing metal top electrode on described second semi-conductor type oxide skin(coating), forms Schottky barrier between described top electrode and described second semi-conductor type oxide skin(coating);
Described bottom electrode is Pt, and its thickness is 100-200nm; The described very TiN that powers on, its thickness is 100nm-200nm; Described resistive material is TaOx, and its thickness is 10-60nm; Described semi-conductor type oxide is TiOx, and its thickness is 5nm-10nm.
2. the method for claim 1, is characterized in that: step 2) and step 6) adopt magnetically controlled sputter method to carry out described deposit; Step 3) to step 5) use reactive sputtering method to carry out described deposit.
3. method as claimed in claim 1 or 2, is characterized in that, step 4) technique of described annealing is: 400 DEG C, oxygen atmosphere, 1h.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210333457.5A CN102903845B (en) | 2012-09-10 | 2012-09-10 | Resistive random access memory and manufacture method thereof |
| US14/360,596 US9214629B2 (en) | 2012-09-10 | 2013-04-26 | Resistive memory and method for fabricating the same |
| PCT/CN2013/074760 WO2014036837A1 (en) | 2012-09-10 | 2013-04-26 | Resistive random access memory and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210333457.5A CN102903845B (en) | 2012-09-10 | 2012-09-10 | Resistive random access memory and manufacture method thereof |
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| Publication Number | Publication Date |
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| CN102903845A CN102903845A (en) | 2013-01-30 |
| CN102903845B true CN102903845B (en) | 2015-05-13 |
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| CN201210333457.5A Expired - Fee Related CN102903845B (en) | 2012-09-10 | 2012-09-10 | Resistive random access memory and manufacture method thereof |
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| Country | Link |
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| US (1) | US9214629B2 (en) |
| CN (1) | CN102903845B (en) |
| WO (1) | WO2014036837A1 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102903845B (en) | 2012-09-10 | 2015-05-13 | 北京大学 | Resistive random access memory and manufacture method thereof |
| KR102244116B1 (en) * | 2014-09-25 | 2021-04-26 | 인텔 코포레이션 | 1s1r memory cells incorporating a barrier layer |
| WO2016137449A1 (en) | 2015-02-24 | 2016-09-01 | Hewlett Packard Enterprise Development Lp | Determining resistance states of memristors in a crossbar array |
| CN105720195B (en) * | 2016-04-21 | 2018-07-31 | 南京理工大学 | A kind of inorganic halogen perovskite resistance-variable storing device and preparation method thereof |
| US10468458B2 (en) | 2016-05-10 | 2019-11-05 | Winbond Electronics Corp. | Resistive random access memory having selector and current limiter structures |
| US10340449B2 (en) * | 2017-06-01 | 2019-07-02 | Sandisk Technologies Llc | Resistive memory device containing carbon barrier and method of making thereof |
| CN107425116A (en) * | 2017-06-05 | 2017-12-01 | 西安电子科技大学 | Resistance-variable storing device based on cushion and preparation method thereof |
| CN107180913A (en) * | 2017-06-20 | 2017-09-19 | 深圳大学 | Non-volatile type memorizer and preparation method based on the organic perovskite material of metal |
| CN108376737A (en) * | 2018-01-24 | 2018-08-07 | 西安交通大学 | A method of preparing high on-off ratio TaOx resistive random access memory |
| US11641787B2 (en) | 2018-03-28 | 2023-05-02 | Institute of Microelectronics, Chinese Academy of Sciences | Self-rectifying resistive memory and fabrication method thereof |
| CN108922965B (en) * | 2018-07-24 | 2020-01-31 | 湖北大学 | resistive random access memory based on perovskite material and preparation method thereof |
| TWI679757B (en) * | 2019-02-15 | 2019-12-11 | 力晶積成電子製造股份有限公司 | Resistive random access memory and manufacturing method thereof |
| CN111146341A (en) * | 2020-01-02 | 2020-05-12 | 集美大学 | Preparation method of resistive random access memory with space limitation effect |
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| CN101101964A (en) * | 2006-07-06 | 2008-01-09 | 三星电子株式会社 | Non-volatile memory device including a variable resistance material |
| CN101667460A (en) * | 2009-10-12 | 2010-03-10 | 中国科学院微电子研究所 | One-time programmable memory based on variable-resistance memory and preparation method thereof |
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| KR101051704B1 (en) * | 2004-04-28 | 2011-07-25 | 삼성전자주식회사 | Memory device using multilayer with resistive gradient |
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| KR20120016044A (en) * | 2009-03-27 | 2012-02-22 | 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. | Switchable junction with intrinsic diode |
| US8502343B1 (en) * | 2010-11-17 | 2013-08-06 | The University Of Toledo | Nanoelectric memristor device with dilute magnetic semiconductors |
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| CN102593351A (en) * | 2012-01-20 | 2012-07-18 | 北京大学 | Low-power-consumption resistive random access memory structure and manufacturing method thereof |
| CN102903845B (en) | 2012-09-10 | 2015-05-13 | 北京大学 | Resistive random access memory and manufacture method thereof |
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2012
- 2012-09-10 CN CN201210333457.5A patent/CN102903845B/en not_active Expired - Fee Related
-
2013
- 2013-04-26 US US14/360,596 patent/US9214629B2/en not_active Expired - Fee Related
- 2013-04-26 WO PCT/CN2013/074760 patent/WO2014036837A1/en active Application Filing
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| CN101030623A (en) * | 2006-02-27 | 2007-09-05 | 三星电子株式会社 | Electrode structure having at least two oxide layers and non-volatile memory device having the same |
| CN101097935A (en) * | 2006-06-28 | 2008-01-02 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
| CN101101964A (en) * | 2006-07-06 | 2008-01-09 | 三星电子株式会社 | Non-volatile memory device including a variable resistance material |
| CN101667460A (en) * | 2009-10-12 | 2010-03-10 | 中国科学院微电子研究所 | One-time programmable memory based on variable-resistance memory and preparation method thereof |
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| Publication number | Publication date |
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| US9214629B2 (en) | 2015-12-15 |
| CN102903845A (en) | 2013-01-30 |
| WO2014036837A1 (en) | 2014-03-13 |
| US20140306173A1 (en) | 2014-10-16 |
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