CN101989644A - Method for improving data retention capacity of resistor random memory - Google Patents
Method for improving data retention capacity of resistor random memory Download PDFInfo
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- CN101989644A CN101989644A CN200910055813XA CN200910055813A CN101989644A CN 101989644 A CN101989644 A CN 101989644A CN 200910055813X A CN200910055813X A CN 200910055813XA CN 200910055813 A CN200910055813 A CN 200910055813A CN 101989644 A CN101989644 A CN 101989644A
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Abstract
The invention provides a method for improving data retention capacity of a resistor random memory, which belongs to the technical field of semiconductor memories. By the method, a medium thin film layer is inserted between an electrode of the resistor random memory and a metallic oxide storage medium layer so that the data retention capacity of the resistor random memory is improved greatly.
Description
Technical field
The invention belongs to the semiconductor memory technologies field, be specifically related to a kind of resistance random access memory, relate in particular to a kind of by inserting the method that metal oxide layer or metal layer of oxynitride improve the resistance random access memory data holding ability.
Background technology
The traditional non-volatility memorizer spare that with Flash is representative has been obtained great success, but along with constantly the reducing of process, Flash is about to arrive its physics limit.For developing follow-on nonvolatile memory substitute technology, some novel memory technologies are developing just vigorously.Resistance random access memory (RRAM) is the most dazzling a kind of in these novel non-volatile memory technologies.Resistance random access memory utilizes the resistance of storage medium under signal of telecommunication effect, but the characteristic of inverse conversion is come storage signal between high resistant and low-resistance.Resistance random access memory is because scaled (scaling down) ability of its excellence, perfect compatible with standard logic process, and preparation technology is simple, has very strong cost advantage, therefore, resistance random access memory is considered to a kind of of tool potentiality in the non-volatile memory technology of future generation.Yet resistance random access memory is really moving towards also to need to overcome a lot of obstacles before the application, and wherein very crucial a bit is to improve its data holding ability (data retention), especially in the Embedded Application field.
Figure 1 shows that the resistance random memory unit schematic diagram of traditional sandwich structure.As shown in Figure 1.With the 1T1R structure is example, its formation method generally is to form after transistorized grid 12, gate dielectric 14 and the source/drain regions 16 on silicon substrate 10 earlier, cover last layer dielectric layer 20 again, in dielectric layer 20, form the end that contact hole connector 22 is connected to source/drain regions 16 then, on contact hole connector 22, form resistive memory cell at last.Traditional resistive memory cell is to pile up from bottom to top with " planar fashion ", forms metallic oxide storage medium layer 26 on bottom electrode 24, and forms top electrode 28 on metallic oxide storage medium layer 26.At first, suppose that this resistance random memory unit is not programmed, for this memory cell of programming, need be with bottom electrode 24 ground connection, and apply positive voltage to top electrode 28, make that current potential Vpg (" programming " current potential) is that forward direction (forward direction) with memory cell is applied to the memory cell two ends.The Vpg current potential forms conductive filament (filament) in metallic oxide storage medium layer 26, cause metallic oxide storage medium layer 26 to enter low resistive state (Low Resistance State).After removing the Vpg current potential, do not rupture at the Filament that forms before, make the metallic oxide storage medium layer still remain on low resistive state.In like manner, in order to wipe this resistance random memory unit, usually need apply positive voltage to bottom electrode 28, and top electrode 24 is kept ground connection, make that current potential Ver (" wiping " current potential) is reverse (reverse) the square memory cell two ends that are applied to resistance random memory unit.The conductive filament (filament) that the Joule heat that the Ver current potential produces in storage material layer 26 is enough to form fuses, and causes storage material layer 26 to enter high-impedance state (High Resistance State).After removing the Ver current potential, belong to the oxide storage medium layer and still remain on high-impedance state.The retention time of resistance random access memory its low resistance state or high-impedance state at read/program potential or after wiping current potential and removing is defined as data holding ability (data retention).
Figure 2 shows that disclosed another the resistor accidental memory structure schematic diagram of Chinese patent.As shown in Figure 2, Chinese patent application number is a kind of resistance random access memory that discloses in the CN200710043707.9 patent, wherein, 40 is substrate, 41 is the bottom electrode of resistance random access memory, 46 is the metallic oxide storage medium layer, and 45 is top electrode, and 46 is the dielectric film between top electrode and metallic oxide storage medium layer.Resistance random access memory shown in Figure 2 than resistance random access memory shown in Figure 1 many one deck dielectric film 26, utilize the high resistant characteristic of dielectric film, the higher Joule heat of its generation reduces reset operation (Reset also is " wiping " operation) electric current of resistance random access memory.
Obviously, be to improve the actual application ability of resistance random access memory, we wish resistance random access memory be programmed the back or be wiped free of after have a good data hold facility.Therefore, necessaryly provide a kind of method that improves the data holding ability of resistance random access memory.
Summary of the invention
The technical problem to be solved in the present invention is to improve the data holding ability of resistance random access memory.
For solving the problems of the technologies described above, the invention provides a kind of method that improves the data holding ability of resistance random access memory, its resistance random access memory comprises bottom electrode, metallic oxide storage medium layer, top electrode, its method feature is, inserts the dielectric film layer between the electrode of described resistance random access memory and metallic oxide storage medium layer.
As first embodiment wherein, between the top electrode of described resistance random access memory and metallic oxide storage medium layer, insert one deck dielectric film layer.Described dielectric film layer is metal oxide or metal oxynitride, and the metallic element in described metal oxide or the metal oxynitride is identical with the metallic element of described top electrode.Described metal oxide or metal oxynitride can form by the method for thin film deposition; Described metal oxide or metal oxynitride also can diffuse to top electrode by the oxygen element in the metallic oxide storage medium layer forms the top electrode oxidation.
As second embodiment wherein, between the bottom electrode of described resistance random access memory and metallic oxide storage medium layer, insert one deck dielectric film layer.Described dielectric film layer is metal oxide or metal oxynitride, and the metallic element in described metal oxide or the metal oxynitride is identical with the metallic element of described bottom electrode.Described metal oxide or metal oxynitride can form by the method for thin film deposition; Described metal oxide or metal oxynitride can diffuse to bottom electrode by the oxygen element in the metallic oxide storage medium layer forms the bottom electrode oxidation.
As the 3rd embodiment wherein, between the top electrode of described resistance random access memory and metallic oxide storage medium layer, insert ground floor dielectric film layer, between the bottom electrode of described resistance random access memory and metallic oxide storage medium layer, all insert second layer dielectric film layer simultaneously.Described ground floor dielectric film layer is metal oxide or metal oxynitride, and the metallic element in its metal oxide or the metal oxynitride is identical with the metallic element of described top electrode; Described second layer dielectric film layer is metal oxide or metal oxynitride, and the metallic element in its metal oxide or the metal oxynitride is identical with the metallic element of described bottom electrode.Described metal oxide or metal oxynitride can be given birth to by the method for thin film deposition and be formed; Described metal oxide or metal oxynitride also can diffuse to electrode by the oxygen element in the metallic oxide storage medium layer forms bottom electrode or bottom electrode oxidation.
According to the method for the data holding ability of raising resistance random access memory provided by the invention, wherein, described dielectric film layer is metal oxide or metal oxynitride.Metallic element in described metal oxide or the metal oxynitride is different from the metallic element in the metallic oxide storage medium layer.One of the oxide of the oxide that described metallic oxide storage medium layer is a copper, the oxide of nickel, titanyl compound, zirconium, the oxide of zinc, oxide of tungsten.It is characterized in that, described upper electrode material is one of Ta, Ti, TaN, TiN, Cu, Al, Pt, W, Ni, Ru, Ru-Ta alloy, Pt-Ti alloy, Ni-Ta alloy, or the composite material of both combinations arbitrarily in Ta, Ti, TaN, TiN, Cu, Al, Pt, W, Ni, Ru, Ru-Ta alloy, Pt-Ti alloy, the Ni-Ta alloy.Described lower electrode material is one of Cu, W, Ni, Zr, Ta, TaN, Ti, TiN, Zn, Al.The thickness range of described thin film dielectrics layer is that 1 nanometer is to 20 nanometers.
Technique effect of the present invention is, by between the electrode of resistance random access memory and metallic oxide storage medium layer, inserting the dielectric film layer, the dielectric film layer can play the hole in prevention filament easy fracture zone to electrode diffusion when low resistance state, thereby impels resistance random access memory to remain on low resistance state; Simultaneously, the dielectric film layer can play the oxygen room that stops trapped hole and re-move the region of fracture to filament when high-impedance state, thereby impels resistance random access memory to remain on high-impedance state; Therefore, use the data holding ability of the resistance random access memory of this method to improve greatly.
Description of drawings
Fig. 1 is the resistance random memory unit schematic diagram of traditional sandwich structure;
Fig. 2 is disclosed another the resistor accidental memory structure schematic diagram of Chinese patent;
Fig. 3 is the resistor accidental memory structure schematic diagram that forms by the first embodiment method;
Fig. 4 is that the low resistance state principle of resistance random access memory among Fig. 3 embodiment is explained schematic diagram;
Fig. 5 is that the high-impedance state principle of resistance random access memory among Fig. 3 embodiment is explained schematic diagram;
Fig. 6 is the resistor accidental memory structure schematic diagram that forms by the second embodiment method;
Figure 7 shows that the resistor accidental memory structure schematic diagram that forms by the 3rd embodiment method;
Fig. 8 forms resistance random access memory data retention characteristics schematic diagram at room temperature according to the first embodiment method provided by the invention;
Fig. 9 is that the low resistance state of foundation first embodiment provided by the invention toasts the data retention characteristics schematic diagram that obtains under three kinds of different temperatures;
Figure 10 is the data retention characteristics schematic diagram of deriving and under the Arrhenius equation according to Fig. 9 experimental data.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.In the drawings, for convenience of description, amplified the thickness in layer and zone, shown in size do not represent actual size.
Reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of etching has crooked or mellow and full characteristics usually, but in embodiments of the present invention, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.
First embodiment of the method for raising resistance random access memory data holding ability provided by the invention inserts the dielectric film layer between the top electrode of resistance random access memory and metallic oxide storage medium layer.Figure 3 shows that the resistor accidental memory structure schematic diagram that forms by the first embodiment method.As shown in Figure 3, on the substrate 200 successively composition form bottom electrode 202, metallic oxide storage medium layer 204, dielectric film layer 206 and top electrode 208.The material of bottom electrode 202 can be Cu, W, Ni, Zr, Ta, TaN, Ti, TiN, Zn or Al, can use physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or electrochemical deposition methods such as (ECP) to form, the thin layer thickness of bottom electrode 202 is not limited by the present invention.The material of metallic oxide storage medium layer can be one of the oxide of the oxide of copper, nickel, titanyl compound, the oxide of zirconium, the oxide of zinc, oxide of tungsten, they all have variable resistance characteristics, promptly externally under the signal of telecommunication effect, can change back and forth in different Resistance states; In this embodiment, be preferably CuxO, wherein 1＜x≤2; Preferably, if lower electrode material is Cu, can be by bottom electrode being carried out the method formation CuxO metallic oxide storage medium layer that thermal oxidation or plasma oxidation are handled.The thickness range of dielectric film layer 206 is that 1 nanometer is to 20 nanometers, in this embodiment, dielectric film layer 206 is metal oxide or metal oxynitride, and is identical with metallic element in the top electrode 208 as the metal oxide of dielectric film layer or the metallic element in the metal oxynitride.Dielectric film layer 206 can form by the mode of deposition on metallic oxide storage medium layer 204, for example, form dielectric film layer 206 by physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or ald methods such as (ALD) deposition.Preferably, in this embodiment, can the top electrode oxidation be formed by the diffusion of the oxygen element in metallic oxide storage medium layer top electrode; For example, when if the metallic oxide storage medium layer is CuxO, when forming top electrode TaN in the above, the interface place of TaN and CuxO, can autoxidation form the very thin TaON layer of one deck, thickness is about 3 nanometers, and this is to form owing to the oxygen element among the CuxO diffuses among the TaN, the power of this diffusion comes from the oxygen concentration difference of CuxO and TaN, perhaps comes from the activity difference of Ta metal and Cu metal.The TaON layer is a kind of as dielectric film layer 206, and the data holding ability that improves resistance random access memory is being played crucial effect.Top electrode 208 is one of Ta, Ti, TaN, TiN, Cu, Al, Pt, W, Ni, Ru, Ru-Ta alloy, Pt-Ti alloy, Ni-Ta alloy, or the composite material of both combinations arbitrarily in Ta, Ti, TaN, TiN, Cu, Al, Pt, W, Ni, Ru, Ru-Ta alloy, Pt-Ti alloy, the Ni-Ta alloy; It can use physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or electrochemical deposition methods such as (ECP) to form, and the thin layer thickness of top electrode 208 is not limited by the present invention.
Further, in conjunction with Fig. 3, the method principle that first embodiment is improved data holding ability is described further.In this embodiment, be CuxO, power on very that TaN, dielectric film layer are that TaON is an example with the metallic oxide storage medium layer.The natural number of drawbacks that exists in the CuxO storage medium film is such as oxygen room, copper room and local attitude etc.After resistance random access memory is programmed by the signal of telecommunication, can form conductive channel filament between top electrode and bottom electrode, the formation of filament is because the comprehensive function that move in the oxygen room of extraneous charge carrier that injects of CuxO storage medium layer and CuxO storage medium layer inside.If adopt forward programming (being to apply positive voltage on the top electrode), what inject so is the hole, and what form promptly also that the defective of filament captures is the hole; If adopt negative sense programming (being to apply positive voltage on the bottom electrode), what inject so is electronics, and what form promptly also that the defective of filament captures is electronics.In the present embodiment, be suitable for the forward programming, what therefore inject is the hole.Again owing to the distribution of oxygen content in the CuxO film of oxidation formation is generally successively decreased from top to bottom gradually, so the filament that forms becomes the distribution of falling the spindle, as shown in Figure 4.Obviously, because quantity is more, need the long time just can lose near the hole in the filament zone of bottom electrode; The zone that so most possibly causes losing efficacy is exactly the filament zone near top electrode, and the existence of TaON dielectric film layer has just in time stopped this regional hole electrode diffusion that makes progress.Therefore, can improve the data holding ability of resistance random access memory low resistance state significantly by this embodiment.When resistance random access memory was erased to high-impedance state, filament was in breaking state (as shown in Figure 5), and the zone of fracture is positioned at top electrode and CuxO film contact position.The maximum likelihood that high-impedance state lost efficacy be among TaON or the CuxO the oxygen room of trapped hole move to filament fracture place and make filament form again, but because the contact position of TaON self and TaON and CuxO all has higher barrier height, therefore, the oxygen room of trapped hole is difficult for moving to the contact position of TaON and CuxO, thereby cause filament to be difficult for forming again, the data that help high-impedance state keep.Therefore, also can improve the data holding ability of Memister high-impedance state significantly by this embodiment.In a word, can improve the data holding ability of Memister significantly by this embodiment.
Need to prove, above mechanism explain is not those skilled in the art's a common practise, but the discovery that studies for a long period of time by the inventor, therefore, those skilled in the art are also unexpected by increasing the data holding ability that the dielectric film layer can improve resistance random access memory.This mechanism explain also is not limited only to CuxO storage medium and TaN top electrode embodiment, also can go to explain with similar mechanism for other metallic oxide storage medium layer and electrode of metal.
Second embodiment of the method for raising resistance random access memory data holding ability provided by the invention inserts the dielectric film layer between the bottom electrode of resistance random access memory and metallic oxide storage medium layer.Figure 6 shows that the resistor accidental memory structure schematic diagram that forms by the second embodiment method.As shown in Figure 6, form bottom electrode 302, dielectric film layer 306, metallic oxide storage medium layer 304 and top electrode 308 on the substrate 300 successively.The material of bottom electrode 302 can be Cu, W, Ni, Zr, Ta, TaN, Ti, TiN, Zn or Al, can use physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or electrochemical deposition methods such as (ECP) to form, the thin layer thickness of bottom electrode 302 is not limited by the present invention.The material of metallic oxide storage medium layer 304 can be one of the oxide of the oxide of copper, nickel, titanyl compound, the oxide of zirconium, the oxide of zinc, oxide of tungsten, they all have variable resistance characteristics, promptly externally under the signal of telecommunication effect, can change back and forth in different Resistance states; In this embodiment, be preferably CuxO, wherein 1＜x≤2; Preferably, if lower electrode material is Cu, can be by bottom electrode being carried out the method formation CuxO metallic oxide storage medium layer that thermal oxidation or plasma oxidation are handled.The thickness range of dielectric film layer 306 be 1 nanometer to 20 nanometers, in this embodiment, dielectric film layer 306 is metal oxide or metal oxynitride
In this embodiment, dielectric film layer 306 is metal oxide or metal oxynitride, and is identical with metallic element in the bottom electrode 202 as the metal oxide of dielectric film layer 306 or the metallic element in the metal oxynitride.Dielectric film layer 306 can form by the mode with deposition on bottom electrode 302, for example, forms dielectric film layer 306 by physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or ald methods such as (ALD) deposition.Preferably, in this embodiment, can the bottom electrode oxidation be formed by the diffusion of the oxygen element in the metallic oxide storage medium layer 306 bottom electrode; For example, if when bottom electrode is TaN, when sputter in the above forms the metallic oxide storage medium layer and is CuxO, the interface place of TaN and CuxO, can autoxidation form the very thin TaON layer of one deck, thickness is about 3 nanometers, and this is to form owing to the oxygen element among the CuxO diffuses among the TaN.The TaON layer is a kind of as dielectric film layer 306, and the data holding ability that improves resistance random access memory is being played crucial effect.Top electrode 308 is one of Ta, Ti, TaN, TiN, Cu, Al, Pt, W, Ni, Ru, Ru-Ta alloy, Pt-Ti alloy, Ni-Ta alloy, or the composite material of both combinations arbitrarily in Ta, Ti, TaN, TiN, Cu, Al, Pt, W, Ni, Ru, Ru-Ta alloy, Pt-Ti alloy, the Ni-Ta alloy; It can use physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or electrochemical deposition methods such as (ECP) to form, and the thin layer thickness of top electrode 308 is not limited by the present invention.
The resistance random access memory of second embodiment shown in Figure 6 is improved the method principle of data holding ability, the method principle of the resistance random access memory raising data holding ability of basic and first embodiment shown in Figure 3 is identical, just dielectric film layer 306 is had an effect between bottom electrode and metallic oxide storage medium, is suitable for negative sense programming (bottom electrode applies forward voltage when promptly programming) relatively.
The 3rd embodiment of the method for raising resistance random access memory data holding ability provided by the invention is between the bottom electrode and metallic oxide storage medium layer of resistance random access memory, insert the dielectric film layer simultaneously between top electrode and the metallic oxide storage medium layer.Figure 7 shows that the resistor accidental memory structure schematic diagram that forms by the 3rd embodiment method.Figure as shown in Figure 7, on the substrate 400 successively composition form bottom electrode 402, the second dielectric film layer 406b, metallic oxide storage medium layer 404, the first dielectric film layer 406a and top electrode 408.The material of bottom electrode 402 can be Cu, W, Ni, Zr, Ta, TaN, Ti, TiN, Zn or Al, can use physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or electrochemical deposition methods such as (ECP) to form, the thin layer thickness of bottom electrode 402 is not limited by the present invention.The material of metallic oxide storage medium layer 404 can be one of the oxide of the oxide of copper, nickel, titanyl compound, the oxide of zirconium, the oxide of zinc, oxide of tungsten, they all have variable resistance characteristics, promptly externally under the signal of telecommunication effect, can change back and forth in different Resistance states; In this embodiment, be preferably CuxO, wherein 1＜x≤2; Preferably, can form by the mode of sputter.The second dielectric film layer 406b is between bottom electrode 402 and metallic oxide storage medium layer 404, the thickness range of the second dielectric film layer 406b is that 1 nanometer is to 20 nanometers, in this embodiment, the second dielectric film layer 406b is metal oxide or metal oxynitride.The second dielectric film layer 406b can form by the mode of deposition on lower electrode layer 402, for example, form the second dielectric film layer 406b by physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or ald methods such as (ALD) deposition.Preferably, in this embodiment, can the bottom electrode oxidation be formed by the diffusion of the oxygen element in metallic oxide storage medium layer bottom electrode; For example, if when bottom electrode is TaN, when sputter in the above forms the metallic oxide storage medium layer and is CuxO, the interface place of TaN and CuxO, can autoxidation form the very thin TaON layer of one deck, thickness is about 3 nanometers, and this is to form owing to the oxygen element among the CuxO diffuses among the TaN.The TaON layer is a kind of as the second dielectric film layer 406b's, and the data holding ability that improves resistance random access memory is being played crucial effect.Top electrode 408 is one of Ta, Ti, TaN, TiN, Cu, Al, Pt, W, Ni, Ru, Ru-Ta alloy, Pt-Ti alloy, Ni-Ta alloy, or the composite material of both combinations arbitrarily in Ta, Ti, TaN, TiN, Cu, Al, Pt, W, Ni, Ru, Ru-Ta alloy, Pt-Ti alloy, the Ni-Ta alloy; It can use physical sputtering, chemical reaction sputter, physical vapor deposition, chemical vapor deposition or electrochemical deposition methods such as (ECP) to form, and the thin layer thickness of top electrode 408 is not limited by the present invention.In like manner, the first dielectric film layer 406a between top electrode 408 and metallic oxide storage medium layer 404 can to have an attribute identical with the second dielectric film layer 406b, and its formation method also can be identical.
The resistance random access memory of second embodiment shown in Figure 7 is improved the method principle of data holding ability, the method principle of the resistance random access memory raising data holding ability of basic and first embodiment shown in Figure 3 is identical, layer 2-only dielectric film layer have an effect between bottom electrode and the metallic oxide storage medium, simultaneously ground floor dielectric film layer is also had an effect between top electrode and metallic oxide storage medium, is suitable for two kinds of programming modes of positive negative sense relatively.
Figure 8 shows that according to the first embodiment method provided by the invention and form resistance random access memory data retention characteristics schematic diagram at room temperature.At first, 100 memory cell of picked at random and with its " programming " to low resistance state, 100 memory cell of picked at random and it " is wiped " to high-impedance state in addition.Then at room temperature, read the resistance of these 200 memory cell every 1000s.Two typical high-impedance states of state representation among Fig. 8 and the time dependent change in resistance situation of low resistance state.As can be seen from the figure, the typical resistance of the high-impedance state of this resistance memory cell and low resistance state is respectively 3k ohm and 200k ohm.At room temperature, the resistance of high low resistance state does not have change substantially, can keep very long a period of time.
Figure 9 shows that the low resistance state according to first embodiment provided by the invention toasts the data retention characteristics schematic diagram that obtains under three kinds of different temperatures.At first, 100 memory cell of picked at random and with its " programming " to low resistance state, 100 memory cell of picked at random and it " is wiped " to high-impedance state in addition, and these 200 memory cell are classified as first group.Then, we make to use the same method and form second group and the 3rd group, and each organizes all 200 memory cell of picked at random, wherein 100 " programmings " to low resistance state, other 100 " wiping " are to high-impedance state.Then, respectively as for toasting under three different steady temperatures in the vacuum drying oven, select 110 degree here with these three groups of memory cell, 125 degree and 135 degree.After every baking a period of time, these three groups of memory cell are taken out and be cooled to room temperature after read its resistance, in finding every group low resistance state, have till 20% the storage-unit-failure.So-called " inefficacy " also promptly becomes high-impedance state by low resistance state, perhaps becomes low resistance state by high-impedance state.As can be seen from the figure, corresponding to 110 degree, the time of low resistance state 20% failure rate of toasting under 125 degree and the 135 degree temperature is respectively 4 * 10
6Second, 8 * 10
5Second, 2 * 10
5Second.We find that the stability of high-impedance state obviously is better than low resistance state simultaneously.
Figure 10 shows that the data retention characteristics schematic diagram of under the Arrhenius equation, deriving and according to Fig. 9 experimental data.Figure 10 is the data holding ability of this structure memory cell of deriving the pairing out-of-service time of low resistance state 20% failure rate under three different temperatures that draw according to Fig. 9 to come out under the Arrhenius equation.As can be seen from Figure 10, the data holding ability of this structure memory cell is 90.5 degree 10 years, is much better than the useful life in 10 years of 85 degree of present report.
The Arrhenius equation is as follows:
Wherein, t is the stoving time of memory cell in vacuum drying oven, and Ea is an activation energy, and κ is a Boltzmann constant, and T is the baking temperature in the vacuum drying oven.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the specification.
Claims (19)
1. method that improves the resistance random access memory data holding ability, described resistance random access memory comprises bottom electrode, metallic oxide storage medium layer, top electrode, it is characterized in that, between the electrode of described resistance random access memory and metallic oxide storage medium layer, insert the dielectric film layer.
2. method according to claim 1 is characterized in that, inserts one deck dielectric film layer between the top electrode of described resistance random access memory and metallic oxide storage medium layer.
3. method according to claim 1 is characterized in that, inserts one deck dielectric film layer between the bottom electrode of described resistance random access memory and metallic oxide storage medium layer.
4. method according to claim 1, it is characterized in that, between the top electrode of described resistance random access memory and metallic oxide storage medium layer, insert ground floor dielectric film layer, between the bottom electrode of described resistance random access memory and metallic oxide storage medium layer, all insert second layer dielectric film layer simultaneously.
5. according to claim 1 or 2 or 3 or 4 described methods, it is characterized in that described dielectric film layer is metal oxide or metal oxynitride.
6. method according to claim 1 is characterized in that the metallic element in described metal oxide or the metal oxynitride is different from the metallic element in the metallic oxide storage medium layer.
7. method according to claim 2 is characterized in that, described dielectric film layer is metal oxide or metal oxynitride, and the metallic element in described metal oxide or the metal oxynitride is identical with the metallic element of described top electrode.
8. method according to claim 7 is characterized in that, described metal oxide or metal oxynitride form by the method for thin film deposition.
9. method according to claim 7 is characterized in that, described metal oxide or metal oxynitride diffuse to top electrode by the oxygen element in the metallic oxide storage medium layer forms the top electrode oxidation.
10. method according to claim 3 is characterized in that, described dielectric film layer is metal oxide or metal oxynitride, and the metallic element in described metal oxide or the metal oxynitride is identical with the metallic element of described bottom electrode.
11. method according to claim 10 is characterized in that, described metal oxide or metal oxynitride are given birth to by the method for thin film deposition and are formed.
12. method according to claim 10 is characterized in that, described metal oxide or metal oxynitride diffuse to bottom electrode by the oxygen element in the metallic oxide storage medium layer forms the bottom electrode oxidation.
13. method according to claim 4 is characterized in that, described ground floor dielectric film layer is metal oxide or metal oxynitride, and the metallic element in its metal oxide or the metal oxynitride is identical with the metallic element of described top electrode; Described second layer dielectric film layer is metal oxide or metal oxynitride, and the metallic element in its metal oxide or the metal oxynitride is identical with the metallic element of described bottom electrode.
14. method according to claim 13 is characterized in that, described metal oxide or metal oxynitride are given birth to by the method for thin film deposition and are formed.
15. method according to claim 13 is characterized in that, described metal oxide or metal oxynitride diffuse to electrode by the oxygen element in the metallic oxide storage medium layer forms bottom electrode or bottom electrode oxidation.
16. method according to claim 1 is characterized in that, one of the oxide of the oxide that described metallic oxide storage medium layer is a copper, the oxide of nickel, titanyl compound, zirconium, the oxide of zinc, oxide of tungsten.
17. method according to claim 1, it is characterized in that, described upper electrode material is one of Ta, Ti, TaN, TiN, Cu, Al, Pt, W, Ni, Ru, Ru-Ta alloy, Pt-Ti alloy, Ni-Ta alloy, or the composite material of both combinations arbitrarily in Ta, Ti, TaN, TiN, Cu, Al, Pt, W, Ni, Ru, Ru-Ta alloy, Pt-Ti alloy, the Ni-Ta alloy.
18. method according to claim 1 is characterized in that, described lower electrode material is one of Cu, W, Ni, Zr, Ta, TaN, Ti, TiN, Zn, Al.
19. method according to claim 1 is characterized in that, the thickness range of described thin film dielectrics layer is that 1 nanometer is to 20 nanometers.
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| CN102820428A (en) * | 2012-09-11 | 2012-12-12 | 同济大学 | Improved oxide-film resistance changing memory and improvement method thereof |
| CN104979470A (en) * | 2014-04-02 | 2015-10-14 | 台湾积体电路制造股份有限公司 | Rram cell bottom electrode formation |
| CN105024011A (en) * | 2014-04-18 | 2015-11-04 | 华邦电子股份有限公司 | Resistive random access memory and manufacturing method thereof |
| CN105280810A (en) * | 2014-06-11 | 2016-01-27 | 华邦电子股份有限公司 | Resistance type random access memory and manufacturing method thereof |
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