CN106803515A - 半导体功率器件的终端结构及其制造方法 - Google Patents
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Abstract
本发明公开了一种半导体功率器件的终端结构，包括：多个P型场限环；介质隔离条将P型场限环之间的N型半导体材料表面完全覆盖；SIPOS层覆盖在各P型场限环的表面上并延伸到介质隔离条表面上；在SIPOS层表面覆盖有介质保护层。SIPOS层和P型场限环直接接触，SIPOS层和N型半导体材料间隔有所述介质隔离条，本发明通过介质隔离条来减少SIPOS层和底部半导体材料接触的面积从而减少漏电，通过SIPOS层和P型场限环直接接触来提高耐压一致性。本发明还公开了一种半导体功率器件的终端结构的制造方法。本发明能降低终端漏电，提高器件耐压以及耐压一致性，工艺简单。
Description
技术领域
本发明涉及半导体集成电路制造领域，特别是涉及一种半导体功率器件的终端结构，本发明还涉及一种半导体功率器件的终端结构的制造方法。
背景技术
功率半导体器件的性能与其终端表面钝化技术密切相关，半绝缘多晶硅(Semi-Insulating Polycrystalline Silicon,SIPOS)是一种含氧或氮的多晶硅或非晶硅薄膜钝化材料，具有半绝缘特性，它能够屏蔽终端区域硅表面电荷或离子沾污以及外电场，提高PN结反向击穿电压和高温反向偏压(High Temperature ReverseBias，HTRB)可靠性。SIPOS薄膜一般采用低压化学气相沉积方法(Low PressureChemical Vapor Deposition,LPCVD)制备，已广泛用于双极型晶体管(如NPN晶体管和PNP晶体管)、金属氧化物半导体场效应晶体管(Metal-Oxide-SemiconductorField-Effect Transistor，MOSFET)、绝缘栅双极型晶体管(Insulated Gate BipolarTransistor，IGBT)以及快恢复二极管(Fast Recovery diode，FRD)等半导体功率器件制造工艺。
如图1所示，是现有第一种半导体功率器件的终端结构的截面示意图；可以参考申请号为201380021704.0的中国专利申请，包括：N型轻掺杂单晶硅衬底101，IGBT的主结或P阱区102，变化横向P型掺杂区(Varied Lateral Doding，VLD)103，SIPOS层104，SIPOS层104的介质保护层105。IGBT的其它与终端关系不大的结构部分省略。但如图1所示的第一种终端结构的不足之处是对SIPOS工艺要求严格控制，容易引起较大的反向漏电流，这是由于这种终端结构中SIPOS层104与底部的硅表面有较大的接触面积引起的。
现有第二种半导体功率器件的终端结构能够参考申请号为201210345440.1的中国专利申请，第二种终端结构采用高阻SIPOS层/二氧化硅层/低阻SIPOS层等复合薄膜钝化超结MOSFET，但SIPOS层/硅的接触面积并没有减少，且工艺复杂，对高阻SIPOS质量要求严格控制，还是容易引起较大的反向漏电流。
如图2所示，是现有第三种半导体功率器件的终端结构的截面示意图；包括：N型轻掺杂单晶硅衬底201，半导体功率器件的主结或P阱区202，在终端区采用二氧化硅层203/SIPOS层204/二氧化硅层205的三层复合薄膜钝化，在终端区的最外侧设置有沟道截止环206，半导体功率器件的有源区的主结或P阱区202通过金属接触孔207引出，沟道截止环206也通过一个金属接触孔207引出。第三种结构的SIPOS层204和底部硅并不接触而是隔离有二氧化硅层203，该结构电场强度分布密切依赖SIPOS层204的性能，器件耐压一致性较差。随着功率器件的电压等级越高，终端占用面积越大，需要SIPOS层204钝化的面积越大，终端漏电以及耐压一致性问题越来越突出。
发明内容
本发明所要解决的技术问题是提供一种半导体功率器件的终端结构，能降低终端漏电，提高器件耐压以及耐压一致性，工艺简单。为此，本发明还提供一种半导体功率器件的终端结构的制造方法。
为解决上述技术问题，本发明提供的半导体功率器件的终端结构环绕在半导体功率器件的有源区的周侧，所述终端结构包括：
多个P型场限环，形成于N型半导体材料中；在俯视面上，各所述P型场限环呈环形结构并环绕在所述有源区的周侧，相邻的所述P型场限环之间间隔有所述N型半导体材料。
介质隔离条将各相邻的所述P型场限环之间的所述N型半导体材料表面完全覆盖。
SIPOS层覆盖在各所述P型场限环的表面上并延伸到所述介质隔离条表面上。
在所述SIPOS层表面覆盖有介质保护层。
所述SIPOS层和所述P型场限环直接接触，所述SIPOS层和所述N型半导体材料间隔有所述介质隔离条，通过所述介质隔离条来减少所述SIPOS层和底部半导体材料接触的面积从而减少漏电，通过所述SIPOS层和所述P型场限环直接接触来提高耐压一致性。
进一步的改进是，所述SIPOS层的厚度为0.2微米～1微米，所述SIPOS层的含氧量或含氮量为5％～35％。
进一步的改进是，所述介质保护层为氮化硅薄膜；或者，所述介质保护层为氮化硅和二氧化硅的复合薄膜；所述介质保护层的厚度为0.2微米～1微米。
进一步的改进是，各所述P型场限环的宽度为2微米～20微米、深度为3微米～70微米。
进一步的改进是，各所述介质隔离条还延伸到邻近的所述P型场限环的表面上，各所述介质隔离条的每一侧延伸到邻近的所述P型场限环的表面上的横向距离为0.5微米～2微米；各相邻的所述介质隔离条间的间距为1微米～19微米；各所述介质隔离条的厚度为0.3微米～3微米。
进一步的改进是，所述半导体材料为硅、锗、砷化镓、碳化硅或氮化镓。
进一步的改进是，所述介质隔离条为二氧化硅条。
进一步的改进是，所述半导体功率器件为快速恢复二极管、金属氧化物半导体场效应晶体管、绝缘栅双极型晶体管和双极型晶体管。
进一步的改进是，所述半导体功率器件为具有超结结构。
为解决上述技术问题，本发明提供的半导体功率器件的终端结构的制造方法中终端结构环绕在半导体功率器件的有源区的周侧，采用如下步骤形成所述终端结构：
步骤一、采用光刻工艺、P型离子注入工艺以及热扩散工艺在N型半导体材料的选定位置形成多个P型场限环；在俯视面上，各所述P型场限环呈环形结构并环绕在所述有源区的周侧，相邻的所述P型场限环之间间隔有所述N型半导体材料。
步骤二、在形成有所述P型场限环的半导体材料表面形成介质隔离层。
步骤三、采用光刻工艺打开后续形成的SIPOS层和各所述P型场限环的接触区域，采用刻蚀工艺去除光刻工艺打开的接触区域的所述介质隔离层形成介质隔离条，所述介质隔离条将各相邻的所述P型场限环之间的所述N型半导体材料表面完全覆盖。
步骤四、形成SIPOS层，所述SIPOS层覆盖在各所述P型场限环的表面上并延伸到所述介质隔离条表面上。
所述SIPOS层和所述P型场限环直接接触，所述SIPOS层和所述N型半导体材料间隔有所述介质隔离条，通过所述介质隔离条来减少所述SIPOS层和底部半导体材料接触的面积从而减少漏电，通过所述SIPOS层和所述P型场限环直接接触来提高耐压一致性。
步骤五、形成介质保护层，所述介质保护层覆盖在所述SIPOS层表面。
进一步的改进是，步骤四中采用LPCVD工艺形成所述SIPOS层，所述SIPOS层的厚度为0.2微米～1微米，所述SIPOS层的含氧量或含氮量为5％～35％。
进一步的改进是，步骤五中采用LPCVD工艺形成所述介质保护层，所述介质保护层为氮化硅薄膜；或者，所述介质保护层为氮化硅和二氧化硅的复合薄膜；所述介质保护层的厚度为0.2微米～1微米。
本发明具有如下有益技术效果：
首先、本发明通过在终端区即终端结构区域设置多个P型场限环，P型场限环本身能够使得终端区的电场强度分布均匀，能提高器件的耐压和一致性；所以本发明通过优化P型场限环的数目、宽度、间距、深度以及掺杂浓度能很好的提高器件的耐压和一致性。
其次、本发明通过P型场限环和其之间的N型半导体材料具有交替排列的关系，同设置介质隔离条完全覆盖P型场限环之间的N型半导体材料，之后再形成SIPOS层，使得SIPOS层仅和P型场限环的半导体材料直接接触，SIPOS层和P型场限环之间的N型半导体材料则通过介质隔离条隔离。这样相对于现有第一种和第二种终端结构，本发明能够大大减少SIPOS层和底部半导体材料的接触面积，这样能够减少器件的反向漏电流，也即相同的SIPOS工艺条件下本发明的反向漏电流更小。而相对于现有第三种终端结构，由于本发明的SIPOS层和P型场限环直接接触，能够避免SIPOS层和底部半导体材料完全隔离时所带来的耐压一致性差的问题，所以本发明能够提高器件的耐压性。
另外，本发明还具有工艺简单的优点。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1是现有第一种半导体功率器件的终端结构的截面示意图；
图2是现有第三种半导体功率器件的终端结构的截面示意图；
图3是本发明实施例半导体功率器件的终端结构的截面示意图；
图4是本发明实施例半导体功率器件的终端结构的俯视图；
图5A-图5E是本发明实施例半导体功率器件的终端结构的制造方法的各步骤中的截面示意图。
具体实施方式
如图3所示，是本发明实施例半导体功率器件的终端结构的截面示意图；如图4所示，是本发明实施例半导体功率器件的终端结构的俯视图；本发明实施例半导体功率器件的终端结构在半导体功率器件的有源区5的周侧，有源区5形成有半导体器件的元胞结构，P阱2为半导体器件的有源区的最外侧的P阱，有源区内部的其它结构省略。本发明实施例中，所述半导体功率器件为快速恢复二极管、金属氧化物半导体场效应晶体管、绝缘栅双极型晶体管和双极型晶体管；所述半导体功率器件还能具有超结结构。
所述终端结构包括：
多个P型场限环4，形成于N型半导体材料1中。本发明实施例中所述半导体材料1为硅；在其它实施例中，所述半导体材料1也能为锗、砷化镓、碳化硅或氮化镓。
在俯视面上，各所述P型场限环4呈环形结构并环绕在所述有源区5的周侧，相邻的所述P型场限环4之间间隔有所述N型半导体材料1。较佳选择为，各所述P型场限环4的宽度为2微米～20微米、深度为3微米～70微米；通过优化P型场限环的数目、宽度、间距、深度以及掺杂浓度，可使终端内电场强度分布均匀，提高器件耐压和一致性；所以本发明实施例中，环的深度、宽度以及环间距是根据具体器件电压等级设计。
介质隔离条3将各相邻的所述P型场限环4之间的所述N型半导体材料1表面完全覆盖。较佳选择为，各所述介质隔离条3还延伸到邻近的所述P型场限环4的表面上，各所述介质隔离条3的每一侧延伸到邻近的所述P型场限环4的表面上的横向距离为0.5微米～2微米；各相邻的所述介质隔离条3间的间距为1微米～19微米；各所述介质隔离条3的厚度为0.3微米～3微米。所述介质隔离条3为二氧化硅条。
SIPOS层6覆盖在各所述P型场限环4的表面上并延伸到所述介质隔离条3表面上。较佳选择为，所述SIPOS层6的厚度为0.2微米～1微米，所述SIPOS层6的含氧量或含氮量为5％～35％。
在所述SIPOS层6表面覆盖有介质保护层7。较佳选择为，所述介质保护层7为氮化硅薄膜；或者，所述介质保护层7为氮化硅和二氧化硅的复合薄膜；所述介质保护层7的厚度为0.2微米～1微米。
所述SIPOS层6和所述P型场限环4直接接触，所述SIPOS层6和所述N型半导体材料1间隔有所述介质隔离条3，通过所述介质隔离条3来减少所述SIPOS层6和底部半导体材料1接触的面积从而减少漏电，通过所述SIPOS层6和所述P型场限环4直接接触来提高耐压一致性。
如图5A至图5E所示，是本发明实施例半导体功率器件的终端结构的制造方法的各步骤中的截面示意图；本发明实施例中，所述半导体功率器件为快速恢复二极管、金属氧化物半导体场效应晶体管、绝缘栅双极型晶体管和双极型晶体管；所述半导体功率器件还能具有超结结构。终端结构环绕在半导体功率器件的有源区5的周侧，本发明实施例方法采用如下步骤形成所述终端结构：
步骤一、如图5A所示，采用光刻工艺、P型离子注入工艺以及热扩散工艺在N型半导体材料1的选定位置形成多个P型场限环4。本发明实施例中所述半导体材料1为硅；在其它实施例中，所述半导体材料1也能为锗、砷化镓、碳化硅或氮化镓。
在俯视面上，各所述P型场限环4呈环形结构并环绕在所述有源区5的周侧，相邻的所述P型场限环4之间间隔有所述N型半导体材料1。本发明实施例中，P型离子注入工艺的注入杂质为硼。各所述P型场限环4的宽度为2微米～20微米、深度为3微米～70微米；通过优化P型场限环的数目、宽度、间距、深度以及掺杂浓度，可使终端内电场强度分布均匀，提高器件耐压和一致性；所以本发明实施例中，环的深度、宽度以及环间距是根据具体器件电压等级设计。
之后，如图5B所示，采用高温氧化方法形成厚度为0.3微米至3微米的场氧化层如二氧化硅场氧化层31。二氧化硅场氧化层31定义出有源区，也即二氧化硅场氧化层31将有源区打开，将终端区覆盖。
采用常规光刻掩膜、二氧化硅蚀刻、P型离子如硼离子注入和热扩散方法形成器件的主结的P阱2。P阱2深度和浓度有IGBT元胞需求决定，一般为3微米～7微米。
完成公知的有源区的多晶硅、N型重掺杂、P型重掺杂和杂质激活等器件有源区工艺。
步骤二、在形成有所述P型场限环4的半导体材料1表面形成介质隔离层3。
本发明实施例中，介质隔离层3为二氧化硅隔离层，采用如下步骤形成：
如图5C所示，采用化学气相沉积方法形成二氧化硅隔离介质层32。
如图5D所示，进行回流退火，由二氧化硅场氧化层31和二氧化硅隔离介质层32叠加形成介质隔离层3。
步骤三、如图5E所示，采用光刻工艺打开后续形成的SIPOS层6和各所述P型场限环4的接触区域，采用刻蚀工艺去除光刻工艺打开的接触区域的所述介质隔离层3形成介质隔离条3，所述介质隔离条3将各相邻的所述P型场限环4之间的所述N型半导体材料1表面完全覆盖。较佳选择为，各所述介质隔离条3还延伸到邻近的所述P型场限环4的表面上，各所述介质隔离条3的每一侧延伸到邻近的所述P型场限环4的表面上的横向距离为0.5微米～2微米；各相邻的所述介质隔离条3间的间距为1微米～19微米；各所述介质隔离条3的厚度为0.3微米～3微米。
步骤四、如图3所示，采用LPCVD工艺方法形成SIPOS层6，所述SIPOS层6覆盖在各所述P型场限环4的表面上并延伸到所述介质隔离条3表面上。所述SIPOS层6和所述P型场限环4直接接触，所述SIPOS层6和所述N型半导体材料1间隔有所述介质隔离条3，通过所述介质隔离条3来减少所述SIPOS层6和底部半导体材料1接触的面积从而减少漏电，通过所述SIPOS层6和所述P型场限环4直接接触来提高耐压一致性。较佳为，所述SIPOS层6的厚度为0.2微米～1微米，所述SIPOS层6的含氧量或含氮量为5％～35％。
步骤五、如图3所示，采用LPCVD工艺方法形成介质保护层7，所述介质保护层7覆盖在所述SIPOS层6表面。较佳选择为，所述介质保护层7为氮化硅薄膜；或者，所述介质保护层7为氮化硅和二氧化硅的复合薄膜；所述介质保护层7的厚度为0.2微米～1微米。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。
Claims (18)
1.一种半导体功率器件的终端结构，终端结构环绕在半导体功率器件的有源区的周侧，其特征在于，所述终端结构包括：
多个P型场限环，形成于N型半导体材料中；在俯视面上，各所述P型场限环呈环形结构并环绕在所述有源区的周侧，相邻的所述P型场限环之间间隔有所述N型半导体材料；
介质隔离条将各相邻的所述P型场限环之间的所述N型半导体材料表面完全覆盖；
SIPOS层覆盖在各所述P型场限环的表面上并延伸到所述介质隔离条表面上；
在所述SIPOS层表面覆盖有介质保护层；
所述SIPOS层和所述P型场限环直接接触，所述SIPOS层和所述N型半导体材料间隔有所述介质隔离条，通过所述介质隔离条来减少所述SIPOS层和底部半导体材料接触的面积从而减少漏电，通过所述SIPOS层和所述P型场限环直接接触来提高耐压一致性。
2.如权利要求1所述的半导体功率器件的终端结构，其特征在于：所述SIPOS层的厚度为0.2微米～1微米，所述SIPOS层的含氧量或含氮量为5％～35％。
3.如权利要求1所述的半导体功率器件的终端结构，其特征在于：所述介质保护层为氮化硅薄膜；或者，所述介质保护层为氮化硅和二氧化硅的复合薄膜；所述介质保护层的厚度为0.2微米～1微米。
4.如权利要求1所述的半导体功率器件的终端结构，其特征在于：各所述P型场限环的宽度为2微米～20微米、深度为3微米～70微米。
5.如权利要求1所述的半导体功率器件的终端结构，其特征在于：各所述介质隔离条还延伸到邻近的所述P型场限环的表面上，各所述介质隔离条的每一侧延伸到邻近的所述P型场限环的表面上的横向距离为0.5微米～2微米；各相邻的所述介质隔离条间的间距为1微米～19微米；各所述介质隔离条的厚度为0.3微米～3微米。
6.如权利要求1所述的半导体功率器件的终端结构，其特征在于：所述半导体材料为硅、锗、砷化镓、碳化硅或氮化镓。
7.如权利要求1或6所述的半导体功率器件的终端结构，其特征在于：所述介质隔离条为二氧化硅条。
8.如权利要求1所述的半导体功率器件的终端结构，其特征在于：所述半导体功率器件为快速恢复二极管、金属氧化物半导体场效应晶体管、绝缘栅双极型晶体管和双极型晶体管。
9.如权利要求8所述的半导体功率器件的终端结构，其特征在于：所述半导体功率器件为具有超结结构。
10.一种半导体功率器件的终端结构的制造方法，终端结构环绕在半导体功率器件的有源区的周侧，其特征在于，采用如下步骤形成所述终端结构：
步骤一、采用光刻工艺、P型离子注入工艺以及热扩散工艺在N型半导体材料的选定位置形成多个P型场限环；在俯视面上，各所述P型场限环呈环形结构并环绕在所述有源区的周侧，相邻的所述P型场限环之间间隔有所述N型半导体材料；
步骤二、在形成有所述P型场限环的半导体材料表面形成介质隔离层；
步骤三、采用光刻工艺打开后续形成的SIPOS层和各所述P型场限环的接触区域，采用刻蚀工艺去除光刻工艺打开的接触区域的所述介质隔离层形成介质隔离条，所述介质隔离条将各相邻的所述P型场限环之间的所述N型半导体材料表面完全覆盖；
步骤四、形成SIPOS层，所述SIPOS层覆盖在各所述P型场限环的表面上并延伸到所述介质隔离条表面上；
所述SIPOS层和所述P型场限环直接接触，所述SIPOS层和所述N型半导体材料间隔有所述介质隔离条，通过所述介质隔离条来减少所述SIPOS层和底部半导体材料接触的面积从而减少漏电，通过所述SIPOS层和所述P型场限环直接接触来提高耐压一致性。
步骤五、形成介质保护层，所述介质保护层覆盖在所述SIPOS层表面。
11.如权利要求10所述的半导体功率器件的终端结构的制造方法，其特征在于：步骤四中采用LPCVD工艺形成所述SIPOS层，所述SIPOS层的厚度为0.2微米～1微米，所述SIPOS层的含氧量或含氮量为5％～35％。
12.如权利要求10所述的半导体功率器件的终端结构的制造方法，其特征在于：步骤五中采用LPCVD工艺形成所述介质保护层，所述介质保护层为氮化硅薄膜；或者，所述介质保护层为氮化硅和二氧化硅的复合薄膜；所述介质保护层的厚度为0.2微米～1微米。
13.如权利要求10所述的半导体功率器件的终端结构的制造方法，其特征在于：各所述P型场限环的宽度为2微米～20微米、深度为3微米～70微米。
14.如权利要求10所述的半导体功率器件的终端结构的制造方法，其特征在于：各所述介质隔离条还延伸到邻近的所述P型场限环的表面上，各所述介质隔离条的每一侧延伸到邻近的所述P型场限环的表面上的横向距离为0.5微米～2微米；各相邻的所述介质隔离条间的间距为1微米～19微米；各所述介质隔离条的厚度为0.3微米～3微米。
15.如权利要求10所述的半导体功率器件的终端结构的制造方法，其特征在于：所述半导体材料为硅、锗、砷化镓、碳化硅或氮化镓。
16.如权利要求10或15所述的半导体功率器件的终端结构的制造方法，其特征在于：所述介质隔离条为二氧化硅条。
17.如权利要求10所述的半导体功率器件的终端结构的制造方法，其特征在于：所述半导体功率器件为快速恢复二极管、金属氧化物半导体场效应晶体管、绝缘栅双极型晶体管和双极型晶体管。
18.如权利要求17所述的半导体功率器件的终端结构的制造方法，其特征在于：所述半导体功率器件为具有超结结构。
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