GB2330452A

GB2330452A - Arrangement for inhibiting dielectric polarisation in high voltage devices

Info

Publication number: GB2330452A
Application number: GB9721954A
Authority: GB
Inventors: James Thomson; Ian Francis Deviny
Original assignee: Plessey Semiconductors Ltd; Mitel Semiconductor Ltd
Current assignee: Plessey Semiconductors Ltd; Microsemi Semiconductor Ltd
Priority date: 1997-10-16
Filing date: 1997-10-16
Publication date: 1999-04-21
Also published as: GB9721954D0

Abstract

A semiconductor device, such as an IGBT, which in use needs to withstand the application of high potential differences without breakdown is provided at a surface with a layer of insulator 10 and a semi-insulating SIPOS layer 11 in good electrical contact with the semiconductor surface in a plurality of guard ring regions and separated from the semiconductor surface by the insulator elsewhere so as to inhibit polarisation of charge in the insulating layer so inhibiting creation of an inversion region at the surface which could result in leakage across the semiconductor device. The structure also offers ESD protection.

Description

SEMICONDUCTOR DEVICES The present invention relates to semiconductor devices and is especially applicable to high voltage devices such as Insulated Gate Bipolar Transistors (IGBT's).

An Insulated Gate Bipolar Transistor is able to switch relatively high currents and voltages, and in its non-conducting state it has to be capable of withstanding a large potential difference across it, which gives rise to high electric fields.

A problem with known devices is that charges can accumulate in insulating layers of the device and can polarise as a result of an electric field through the insulating layers leading to inversion of the conductivity type of an adjacent semiconductor region. This problem is particularly noticeable in the potential field isolation region (isolating field region) which functions to isolate the emitter/source contact area from regions at collector potential. Accumulation of charge in the overlying insulating layer can result in inversion of the conductivity type in the field region such that off-state leakage occurs. Such electric charges are, for example, generated by the ingress of moisture into the device which then polarises under the influence of electric field to cause an adverse semi-stable electric charge.

The use of doped regions with a high impurity concentration forming complete rings (known as guard or field rings) around the active parts of the circuit is a known method of ensuring that the electric charge in the isolating field region is distributed around the device, thereby optimising off-state breakdown voltage or leakage. These rings may be formed by the introduction of impurities by conventional means into the surface so as to form regions of the opposite conductivity type to the surrounding semiconductor.

The level of impurities is high enough to produce a higher conductivity in the rings compared to the surrounding semiconductor.

Various constructional methods are known that seek to control the formation of charge in the isolating field region insulating layer such as polyimide coating on the surface of the (typically silicon) device which acts as a barrier to moisture. Another method uses a semi-insulating film very close to, but not in contact with the silicon surface, i.e. separated by a very thin, typically chemically grown oxide layer. This method depends on the tunnelling of electrons through the oxide which is effective in modifying the electric field at the surface of the substrate. It is difficult to implement due to the tight tolerances required during manufacture.

The object of the present invention is to provide a more effective means of modifying the electric field in an insulating layer of a semiconductor device that is also simple to implement.

The present invention provides a semiconductor device comprising a layer of semiconductor material of a first conductivity type with a defined surface, a plurality of regions of a second conductivity type arranged in the surface of the semiconductor layer; an insulating layer arranged on the surface of the semiconductor layer; and a semiinsulating layer arranged in good electrical contact with the semiconductor layer in the plurality of regions and separated from the semiconductor layer by the insulating layer elsewhere, wherein in use, an electric field in the insulating layer is modified.

The device may advantageously incorporate a conductive layer between and in contact with the regions and the semi-insulating layer. Where the semi-insulating layer is an oxygen doped polysilicon film, the construction has been labelled SIPOX Semi Insulating Polysilicon On Oxide.

The semiconductor layer may comprise a semiconducting substrate or a layer formed in or on a semiconducting or insulating substrate.

An embodiment of the invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 shows a plan view of an IGBT device; Figure 2 shows a partial cross-sectional view taken through the isolating field region of the IGBT device of Figure 1; Figure 3 shows an enlarged portion of the cross section of Figure 2.

Referring to Figure 1; the IGBT device is formed on a suitable substrate, typically silicon. The active area of the IGBT device consists of an array of source/emitter/contacts 2 in a polysilicon gate area 1. The active area of the Power Device is that portion responsible for controlling the current flow. This consists of an array of small cells (usually numbering several thousand) all acting in parallel to give a required total current handling capability. Each cell is made up of a source/emitter region 2 surrounded by polysilicon gate area 1. In the on-state current flows from the emitter to the collector (not shown) located on the under side of the wafer. Isolating field region 3 (which isolates emitter region 2 from the collector potential which, in use, extends from the bottom surface of the substrate around the edges 4 of the device) comprises a number guard rings 5.

The IGBT has a substrate of bulk silicon (not shown) upon which an epitaxial silicon layer 8 is provided. The silicon substrate is provided on the underside with a metal electric contact layer (not shown) which acts as the collector for the IGBT and would act as the drain in the case of the invention being applied to a MOSFET.

The thickness of the epitaxial layer depends upon the voltage drop required. In this embodiment the epitaxial layer 8 is n type and the bulk silicon substrate is p type.

The source/emitters regions of the cells are recessed and are electrically interconnected by aluminium metallisation layer (not shown) in the region 1.

The gate of the IGBT cell is formed by a gate oxide layer and a gate conductor layer (not shown) covered by further oxide.

Referring to Figure 2; this shows a cross-section taken through the isolating field region of the IGBT of Figure 1. In Figure 2 only the top part of the IGBT is shown, i.e. the epitaxial layer 8 and the features created in and on this layer. The rings 5 comprise doped contact regions 7 of opposite conductivity type to the surrounding semiconductor.

The regions 7 may be formed by conventional diffusion or ion implantation techniques using standard photo-masking and etch techniques. In this embodiment the regions are p type. The epitaxial layer 8 is covered in the areas around the rings 5 by layer 10 in the form of an insulating film, such as silicon dioxide which may be formed by standard techniques. Semi-insulating film 11 comprises a semi-insulating layer such as oxygen doped polysilicon film, covered with silicon nitride. Semi-insulating film 11 is formed on the insulating film 10 and rings 5 of the field region. At rings 5 interruptions in the insulating film 10 allow contact between semi-insulating film 11 and doped regions 7.

Around rings 5 the semi-insulating film 11 is isolated from the epitaxial layer 8 by insulating layer 10.

Referring to Figure 3; the contact area of rings 5 may be increased by trenching, by which is meant etching a trench through the surface of the substrate into the doped regions 7, which may be achieved by conventional means using the insulating film 10 as a self-aligned etch mask. The contact resistance between the semi-insulating layer 11, and the doped regions 7 may be further reduced by introducing a conductive layer by, for example, employing a selective silicidation 12 (i.e. introducing metal impurities in order to create conduction-enhancing metal silicides) at their interface using well known techniques such as sputtering. Other methods for reducing the resistance in this area may be used, including implantation of the same type of impurity into the top surface 13 of the doped regions either using the insulating film 10 as a self-aligned mask or in conjunction with a resist mask to exclude the implant from the insulating film. These methods may be applied individually or together.

Advantageously, the formation of a conduction layer at the contact interface may also act to improve the resistance of the IGBT device to electro-static discharges.

The operation of the device of the invention will now be described. In the off state the emitter and collector regions of the IGBT achieve different electrical potentials thereby creating an electric field between these regions. The isolating field region 3 acts to prevent electrical breakdown between the regions which may be caused by this electrical field. In use therefore an electrical potential gradient exists across the isolating field region 3 both at the surface and through the bulk silicon. This electrical potential gradient creates an electric field in the insulating layer 10 which will tend to cause polarisation of charges trapped in the insulation layer. Semi-insulating layer 11 is brought into electrical contact with the silicon epitaxial layer 8 at a number of contact areas, e.g. at guard rings 5. As a result of these contacts the electrical potential gradient in the semi-insulating layer closely matches that across the surface of the substrate in the isolating field region so that at any position across the isolating field region 3 the potential of the silicon surface and the overlying semi-insulating layer 11 will be approximately the same. As the insulator 10 is sandwiched between the top surface of the epitaxial layer 8 and the semi-insulating layer 11, any electric field across the insulating layer 10 will tend to be reduced to zero. In the absence of an electrical field, polarisation of charge in the insulating layer 10 does not take place and inversion of the conductivity type at the surface of the epitaxial layer 8 is inhibited.

The scope of the invention is not limited to doped contacts in the form of rings and the invention applies equally to devices with other forms of contact, and linear contacts.

Claims

CLAIMS 1. A semiconductor device comprising a layer of semiconductor material of a first conductivity type with a defined surface, a plurality of regions of a second conductivity type arranged in the surface of the semiconductor layer; an insulating layer arranged on the surface of the semiconductor layer; and a semi insulating layer arranged in good electrical contact with the semiconductor layer in the plurality of regions and separated from the semiconductor layer by the insulating layer elsewhere, wherein in use, an electric field in the insulating layer is modified.
2. The semiconductor device of Claim 1 comprising a conductive layer between, and in contact with, at least one of said plurality of regions and the semi insulating layer.
3. The semiconductor device of any of the above claims wherein said electrical contact exists at locations where the insulating layer has been selectively removed.
4. The semiconductor device of any one of the above claims wherein the semi insulating material is positioned and arranged to reduce the electric field strength in the insulating layer.
5. The serniconductor device of any of the above claims wherein in use the surface of the semiconductor substrate is subject to an electrical potential gradient and wherein the semi-insulating material is positioned and arranged to allow modification of the electric field in and across the insulating layer by assuming an electrical potential gradient substantially identical to the electrical potential gradient across the surface of the semiconductor layer.
6. The semiconductor device of any above claim wherein polarisation of charge in the insulating layer is inhibited.
7. The semiconductor device of any of the above claims comprising at least one insulated gate bipolar transistor (IGBT), wherein said plurality of regions are formed in an isolating field region of said IGBT.
8. A method of manufacture of a semiconductor device comprising the steps of providing a semiconductor layer of a first conductivity type with a defined surface; arranging a plurality of regions of a second conductivity type in the surface of the semiconductor layer; providing an insulating layer on the surface of the semiconductor layer; arranging a semi-insulating layer, in good electrical contact with the semiconductor layer in the plurality of regions and separated from the semi-conductor layer by the insulating layer elsewhere.
9. The method of Claim 8 further comprising the step of providing a conductive layer between, and in contact with. at least one of the plurality of regions and the semi-insulating layer.
10. The method of any of Claims 8 to 9 further comprising the step of implanting near the surface of the semiconductor layer in the plurality of regions additional impurities of the same type as those used to create the regions.
11. The method of any one of Claims 8 to 10 wherein the insulating layer is used as a self-aligned mask.
12. The method of any one of Claims 8 to 11 wherein the access to the plurality of regions for making said good electrical contact is provided by the step of selectively removing the insulating layer.
13. A method for modifying an electric field in an insulating layer formed on a semiconductor layer comprising the steps of providing a semi-insulating layer on the insulating layer, and electrically connecting the semi-insulating layer at intervals to the semiconductor layer.
14. The method of Claim 13 comprising the step of creating contact regions for connection of the semiconductor layer to the semi-insulating layer by selective removal of the insulating layer.
15. The method of any one of Claims 13 to 14 comprising the step of providing doped regions in the surface of the semiconductor layer at the points for connection with the semi-insulating layer.
16. The method of Claim 15 comprising the step of providing a conductive layer at a connection point between and in intimate contact with the doped regions and the semi-insulating layer.
17. The method of any one of Claims 13 to 16 wherein the insulating layer is formed in an isolating field region of an insulated gate bipolar transistor (IGBT), wherein polarisation of charge in the insulating layer is prevented.
18. The method of any one of Claims 13 to 17 wherein leakage caused by inversion of the semiconductor layer in the region of the insulating layer is inhibited.
19. A semiconductor device substantially as hereinbefore described with reference to the figures.
20. A method for manufacture of a semiconductor device substantially as hereinbefore described with reference to the figures.
21. A method for modifying an electric field in an insulating layer formed on a semiconductor layer or substrate substantially as hereinbefore described with reference to the figures.