CN106802388A - A kind of test module of hybrid digital-analog integrated circuit - Google Patents
A kind of test module of hybrid digital-analog integrated circuit Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
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Abstract
A kind of test module of hybrid digital-analog integrated circuit, belongs to semiconductor hybrid digital-analog integrated circuit design for Measurability field.On the premise of circuit basic function is not influenceed; in the case where number of pins is limited; by increasing mode controlling unit, input pin Multiplexing Unit, output pin Multiplexing Unit, DAC data bypass units; solve existing hybrid digital-analog integrated circuit test design difficulty big; the not comprehensive enough problem of test; the present invention can be with relatively low design complexities and design time cost; improve the flexibility of the test design of hybrid digital-analog integrated circuit; realize that express delivery positions failure, it is ensured that the validity and completeness of chip testing.
Description
Technical field
The present invention relates to a kind of test module of hybrid digital-analog integrated circuit, belonging to semiconductor hybrid digital-analog integrated circuit can
The property surveyed design field, is mainly used in the test design of the limited semiconductor hybrid digital-analog integrated circuit of number of pins.
Background technology
It is produced various in design and manufacturing process with the continuous progress of method of designing integrated circuit and technology
Problem results in the difficulty and cost more and more higher of chip testing, and measurability problem has become raising product reliability and finished product
One very important factor of rate.Test cost is sharply increased, and traditional method of testing seems and is difficult to be competent at.
In recent years, IC industry high speed prosperity and development, it is traditional for the functional density requirement more and more higher of system
By lifting manufacturing process, Optimization Design cannot meet system compact, integrated realizing the method for high integration
Change, the active demand of low-power consumption.Therefore, by including various points including numeral, simulation, analog-digital converter and digital analog converter etc.
The integrated hybrid digital-analog integrated circuit designing technique on a single chip of vertical unit, reduces volume, lifting integrated level, carries as system
High performance key point.Hybrid digital-analog integrated circuit, the adequacy of its test is undoubtedly key for the reliability application of system
In key.Therefore, the design for Measurability research of hybrid digital-analog integrated circuit all has in terms of theoretical research and engineering practice
Very prominent value.
Hybrid digital-analog integrated circuit both comprising digital logic portion or included analog logic part, and contained numeral
Signal and analog signal are with functional relation tight association.Digital logic portion and analog logic part exist with DAC and ADC respectively
The interaction of signal, the particularity of Digital Analog Hybrid Circuits structure brings huge difficulty to the test of circuit, and this is mainly reflected in
3 aspects below：
(1) controllability of hybrid digital-analog integrated circuit is not high with observability degree.The output signal of such as ADC is numeral
The input of logic, response that can not be by outside output I/O pin to ADC is directly observed, so being difficult to ADC logics
And its prime analog circuit realizes observability.The input signal of DAC comes from the output of Digital Logic, it is impossible to defeated by outside
Enter I/O pin and apply excitation, so the controllability degree of DAC logics and following stage analog circuit is very low.On the whole, circuit
The accessibility of digital-to-analog device becomes very low, increases the difficulty of test, it is difficult to the coverage rate of lifting test.
(2) it is unable to fault location.If mixed signal module is tested as an entirety, analog portion and numeral
There is mutually constraint between part, when output result be expected not being inconsistent, that is, when showing to there is failure inside circuit, it is impossible to which positioning is
The failure of analog circuit or the failure of digital circuit.
(3) see on the whole, in order to plate level is applied, simplifying encapsulation requires, reduce packaging cost, Digital Analog Hybrid Circuits are general
Only limited I/O pin number, reduces the controllability and observability of circuit, as a consequence it is hardly possible to directly carries out test and swashs
Encourage applying and response analysis.
The content of the invention
The problem that technology of the invention is solved is：Overcome the deficiencies in the prior art, there is provided a kind of hybrid digital-analog integrated circuit
Test module, improve the controllability of hybrid digital-analog integrated circuit and observability degree, can directly carry out test and excitation
Apply and response analysis, and position failure, it is ensured that the validity and completeness of chip testing.
Technical solution of the invention is：A kind of test module of hybrid digital-analog integrated circuit, including：Schema control list
Unit, input pin Multiplexing Unit, output pin Multiplexing Unit and DAC data bypass units；
Mode controlling unit：Mode control signal chip_mode1, chip_mode0 according to outside input, produce ADC
Test mode signal adc_mode, scan testing mode signal scan_mode, functional mode signal func_mode and DAC are surveyed
Examination mode signal dac_mode, and by scan testing mode signal scan_mode, functional mode signal func_mode and DAC
Test mode signal dac_mode is exported and is given input pin Multiplexing Unit, by ADC test mode signals adc_mode, sweep test
Mode signal scan_mode and functional mode signal func_mode are exported and are given output pin Multiplexing Unit, and functional mode is believed
Number func_mode and DAC test mode signals dac_mode is exported and is given DAC data bypass units；
Input pin Multiplexing Unit：The input signal DIN of hybrid digital-analog integrated circuit is received, according to coming from Schema control
The scan testing mode signal scan_mode of unit, functional mode signal func_mode and DAC test mode signal dac_
Mode, determines that the fuction output signal func_do of input pin Multiplexing Unit, Scan out scan_do, DAC test are defeated
Go out signal dac_do；
Output pin Multiplexing Unit：Receive output signal adc_di, the fuction output signal of digital function logic of ADC
The Scan out scan_di of func_di and digital function logic, tests according to the ADC for coming from mode controlling unit
Mode signal adc_mode, functional mode signal func_mode and scan testing mode signal scan_mode, it is determined that output
The output signal DOUT of pin multiplexing unit, and outwards export, the output signal DOUT is used to judge that the first analog functuion is patrolled
Volume and the Functional Design of ADC, the Functional Design of digital function logic, digital function logic Scan Design it is whether correct；
DAC data bypass units：Receive fuction output data func_data, the input pin multiplexing of digital function logic
The DAC test output signal dac_do of unit, according to the functional mode signal func_mode for coming from mode controlling unit, with
And DAC test mode signal adc_mode, determining the output data dac_data of DAC data bypass units, the data pass through DAC
DAC test results are outwards exported with the second analog functuion logic, the second analog functuion logic outwards exports DAC test results
Whether the Functional Design for judging DAC and analog functuion logic is correct.
As mode control signal chip_mode1=0, during chip_mode0=0, ADC test mode signals adc_mode=
0th, scan testing mode signal scan_mode=0, functional mode signal func_mode=1, DAC test mode signal dac_
Mode=0, circuit is operated in functional mode；As mode control signal chip_mode1=0, during chip_mode0=1, ADC is surveyed
Examination mode signal adc_mode=0, scan testing mode signal scan_mode=0, functional mode signal func_mode=0,
DAC test mode signal dac_mode=1, circuit is operated in DAC test patterns；As mode control signal chip_mode1=1,
During chip_mode0=0, ADC test mode signals adc_mode=1, scan testing mode signal scan_mode=0, function
Mode signal func_mode=0, DAC test mode signal dac_mode=0, circuit is operated in ADC test patterns；Work as pattern
Control signal chip_mode1=1, during chip_mode0=1, ADC test mode signals adc_mode=0, scan testing mode
Signal scan_mode=1, functional mode signal func_mode=0, DAC test mode signal dac_mode=0, circuit work
In scan testing mode.
The input pin Multiplexing Unit determines that the fuction output signal func_do of input pin Multiplexing Unit, scanning are defeated
The principle for going out signal scan_do, DAC test output signal dac_do is：When scan testing mode signal scan_mode is 1,
Scan out scan_do is equal to input signal DIN, and other two is fixed level；As functional mode signal func_mode
For 1 when, fuction output signal func_do be equal to input signal DIN, other two is fixed level；When DAC test mode signals
When dac_mode is 1, DAC test output signals dac_do is equal to input signal DIN, and other two is fixed level.
The output pin Multiplexing Unit determines that the principle of the output signal DOUT of output pin Multiplexing Unit is：Work as ADC
When test mode signal adc_mode is 1, output signal DOUT is equal to the output signal adc_di of ADC, and other two is fixation
Level；When functional mode signal func_mode is 1, output signal DOUT is equal to the fuction output signal of digital function logic
Func_di, other two is fixed level；When scan testing mode signal scan_mode is 1, output signal DOUT is equal to
The Scan out scan_di of digital function logic, other two is fixed level.
The DAC data bypass unit determines that the principle of the output data dac_data of DAC data bypass units is：Work as work(
When energy mode signal func_mode is 1, output data dac_data is equal to the fuction output data func_ of digital function logic
data；When DAC test mode signals dac_mode is 1, output data dac_data is equal to the DAC of input pin Multiplexing Unit
Test output signal dac_do.
The present invention has the beneficial effect that compared with prior art：
(1) present invention by two Schema control pins chip_mode1, chip_mode0 realize normal mode of operation and
The switching of test pattern, under different test patterns, analog functuion logical sum digital function logic is separate, mutually not shadow
Ring.
(2) circuit is divided into four kinds of patterns by the present invention by mode controlling unit：func_mode、dac_mode、adc_
Mode, scan_mode, effectively, it is digital function logic or simulation work(that can quickly position failure to each only one of which pattern
Can logic.
(3) present invention, can be under dac_mode patterns, by input pipe in the case where chip exterior port is not increased
Pin Multiplexing Unit and DAC data bypass units, are directly input to port DAC module and are tested, improve controllability；
Under adc_mode patterns, by output pin Multiplexing Unit, direct ADC output improves considerable to circuit output port
The property surveyed；Under scan_mode patterns, by input pin Multiplexing Unit, port is directly input to digital function logic, improved
Controllability, by output pin Multiplexing Unit, directly improves considerable the output of digital function logic to circuit output port
The property surveyed.Greatly reduce the demand to I/O pin number that chip testing is brought.
Brief description of the drawings
Fig. 1 is hybrid digital-analog integrated circuit schematic diagram；
Fig. 2 is the hybrid digital-analog integrated circuit schematic diagram comprising test module of the present invention；
Fig. 3 is the schematic diagram of mode controlling unit of the present invention；
Fig. 4 is the schematic diagram of input pin Multiplexing Unit of the present invention；
Fig. 5 is the schematic diagram of output pin Multiplexing Unit of the present invention；
Fig. 6 is the schematic diagram of DAC data bypass unit of the present invention.
Specific embodiment
It is as shown in Figure 1 hybrid digital-analog integrated circuit schematic diagram.It is illustrated in figure 2 the digital-to-analogue comprising test module of the present invention
Hydrid integrated circuit schematic diagram.Test module of the invention includes：Mode controlling unit, input pin Multiplexing Unit, efferent duct
Pin Multiplexing Unit and DAC data bypass units.
Mode controlling unit：Mode control signal chip_mode1, chip_mode0 according to outside input, produce ADC
Test mode signal adc_mode, scan testing mode signal scan_mode, functional mode signal func_mode and DAC are surveyed
Examination mode signal dac_mode, and by scan testing mode signal scan_mode, functional mode signal func_mode and DAC
Test mode signal dac_mode is exported and is given input pin Multiplexing Unit, by ADC test mode signals adc_mode, sweep test
Mode signal scan_mode and functional mode signal func_mode are exported and are given output pin Multiplexing Unit, and functional mode is believed
Number func_mode and DAC test mode signals dac_mode is exported and is given DAC data bypass units.
As shown in figure 3, mode controlling unit by two phase inverters IV1, IV2 and four and door AND1, AND2, AND3,
AND4 is constituted；The input of phase inverter IV1 and phase inverter IV2 connects chip_mode0 and chip_mode1 respectively；With door AND1
Input connect the output end of phase inverter IV1 and IV2, output end connection func_mode respectively；With the input point of door AND2
Not Lian Jie phase inverter IV1 output end and chip_mode1, output end connection dac_mode；Input with door AND3 connects respectively
Connect the output end and chip_mode0 of phase inverter IV2, output end connection adc_mode；Input with door AND4 is connected respectively
Chip_mode1 and chip_mode0, output end connection scan_mode.
As mode control signal chip_mode1=0, during chip_mode0=0, ADC test mode signals adc_mode=
0th, scan testing mode signal scan_mode=0, functional mode signal func_mode=1, DAC test mode signal dac_
Mode=0, circuit is operated in functional mode；As mode control signal chip_mode1=0, during chip_mode0=1, ADC is surveyed
Examination mode signal adc_mode=0, scan testing mode signal scan_mode=0, functional mode signal func_mode=0,
DAC test mode signal dac_mode=1, circuit is operated in DAC test patterns；As mode control signal chip_mode1=1,
During chip_mode0=0, ADC test mode signals adc_mode=1, scan testing mode signal scan_mode=0, function
Mode signal func_mode=0, DAC test mode signal dac_mode=0, circuit is operated in ADC test patterns；Work as pattern
Control signal chip_mode1=1, during chip_mode0=1, ADC test mode signals adc_mode=0, scan testing mode
Signal scan_mode=1, functional mode signal func_mode=0, DAC test mode signal dac_mode=0, circuit work
In scan testing mode.
The truth table of mode controlling unit is as shown in table 1.
The mode controlling unit truth table of table 1
| chip_mode1 | chip_mode0 | func_mode | dac_mode | adc_mode | scan_mode |
| 0 | 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 |
Input pin Multiplexing Unit：The input signal DIN of hybrid digital-analog integrated circuit is received, according to coming from Schema control
The scan testing mode signal scan_mode of unit, functional mode signal func_mode and DAC test mode signal dac_
Mode, determines that the fuction output signal func_do of input pin Multiplexing Unit, Scan out scan_do, DAC test are defeated
Go out signal dac_do.
As shown in figure 4, input pin Multiplexing Unit by nine Port Multiplier MUX11, MUX12, MUX13, MUX21, MUX22,
MUX23, MUX31, MUX32, MUX33 are constituted.0 data input pin and 1 data input pin of Port Multiplier MUX11, connect and fix 0 or 1,
Select the output dac_mode of termination mode control unit.The 1 data input termination of MUX12 fixes 0 or 1, the connection of 0 input
The output of MUX11, selects the output func_mode of termination mode control unit.The 0 input connection MUX12 of Port Multiplier MUX13
Output, 1 input connection DIN, select termination mode control unit output scan_mode.0 data of Port Multiplier MUX21
Input, 1 data input pin, connect and fix 0 or 1, select the output scan_mode of termination mode control unit.1 number of MUX22
0 or 1 is fixed according to input termination, 0 input connects the output of MUX21, select the output func_ of termination mode control unit
mode.0 input of Port Multiplier MUX23 connects the output of MUX22, and 1 input connection DIN selects termination mode control unit
Output dac_mode.0 data input pin of Port Multiplier MUX31,1 data input pin, connect and fix 0 or 1, select termination mode control
The output dac_mode of unit processed.The 1 data input termination of MUX32 fixes 0 or 1, and 0 input connects the output of MUX31, selection
The output scan_mode of termination mode control unit.0 input of Port Multiplier MUX33 connects the output of MUX32, and 1 input connects
DIN is met, the output func_mode of termination mode control unit is selected.
The fuction output signal func_do of input pin Multiplexing Unit, Scan out scan_do, DAC test output
The determination principle of signal dac_do is：When scan testing mode signal scan_mode is 1, Scan out scan_do etc.
In input signal DIN, other two is fixed level；When functional mode signal func_mode is 1, fuction output signal
Func_do is equal to input signal DIN, and other two is fixed level；When DAC test mode signals dac_mode is 1, DAC
Test output signal dac_do is equal to input signal DIN, and other two is fixed level.
The truth table of input pin Multiplexing Unit is as shown in table 2.
The input pin Multiplexing Unit truth table of table 2
Output pin Multiplexing Unit：Receive output signal adc_di, the fuction output signal of digital function logic of ADC
The Scan out scan_di of func_di and digital function logic, tests according to the ADC for coming from mode controlling unit
Mode signal adc_mode, functional mode signal func_mode and scan testing mode signal scan_mode, it is determined that output
The output signal DOUT of pin multiplexing unit, and outwards export, the output signal DOUT is used to judge that the first analog functuion is patrolled
Volume and the Functional Design of ADC, the Functional Design of digital function logic, digital function logic Scan Design it is whether correct.
As shown in figure 5, output pin Multiplexing Unit is made up of three Port Multipliers MUX1, MUX2, MUX3.Port Multiplier MUX1's
0 data input termination fixes 0 or 1,1 data input termination adc_di, selects the output adc_mode of termination mode control unit.
0 input of Port Multiplier MUX2 connects the output of MUX1, and 1 data input termination scan_di selects termination mode control unit
Output scan_mode.0 input of Port Multiplier MUX3 connects the output of MUX2,1 input connection func_di, selection termination mould
The output func_mode of formula control unit.The data output of MUX3 terminates the output end DOUT of output pin Multiplexing Unit.
Output pin Multiplexing Unit determines that the principle of the output signal DOUT of output pin Multiplexing Unit is：When ADC tests
When mode signal adc_mode is 1, output signal DOUT is equal to the output signal adc_di of ADC, and other two is fixed level；
When functional mode signal func_mode is 1, output signal DOUT is equal to the fuction output signal func_ of digital function logic
Di, other two is fixed level；When scan testing mode signal scan_mode is 1, output signal DOUT is equal to digital work(
The Scan out scan_di of energy logic, other two is fixed level.
The truth table of output pin Multiplexing Unit is as shown in table 3.
The output pin Multiplexing Unit truth table of table 3
DAC data bypass units：Receive fuction output data func_data, the input pin multiplexing of digital function logic
The DAC test output signal dac_do of unit, according to the functional mode signal func_mode for coming from mode controlling unit, with
And DAC test mode signal adc_mode, determining the output data dac_data of DAC data bypass units, the data pass through DAC
DAC test results are outwards exported with the second analog functuion logic, the second analog functuion logic outwards exports DAC test results
Whether the Functional Design for judging DAC and analog functuion logic is correct.
As shown in fig. 6, DAC data bypass unit is made up of two Port Multipliers MUXM1, MUXM2.0 number of Port Multiplier MUXM1
0/1,1 data input termination TEST_DATA is fixed according to input termination, the output dac_mode of termination mode control unit is selected.
0 input of Port Multiplier MUXM2 connects the output of MUXM1, and 1 data input termination FUNC_DATA, selection termination mode control is single
The output func_mode of unit.Dac_data connects the data output end of MUXM2.
The determination principle of the output data dac_data of DAC data bypass units is：As functional mode signal func_mode
For 1 when, output data dac_data be equal to digital function logic fuction output data func_data；When DAC test patterns letter
When number dac_mode is 1, output data dac_data is equal to the DAC test output signals dac_do of input pin Multiplexing Unit.
The design procedure of test module of the present invention is as follows：
(1) the design top layer in hybrid digital-analog integrated circuit increases by two new chip ports：Chip_mode1, chip_
Mode0, as two inputs of mode controlling unit, mode controlling unit is added to the top layer of design；
(2) input pin Multiplexing Unit is added after the input PAD units of design top layer, is determined required under scan_mode
Input control signal number and internal DAC-circuit bit wide, the maximum of the two is required input pin Multiplexing Unit
Number；
(3) output pin Multiplexing Unit is added before the output PAD units of design top layer, is determined required under scan_mode
Output signal number and internal adc circuit bit wide, the maximum of the two is required output pin Multiplexing Unit number；
(4) DAC data bypass units are added before DAC-circuit；
(5) in design top layer, the mode of code is manually rewritten, is connected according to annexation as shown in Figure 2
Connect.
It is big for hybrid digital-analog integrated circuit design for Measurability difficulty, not comprehensive enough problem is tested, the present invention is proposed
Hybrid digital-analog integrated circuit test module, the test module can complete number with relatively low design complexities and design time cost
The test design of mould hydrid integrated circuit, improves the controllability and observability degree, Neng Gouzhi of hybrid digital-analog integrated circuit
Tap into row test and excitation to apply and response analysis, and position failure, it is ensured that the validity and completeness of chip testing.
Unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.
Claims (5)
1. a kind of test module of hybrid digital-analog integrated circuit, it is characterised in that including：Mode controlling unit, input pin multiplexing
Unit, output pin Multiplexing Unit and DAC data bypass units；
Mode controlling unit：Mode control signal chip_mode1, chip_mode0 according to outside input, produce ADC tests
Mode signal adc_mode, scan testing mode signal scan_mode, functional mode signal func_mode and DAC test mould
Formula signal dac_mode, and scan testing mode signal scan_mode, functional mode signal func_mode and DAC are tested
Mode signal dac_mode is exported and is given input pin Multiplexing Unit, by ADC test mode signals adc_mode, scan testing mode
Signal scan_mode and functional mode signal func_mode are exported and are given output pin Multiplexing Unit, by functional mode signal
Func_mode and DAC test mode signals dac_mode is exported and is given DAC data bypass units；
Input pin Multiplexing Unit：The input signal DIN of hybrid digital-analog integrated circuit is received, according to coming from mode controlling unit
Scan testing mode signal scan_mode, functional mode signal func_mode and DAC test mode signal dac_mode,
Determine fuction output signal func_do, Scan out scan_do, DAC test output signal of input pin Multiplexing Unit
dac_do；
Output pin Multiplexing Unit：Receive output signal adc_di, the fuction output signal func_ of digital function logic of ADC
The Scan out scan_di of di and digital function logic, believes according to the ADC test patterns for coming from mode controlling unit
Number adc_mode, functional mode signal func_mode and scan testing mode signal scan_mode, determine that output pin is answered
With the output signal DOUT of unit, and outwards export, the output signal DOUT is used to judge the first analog functuion logical sum ADC
Functional Design, the Functional Design of digital function logic, digital function logic Scan Design it is whether correct；
DAC data bypass units：Receive fuction output data func_data, the input pin Multiplexing Unit of digital function logic
DAC test output signal dac_do, according to the functional mode signal func_mode for coming from mode controlling unit, and DAC
Test mode signal adc_mode, determines the output data dac_data of DAC data bypass units, and the data are by DAC and the
Two analog functuion logics outwards export DAC test results, and the second analog functuion logic outwards exports DAC test results to be used for
Judge whether the Functional Design of DAC and analog functuion logic is correct.
2. the test module of a kind of hybrid digital-analog integrated circuit according to claim 1, it is characterised in that：Work as Schema control
Signal chip_mode1=0, during chip_mode0=0, ADC test mode signals adc_mode=0, scan testing mode signal
Scan_mode=0, functional mode signal func_mode=1, DAC test mode signal dac_mode=0, circuit are operated in work(
Can pattern；As mode control signal chip_mode1=0, during chip_mode0=1, ADC test mode signals adc_mode=
0th, scan testing mode signal scan_mode=0, functional mode signal func_mode=0, DAC test mode signal dac_
Mode=1, circuit is operated in DAC test patterns；As mode control signal chip_mode1=1, during chip_mode0=0, ADC
Test mode signal adc_mode=1, scan testing mode signal scan_mode=0, functional mode signal func_mode=
0th, DAC test mode signals dac_mode=0, circuit is operated in ADC test patterns；As mode control signal chip_mode1=
When 1, chip_mode0=1, ADC test mode signals adc_mode=0, scan testing mode signal scan_mode=1, work(
Energy mode signal func_mode=0, DAC test mode signal dac_mode=0, circuit is operated in scan testing mode.
3. the test module of a kind of hybrid digital-analog integrated circuit according to claim 1, it is characterised in that：The input pipe
Pin Multiplexing Unit determines that the fuction output signal func_do of input pin Multiplexing Unit, Scan out scan_do, DAC are surveyed
The principle of examination output signal dac_do is：When scan testing mode signal scan_mode is 1, Scan out scan_do
Equal to input signal DIN, other two is fixed level；When functional mode signal func_mode is 1, fuction output signal
Func_do is equal to input signal DIN, and other two is fixed level；When DAC test mode signals dac_mode is 1, DAC
Test output signal dac_do is equal to input signal DIN, and other two is fixed level.
4. the test module of a kind of hybrid digital-analog integrated circuit according to claim 1, it is characterised in that：The efferent duct
Pin Multiplexing Unit determines that the principle of the output signal DOUT of output pin Multiplexing Unit is：As ADC test mode signals adc_
When mode is 1, output signal DOUT is equal to the output signal adc_di of ADC, and other two is fixed level；When functional mode letter
When number func_mode is 1, output signal DOUT is equal to the fuction output signal func_di of digital function logic, and other two is
Fixed level；When scan testing mode signal scan_mode is 1, output signal DOUT is equal to the scanning of digital function logic
Output signal scan_di, other two is fixed level.
5. the test module of a kind of hybrid digital-analog integrated circuit according to claim 1, it is characterised in that：The DAC numbers
The principle that the output data dac_data of DAC data bypass units is determined according to by-pass unit is：As functional mode signal func_
When mode is 1, output data dac_data is equal to the fuction output data func_data of digital function logic；When DAC tests mould
When formula signal dac_mode is 1, output data dac_data is equal to the DAC test output signals dac_ of input pin Multiplexing Unit
do。
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111030691A (en) * | 2019-12-30 | 2020-04-17 | 思瑞浦微电子科技（苏州）股份有限公司 | Reliability verification method and system based on analog-to-digital converter |
| CN111381148A (en) * | 2018-12-29 | 2020-07-07 | 无锡华润矽科微电子有限公司 | System and method for realizing chip test |
| CN115078968A (en) * | 2022-06-15 | 2022-09-20 | 上海类比半导体技术有限公司 | Chip test circuit, self-test chip and chip test system |
| CN117111045A (en) * | 2023-10-25 | 2023-11-24 | 成都量芯集成科技有限公司 | Signal generator for phase type laser measurement |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5887001A (en) * | 1995-12-13 | 1999-03-23 | Bull Hn Information Systems Inc. | Boundary scan architecture analog extension with direct connections |
| CN1385710A (en) * | 2001-05-11 | 2002-12-18 | 株式会社鼎新 | Event tester structure for mixed signal test |
| US20040177303A1 (en) * | 2001-02-09 | 2004-09-09 | Toshiyuki Miura | Analog-hybrid ic test system |
| CN1879029A (en) * | 2003-11-26 | 2006-12-13 | 爱德万测试株式会社 | Synchronization of modules for analog and mixed signal testing |
| JP2007178387A (en) * | 2005-12-28 | 2007-07-12 | Toshiba Corp | Semiconductor integrated circuit device |
| JP2008153600A (en) * | 2006-12-20 | 2008-07-03 | Renesas Technology Corp | Semiconductor integrated circuit device |
| CN201331568Y (en) * | 2009-01-14 | 2009-10-21 | 西安明泰半导体测试有限公司 | Testing device for digifax mix signal integrate circuit |
| CN101592706A (en) * | 2009-07-08 | 2009-12-02 | 天津渤海易安泰电子半导体测试有限公司 | Digital and analog mixed signal chip test card |
| CN101592707A (en) * | 2009-07-08 | 2009-12-02 | 天津渤海易安泰电子半导体测试有限公司 | Analog and digital mixed signal chip test card |
| CN201434901Y (en) * | 2009-07-08 | 2010-03-31 | 天津渤海易安泰电子半导体测试有限公司 | Test card for digital and analog mixed signal chip on chip tester |
| CN102401878A (en) * | 2010-09-08 | 2012-04-04 | 凌阳科技股份有限公司 | Testing system and method for mixed-mode IC (integrated circuit) |
-
2016
- 2016-12-23 CN CN201611214526.5A patent/CN106802388B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5887001A (en) * | 1995-12-13 | 1999-03-23 | Bull Hn Information Systems Inc. | Boundary scan architecture analog extension with direct connections |
| US20040177303A1 (en) * | 2001-02-09 | 2004-09-09 | Toshiyuki Miura | Analog-hybrid ic test system |
| CN1385710A (en) * | 2001-05-11 | 2002-12-18 | 株式会社鼎新 | Event tester structure for mixed signal test |
| CN1879029A (en) * | 2003-11-26 | 2006-12-13 | 爱德万测试株式会社 | Synchronization of modules for analog and mixed signal testing |
| JP2007178387A (en) * | 2005-12-28 | 2007-07-12 | Toshiba Corp | Semiconductor integrated circuit device |
| JP2008153600A (en) * | 2006-12-20 | 2008-07-03 | Renesas Technology Corp | Semiconductor integrated circuit device |
| CN201331568Y (en) * | 2009-01-14 | 2009-10-21 | 西安明泰半导体测试有限公司 | Testing device for digifax mix signal integrate circuit |
| CN101592706A (en) * | 2009-07-08 | 2009-12-02 | 天津渤海易安泰电子半导体测试有限公司 | Digital and analog mixed signal chip test card |
| CN101592707A (en) * | 2009-07-08 | 2009-12-02 | 天津渤海易安泰电子半导体测试有限公司 | Analog and digital mixed signal chip test card |
| CN201434901Y (en) * | 2009-07-08 | 2010-03-31 | 天津渤海易安泰电子半导体测试有限公司 | Test card for digital and analog mixed signal chip on chip tester |
| CN102401878A (en) * | 2010-09-08 | 2012-04-04 | 凌阳科技股份有限公司 | Testing system and method for mixed-mode IC (integrated circuit) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111381148A (en) * | 2018-12-29 | 2020-07-07 | 无锡华润矽科微电子有限公司 | System and method for realizing chip test |
| CN111381148B (en) * | 2018-12-29 | 2023-02-21 | 华润微集成电路(无锡)有限公司 | System and method for realizing chip test |
| CN111030691A (en) * | 2019-12-30 | 2020-04-17 | 思瑞浦微电子科技（苏州）股份有限公司 | Reliability verification method and system based on analog-to-digital converter |
| CN111030691B (en) * | 2019-12-30 | 2023-04-18 | 思瑞浦微电子科技（苏州）股份有限公司 | Reliability verification method and system based on analog-to-digital converter |
| CN115078968A (en) * | 2022-06-15 | 2022-09-20 | 上海类比半导体技术有限公司 | Chip test circuit, self-test chip and chip test system |
| CN117111045A (en) * | 2023-10-25 | 2023-11-24 | 成都量芯集成科技有限公司 | Signal generator for phase type laser measurement |
| CN117111045B (en) * | 2023-10-25 | 2023-12-29 | 成都量芯集成科技有限公司 | Signal generator for phase type laser measurement |
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