CN115453324A - SIP chip internal interconnection testing method based on ATE - Google Patents

Abstract

The invention provides an internal interconnection test method of an SIP chip based on ATE, which comprises the following steps: s1, compiling an interconnection test program by the SVF; s2, analyzing the written SVF program into a pattern capture format file; s3, processing the vector which accords with the JTAG bus time sequence in the mode capture format file; and S4, transplanting the obtained test time sequence into an ATE test system, and carrying out interconnection test according to the specific form of the interconnection model in the SIP chip. The invention can efficiently and quickly generate the JTAG bus test time sequence aiming at different interconnection models between the SIP chip and the ATE system, thereby improving the test efficiency.

Description

SIP chip internal interconnection testing method based on ATE

Technical Field

The invention relates to the technical field of System In Package (SIP) chip testing, in particular to an internal interconnection testing method of an SIP chip based on ATE.

Background

In recent years, with the continuous breakthrough of the manufacturing technology of the nanoscale integrated circuit, moore's law development reaches a certain bottleneck, and the SIP technology provides a brand new design idea for solving the problem. A plurality of unpackaged bare chips, passive devices such as resistors, capacitors and the like are three-dimensionally integrated in a small system through the SIP technology, so that the SIP chip with a specific function is formed. However, the advanced packaging technology based on the SIP chip is continuously developed, and the manufacturing process of the SOC bare chip is continuously reduced, so that the density of devices inside the SIP chip is continuously increased, the types of the devices are continuously enriched, the density of internal interconnection lines is continuously increased, and higher requirements are provided for testing the internal interconnection of the SIP chip.

The Joint Test Action Group (JTAG for short) in 90 s of the 20 th century introduced the concept of boundary scan Test technology into chip testing for the first time, and finally formed the IEEE1149.1 standard, which was recognized in the industry. After decades of research and research, the JTAG test technology is continuously emerging, and forms the IEEE 1149.4 standard for mixed signal test, the IEEE 1149.6 standard for advanced digital networks, the IEEE 1500 standard for SoC chips, the IEEE1532 standard for on-line configuration of programmable devices, and the like. For testing of the SIP chip, the institute of electrical and electronics engineers (IEEE 1838) introduced in 2019, which is developed based on IEEE1149.1 and IEEE 1500 and is mainly used for DFT circuit design of a complex SIP chip. IEEE1838 gives theoretical guidance in addressing interoperability and testability issues between vertically stacked (e.g., 2.5D, 3D) chips, and IEEE1838 compliant products are not well established in the industry today. At present, the mature and common JTAG test technology based on the IEEE1149 standard is widely applied to the test field of electronic products such as single chips, single-board systems, multi-chip system modules and the like, and has a solid technical foundation in the aspect of solving interconnection test.

On the basis of the development of DFT technology, an interconnection test scheme aiming at a complex electronic system is developed. A DiaTem test system developed by foreign Temento Systems company based on the IEEE1149.1 standard is specially used for carrying out comprehensive interconnection test on a complex board-level digital circuit system. The DiaTem system reserves 4 JTAG interfaces and can simultaneously carry out interconnection test on a multi-scan chain system. Compared with the foreign countries, the domestic test technology research is also carried out on the multi-core heterogeneous SIP chip, a series of test methods are formed, for example, the Wuxi Mitsuti core electronics company Limited proposes a method for compressing test vectors of a 3D-SIP chip, a 3D-SIP chip test device and a system are established, a multi-layer stacked 3D-SIP chip test method is invented, and related test software is formed; fifty-eighth research institute of china electronic technology group company has proposed a multicore grain heterogeneous SIP chip test debugging technology based on JTAG interface; the Western-Ann electronic science and technology university provides a high-speed chip collaborative test based on a multi-core heterogeneous SIP chip; the Tianjin science and technology university provides a multi-core heterogeneous SIP chip special test platform research based on an embedded technology; a first research institute of China aerospace science and technology group company provides a multi-core heterogeneous SIP chip test technology research based on a JTAG test technology; the research institute of the aviation industry, the Western's aviation computing technology, provides a test method research and test board design of SIPHKY 2101A.

It can be seen from the above that the test technology for the JTAG bus is well studied abroad, and a certain achievement is also formed in the JTAG bus controller in China. However, these achievements are mainly applied to board-level systems, and a JTAG bus controller is generally adopted to complete the test control of the object to be tested. The test research for the SIP chip in the mass production stage is less, and from the existing complex SIP microsystem chip test technology, the test is generally performed by adopting a functional test mode. The function testing method needs to complete complex function code stream loading through an ATE system, and is difficult to complete function verification in cooperation with the ATE system for some complex interfaces (such as EMIF, PCIE, SRIO and the like); secondly, when the functional test fails, accurate fault location is difficult to carry out. A special internal interconnection testing method for the mass production stage of SIP chips is urgently needed to be researched.

When the JTAG bus controller is not designed in the SIP chip and on the periphery of the DIB board, the ATE test system needs to complete the receiving and transmitting of the JTAG bus test time sequence. However, writing the JTAG bus test vector manually in the ATE system is complicated, and a new method for generating the JTAG bus test vector is urgently needed.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides an SIP chip internal interconnection testing method based on ATE.

The purpose of the invention is realized by the following technical scheme:

an internal interconnection test method of an SIP chip based on ATE (automatic test equipment), comprising the following steps of:

s1, compiling an interconnection test program by the SVF;

s2, analyzing the written SVF program into a pattern capture format file;

s3, processing the vector which accords with the JTAG bus time sequence in the mode capture format file;

and S4, transplanting the obtained test time sequence into an ATE test system, and carrying out interconnection test according to the specific form of the interconnection model in the SIP chip.

Further, in step S4, the interconnection model in the SIP chip includes a logic cluster interconnection model, a memory interconnection model, an ATE cooperative interconnection model, a scan chain interconnection model, and an ATE direct connection model.

Further, in the case of using a logic cluster interconnection model or a memory interconnection model, all IO ports of the NBS device are surrounded by scan links, a boundary scan cell connected to an input end of the NBS device is set to an input mode, a boundary scan cell connected to an output port is set to a sampling mode, and an test instruction is used for testing.

Further, the specific test steps are as follows:

step S411: the instruction register sends an EXTEST test instruction;

step S412: sending a periodic test excitation to an NBS input port through a boundary scanning unit connected with the NBS input port;

step S413: the boundary scanning unit connected with the NBS output port receives the test response and the expected value of the first test period to analyze, and meanwhile, the boundary scanning unit of the input end continues to send the test excitation of the second period;

the test can be completed by repeating step S413.

Further, in the case of the ATE collaborative interconnect model, the NBS circuit is surrounded by scan links, with input ports connected to the boundary scan links and output ports connected directly to the ATE system.

Further, the specific test steps are as follows:

step S421: the instruction register sends a pre-installed instruction;

step S422: sending a first test vector to a boundary scanning unit connected with the NBS device through a TDI pin, wherein the first test excitation does not act on an input port of the NBS device;

step S423: the instruction register loads an external test instruction, and the first test excitation sent by the preinstalled instruction acts on the input end of the NBS device;

step S424: the ATE end receives the first test response of the NBS device, compares the first test response with an expected value, and simultaneously the TDI port sends a second test excitation;

the step S424 is repeated to complete the verification of the test vectors of the NBS device for all cycles.

Further, in the case of using the scan chain interconnection model, half of the network ports are used as input terminals, and half of the network ports are used as output terminals, and the setting of the input terminal data and the reading of the output terminal data are completed through the boundary scan unit.

Further, the specific test steps are as follows:

step S431: the instruction register sends a pre-installed instruction;

step S432: sending a first test vector to a boundary scanning unit of a BS1 device through a TDI pin;

step S433: the instruction register loads an external test instruction;

step S434: the terminal boundary scanning unit of the BS2 device receives the first test response, compares the first test response with an expected value, and simultaneously sends a second test excitation through the TDI port;

the step S434 is repeated to complete the test.

Further, in the case of using the ATE direct model, the boundary scan cell pins of the BS device are directly connected to the digital channels of the ATE system.

Further, the specific test steps are as follows:

step S441: the instruction register sends a preassembly instruction;

step S442: sending a first test vector to a boundary scanning unit connected with a BS device through a TDI pin;

step S443: the instruction register loads an external test instruction;

step S444: the ATE end receives the first test response, compares the first test response with an expected value, and simultaneously sends a second test excitation through the TDI port;

the step S444 is repeated to complete the test.

The NBS device represents a Non-Boundary Scan (NBS) device;

the BS device denotes a Boundary Scan (BS) device.

The invention has the beneficial effects that:

aiming at different interconnection models between the SIP chip and the ATE system, the JTAG bus test time sequence is generated efficiently and quickly, and the test efficiency is improved.

Drawings

FIG. 1 is a flowchart of an ATE-based SIP chip internal interconnection testing method according to an embodiment of the present invention;

FIG. 2 is a schematic illustration of an SVF program according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a PCF file converted according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a test timing sequence according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of the structure of a logic cluster interconnect model and a memory interconnect model according to an embodiment of the invention;

FIG. 6 is a schematic diagram of an ATE collaborative interconnection model according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a scan chain interconnect model according to an embodiment of the present invention;

fig. 8 is a schematic diagram of an ATE direct-connection model according to an embodiment of the present invention.

Detailed Description

The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

The first embodiment is as follows:

as shown in fig. 1, the method for testing internal interconnection of an SIP chip based on ATE provided in the embodiment of the present invention specifically includes the following steps:

and S1, writing an interconnection test program by the SVF. The SVF language is mature in industrial field, is a high-level description of JTAG bus operation, and has a program loading and boundary scan test logic description of a programmable device in a main application scene, wherein the program loading and the boundary scan test logic description are both based on a JTAG interface to complete corresponding operation. In both the Quartus development environment and the ISE development environment, SVF files for describing programming can be generated, and decoding and program online loading of the SVF files are completed through an emulator and a JTAG interface. SVF is also commonly used for board level JTAG interconnection testing, in addition to its application in CPLD, FPGA programmable devices. In the JTAG interconnection test, SVF is mainly used for describing a test flow and a test method and has good readability and universality. Table 1 shows the correspondence between the state of the IEEE1149.1 state machine and the SVF instruction, and as shown in table 1, some test instructions forcibly specified in the SVF correspond to the state of the JTAG state machine in the IEEE1149.1 one by one. In the boundary scan test, mainly through the switching of the state machine state, the test instruction setting and the test data sending and receiving are performed, and the SVF statement can describe the process in detail. Therefore, a corresponding SVF test program can be compiled according to specific test requirements, and then the SVF test files are converted into a test time sequence conforming to the JTAG bus, so that the test can be completed on an ATE test platform.

IEEE11.49.1 State name	SVF instruction
		Test-Logic-Reset	RESET
Run-Test/Idle	IDLE
		Select-DR-Scan	DRSELECT
Capture-DR	DRCAPTURE
		Shift-DR	DRSHIFT
Exit1-DR	DREXIT1
		……	……
Exit1-IR	IREXIT1
		Pause-IR	IRPAUSE
Exit2-IR	IREXIT2
		Update-IR	IRUPDATE

TABLE 1

And S2, analyzing the written SVF program into a Pattern Capture Format (PCF) file. Specifically, taking the SVF program shown in fig. 2 as an example for explanation, firstly, the first 14 rows of the SVF program are used to control the JTAG state machine to Run-Test/Idle state, so as to prepare for the subsequent Instruction register operation and data register operation, and as can be known from the state machine switching principle of TAPC, no matter where the initial state of the state machine is, as long as the state control pin TMS sends out a high level signal for 5 and more than 5 clock cycles, the state machine will jump to Run-Test/Idle state, the Test vector generated in the PCF file after the SVF program of the first 14 rows is transcoded is the Test Logic Reset part in fig. 3, the Test Logic Reset part describes the level state of each clock cycle restck, TMS, TDI, TDO, and TDO in turn, and then the IDCODE command SIR 6TDI (04) MASK (3 f) is sent to the Instruction register, wherein SIR is the command sent by the command register, the next 6 represents the length of the command register of the target Device, TDI (04) represents writing "000100" IDCODE command from the TDI port to the command register, MASK (3 f) represents that the data input from the previous TDI port is valid With the lower 6 bits, the SIR 6TDI (04) MASK (3 f) program corresponds to the Test vector in the PCF file, such as the Loading Device With "IDCODE" Instruction part of FIG. 3, after writing the IDCODE command to the command register, the identification register of the Device is connected in the TDI/TDO link, SDR32TDI (00000000) SMASK (00000000) TDO (000 ae02 f) MASK (ffffffff) program is used to complete the reading and verification of the Device identification, wherein SDR is the data register operation command, known from the BSDL file, the identification data of the Device is 000aef 02TMS, the TMS port control state machine operates to the Shift-DR state, and shifting the identification information out of the TDO port at the falling edge of the CLK clock, and returning the TMS control state machine to a Run-Test/Idle state after ID data reading is completed, wherein the corresponding Test vector in the PCF file is as shown in a ReadID part of FIG. 3.

And S3, processing the vector which accords with the JTAG bus time sequence in the mode capture format (PCF) file. Taking the PCF file shown in fig. 3 as an example, the Test Logic Reset part, the Loading Device With "IDCODE" Instruction part, and the ReadID part in the file are converted into Test timing sequences, and the specific form is shown in fig. 4.

And S4, transplanting the obtained test time sequence into an ATE test system, and carrying out interconnection test according to the specific form of the interconnection model in the SIP chip. The interconnection model in the SIP chip includes a logic cluster interconnection model, a memory interconnection model, an ATE cooperative interconnection model, a scan chain interconnection model, an ATE direct connection model, and other models.

As shown in fig. 5, in the logic cluster interconnection model, all IO pins of the non-boundary scan device are all connected to the boundary scan chain, which is common in the SIP chip, the logic cluster interconnection model is very similar to the memory interconnection model, and all IO pins of the NBS device are connected to the boundary scan chain, so the above model may also be referred to as the memory interconnection model.

All IO ports of the NBS device are surrounded by scanning links, a boundary scanning unit connected with an input end of the NBS device is set to be in an input mode, a boundary scanning unit connected with an output end of the NBS device is set to be in a sampling mode, an EXTEST testing instruction is adopted for testing, and the specific testing steps are as follows:

step S411: the instruction register sends an EXTEST test instruction;

step S412: sending a periodic test excitation to an NBS input port through a boundary scanning unit connected with the NBS input port;

step S413: and the boundary scanning unit connected with the NBS output port receives the test response and the expected value of the first test period to analyze, and meanwhile, the boundary scanning unit at the input end continues to send the test excitation of the second period.

The step S413 is repeated to complete the test of the logical cluster model.

As shown in fig. 6, the NBS circuit in the ATE collaborative interconnection model is surrounded by the scan link, the input port is connected to the boundary scan link, and the output port is directly connected to the ATE system, and the specific test steps are as follows:

step S421: the instruction register sends a preassembly instruction;

step S422: sending a first test vector to a boundary scanning unit connected with the NBS device through a TDI pin, wherein the first test excitation does not act on an input port of the NBS device;

step S423: the instruction register loads an external test instruction, and the first test excitation sent by the preinstalled instruction acts on the input end of the NBS device;

step S424: the ATE terminal receives the first test response of the NBS device, compares it to an expected value, and the TDI port sends a second test stimulus.

The verification of the test vectors of the NBS device can be completed by repeating step S424.

As shown in fig. 7, the boundary scan cells of two BS devices are interconnected in a scan chain interconnect model, all interconnect ports being connected to boundary scan links, which is also common in SIP chips. The test method aiming at the scan chain interconnection model still continues the test method in the board-level interconnection test system, uses half network ports as input ends and half network ports as output ends, and completes the setting of input end data and the reading of output end data through a boundary scan unit, and the specific test steps are as follows:

step S431: the instruction register sends a preassembly instruction;

step S432: sending a first test vector to a boundary scanning unit of a BS1 device through a TDI pin;

step S433: the instruction register loads an external test instruction;

step S434: and the boundary scanning unit of the BS2 device receives the first test response, compares the first test response with an expected value, and simultaneously sends a second test excitation through the TDI port.

The step S434 is repeatedly executed to complete the test of the scan chain interconnection model.

As shown in fig. 8, the IO port of the boundary scan device in the ATE direct connection model is directly physically connected to the ATE. Aiming at the test of an ATE direct connection model, an ATE system can serve as an input end to send high and low levels, and a boundary scanning unit detects high and low time sequences sent by the ATE, so that the test of an ATE direct connection network is completed. Otherwise, the boundary scan cell is used as an input terminal to send high and low levels, and the ATE terminal detects the high and low levels sent by the boundary scan cell. The method comprises the following steps of directly connecting a boundary scanning unit pin of a BS device with a digital channel of an ATE system, and specifically testing the method as follows:

step S441: the instruction register sends a pre-installed instruction;

step S442: sending a first test vector to a boundary scanning unit connected with a BS device through a TDI pin;

step S443: the instruction register loads an external test instruction;

step S444: the ATE end receives the first test response, compares it to an expected value, and the TDI port sends a second test stimulus.

The step S444 is repeated to complete the testing of the ATE direct-connection model.

The above-mentioned embodiments only express the specific embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention.

Claims (10)

1. An internal interconnection test method of an SIP chip based on ATE (automatic test equipment), which is characterized by comprising the following steps:

s1, compiling an interconnection test program by the SVF;

s2, analyzing the written SVF program into a pattern capture format file;

s3, processing the vector which accords with the JTAG bus time sequence in the mode capture format file;

and S4, transplanting the obtained test time sequence into an ATE test system, and carrying out interconnection test according to the specific form of the interconnection model in the SIP chip.

2. The ATE-based SIP chip internal interconnection testing method of claim 1, wherein in the step S4, the interconnection models in the SIP chip comprise a logic cluster interconnection model, a memory interconnection model, an ATE cooperative interconnection model, a scan chain interconnection model and an ATE direct connection model.

3. The ATE-based SIP chip internal interconnect testing method of claim 2, wherein in case of using a logic cluster interconnect model or a memory interconnect model, all IO ports of the NBS device are surrounded by scan links, the boundary scan cells connected to the input ports of the NBS device are set to input mode, the boundary scan cells connected to the output ports are set to sampling mode, and testing is performed using the test instructions EXTEST.

4. The ATE-based SIP chip internal interconnection testing method of claim 3, wherein the specific testing steps are as follows:

step S411: the instruction register sends an EXTEST test instruction;

step S412: sending a periodic test excitation to an NBS input port through a boundary scanning unit connected with the NBS input port;

step S413: the boundary scanning unit connected with the NBS output port receives the test response and the expected value of the first test period to analyze, and meanwhile, the boundary scanning unit of the input end continues to send the test excitation of the second period;

the test can be completed by repeating step S413.

5. The ATE-based SIP chip internal interconnect testing method of claim 2, wherein the NBS circuit is surrounded by scan links, input ports are connected to boundary scan links, and output ports are connected directly to the ATE system, using an ATE co-interconnect model.

6. The ATE-based SIP chip internal interconnection testing method of claim 5, wherein the specific testing steps are as follows:

step S421: the instruction register sends a pre-installed instruction;

step S422: sending a first test vector to a boundary scanning unit connected with the NBS device through a TDI pin, wherein the first test excitation does not act on an input port of the NBS device;

step S423: the instruction register loads an external test instruction, and the first test excitation sent by the preinstalled instruction acts on the input end of the NBS device;

step S424: the ATE end receives a first test response of the NBS device, the first test response is compared with an expected value, and the TDI port sends a second test excitation;

the verification of the test vectors of the NBS device can be completed by repeating step S424.

7. The method for testing the internal interconnection of the ATE-based SIP chip as claimed in claim 2, wherein in case of employing the scan chain interconnection model, half of the network ports are used as input ports and half of the network ports are used as output ports, and the setting of the input port data and the reading of the output port data are completed by the boundary scan cell.

8. The ATE-based SIP chip internal interconnection testing method of claim 7, wherein the specific testing steps are as follows:

step S431: the instruction register sends a pre-installed instruction;

step S432: sending a first test vector to a boundary scanning unit of a BS1 device through a TDI pin;

step S433: the instruction register loads an external test instruction;

step S434: the terminal boundary scanning unit of the BS2 device receives the first test response, compares the first test response with an expected value, and simultaneously sends a second test excitation through the TDI port;

the step S434 is repeated to complete the test.

9. The ATE-based SIP chip internal interconnection testing method of claim 2, wherein the boundary scan cell pins of the BS device are directly connected to the digital channels of the ATE system using the ATE direct connection model.

10. The method for testing the internal interconnections of the ATE-based SIP chip, according to claim 9, wherein the specific testing steps are as follows:

step S441: the instruction register sends a pre-installed instruction;

step S442: sending a first test vector to a boundary scanning unit connected with a BS device through a TDI pin;

step S443: the instruction register loads an external test instruction;

step S444: the ATE end receives the first test response, compares the first test response with an expected value, and simultaneously sends a second test excitation through the TDI port;

the step S444 is repeated to complete the test.

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