CN111030691A - Reliability verification method and system based on analog-to-digital converter - Google Patents
Reliability verification method and system based on analog-to-digital converter Download PDFInfo
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Abstract
The invention discloses a reliability verification method and a system based on an analog-to-digital converter, wherein the method comprises the following steps: s1, providing a test signal and sending the test signal to a logic digital unit in the analog-to-digital converter; s2, extracting the quiescent current and/or output signals of the logic digital unit; and S3, judging whether the logic in the logic digital unit is normal according to the quiescent current and/or the output signal under different clock cycles. The invention introduces a reliability verification mechanism aiming at the logic digital unit of the ADC, the verification circuit is simple and effective, and the reliability verification of the logic digital unit can be realized by testing the quiescent current IDDQ and/or comparing the output code pattern.
Description
Technical Field
The invention belongs to the technical field of analog-to-digital conversion, and particularly relates to a reliability verification method and system based on an analog-to-digital converter.
Background
Referring to fig. 1, an Analog to Digital Converter (ADC) generally includes an Analog unit and a Logic Digital unit (Logic), where the Logic Digital unit (Logic) receives an output signal of a Comparator in the Analog unit, and CLK is a clock signal of the Logic Digital unit.
In the prior art, a logic digital unit usually cannot be Designed For Test (DFT), when an ADC is abnormal, the problem that an analog unit and a digital part of the ADC cannot be distinguished, and the problem that a chip reaches the whole logic link of an upper computer cannot be distinguished exist, so that a greater reliability risk exists, and the problem positioning time is long when the ADC is abnormal.
Therefore, in view of the above technical problems, it is desirable to provide a method and a system for verifying reliability based on an analog-to-digital converter.
Disclosure of Invention
The invention aims to provide a reliability verification method and a system based on an analog-to-digital converter, so as to realize the reliability verification of a logic digital unit of the analog-to-digital converter.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a method of analog-to-digital converter-based reliability verification, the method comprising:
s1, providing a test signal and sending the test signal to a logic digital unit in the analog-to-digital converter;
s2, extracting the quiescent current and/or output signals of the logic digital unit;
and S3, judging whether the logic in the logic digital unit is normal according to the quiescent current and/or the output signal under different clock cycles.
In one embodiment, the step S3 includes:
judging whether the logic in the logic digital unit is normal or not according to the quiescent currents in different clock periods;
if the quiescent current under different clock periods is within a preset current range, judging that the logic in the logic digital unit is normal;
and if the quiescent current under different clock periods is out of the preset current range, judging that the logic in the logic digital unit is abnormal.
In one embodiment, the step S3 includes:
judging whether the logic in the logic digital unit is normal or not according to the output signal;
if the code pattern of the output signal is the same as that of the test signal, judging that the logic in the logic digital unit is normal;
and if the code pattern of the output signal is different from the code pattern of the test signal, judging that the logic in the logic digital unit is abnormal.
In one embodiment, the test signal is 0/1 codes output by the pattern generator.
In one embodiment, the method further comprises:
the logic digital unit receives a test signal or an output signal of the analog unit through the gate;
under the reliability verification state, the logic digital unit receives a test signal through a gate;
under the normal working state of the analog-digital converter, the logic digital unit receives the output signal of the analog unit through the gate.
The technical scheme provided by one embodiment of the invention is as follows:
an analog-to-digital converter-based reliability verification system, the system comprising:
the test signal providing unit is used for providing a test signal and sending the test signal to a logic digital unit in the analog-to-digital converter;
the current/signal extraction unit is used for extracting the quiescent current and/or the output signal of the logic digital unit;
and the logic judgment unit is used for judging whether the logic in the logic digital unit is normal or not according to the quiescent current and/or the output signal under different clock cycles.
In one embodiment, the logic determining unit is configured to:
judging whether the logic in the logic digital unit is normal or not according to the quiescent currents in different clock periods;
if the quiescent current under different clock periods is within a preset current range, judging that the logic in the logic digital unit is normal;
and if the quiescent current under different clock periods is out of the preset current range, judging that the logic in the logic digital unit is abnormal.
In one embodiment, the logic determining unit is configured to:
judging whether the logic in the logic digital unit is normal or not according to the output signal;
if the code pattern of the output signal is the same as that of the test signal, judging that the logic in the logic digital unit is normal;
and if the code pattern of the output signal is different from the code pattern of the test signal, judging that the logic in the logic digital unit is abnormal.
In one embodiment, the test signal providing unit is a pattern generator, and the test signal provided by the pattern generator is 0/1 codes.
In one embodiment, the system further comprises a gate, wherein the input end of the gate is respectively connected with the analog unit and the test signal providing unit, and the output end of the gate is connected with the logic digital unit.
Compared with the prior art, the invention has the following advantages:
the invention introduces a reliability verification mechanism aiming at the logic digital unit of the ADC, the verification circuit is simple and effective, and the reliability verification of the logic digital unit can be realized by testing the quiescent current IDDQ and/or comparing the output code pattern;
the invention can provide guidance for positioning the abnormal problem of the ADC, can rapidly distinguish the problems of an analog-digital converter analog unit, a logic digital unit and the whole logic link from a chip to an upper computer, and greatly shortens the time for positioning the abnormal problem of the ADC;
the invention can be applied to the verification of the logic reliability of the ADC with different structures.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a block diagram of an analog-to-digital converter in the prior art;
FIG. 2 is a schematic flow chart of a method for verifying reliability based on an analog-to-digital converter according to the present invention;
FIG. 3 is a block diagram of an analog-to-digital converter-based reliability verification system according to the present invention;
fig. 4 is a block diagram of an analog-to-digital converter in embodiments 1 and 2 of the present invention.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.
Referring to fig. 2, the invention discloses a reliability verification method based on an analog-to-digital converter, comprising:
s1, providing a test signal and sending the test signal to a logic digital unit in the analog-to-digital converter;
s2, extracting the quiescent current and/or output signals of the logic digital unit;
and S3, judging whether the logic in the logic digital unit is normal according to the quiescent current and/or the output signal under different clock cycles.
Referring to fig. 3, the present invention also discloses a reliability verification system based on an analog-to-digital converter, including:
the test signal providing unit is used for providing a test signal and sending the test signal to a logic digital unit in the analog-to-digital converter;
the current/signal extraction unit is used for extracting the quiescent current and/or the output signal of the logic digital unit;
and the logic judgment unit is used for judging whether the logic in the logic digital unit is normal or not according to the quiescent current and/or the output signal under different clock cycles.
The present invention is further illustrated by the following specific examples.
Example 1:
fig. 4 is a block diagram of the reliability verification system based on the ADC in this embodiment, in which the ADC includes an analog unit 10 and a logic digital unit 20, a data path inside the logic digital unit 20 is a string of D flip-flops, and the D flip-flops also include other combinational logics, which will not be described in detail in the present invention.
The test signal providing unit in this embodiment is a Pattern generator (Pattern) 30, and the test signal provided by the Pattern generator 30 is 0/1 codes, through which the reliability verification of the logic digital unit 20 is implemented.
In addition, in the embodiment, a gate 40 is further provided, and an input end of the gate 40 is connected to the analog unit 10 and the code pattern generator 30, respectively, and an output end thereof is connected to the logic digital unit 20.
The selection of the working signal and the test signal is realized through the gate, and the logic digital unit 20 receives the test signal through the gate 40 in the reliability verification state; in the normal operation of the analog-to-digital converter, the logic digital unit 20 receives the output signal of the analog unit 10 through the gate 40.
The reliability verification method based on the analog-to-digital converter in this embodiment specifically includes the following steps:
and S1, providing a test signal and sending the test signal to a logic digital unit in the analog-to-digital converter.
The Pattern generator 30 outputs a test signal after receiving the CONVST signal, and the gate selects the output signal of the Pattern generator as the input signal of the logic digital unit 20 in the reliability verification state, and further injects 0/1 codes into the logic digital unit 20.
And S2, extracting the quiescent current of the logic digital unit.
Since the injected code pattern is a toggle pattern of 0/1, each node of the data path will toggle (including combinational logic in the middle of D flip-flops, etc.) in different clock CLK periods, and whether the logic of the logic digital unit is normal can be determined by testing the quiescent current IDDQ in different clock periods.
And S3, judging whether the logic in the logic digital unit is normal according to the quiescent current in different clock cycles.
Judging whether the logic in the logic digital unit is normal or not through the quiescent current specifically comprises the following steps:
if the quiescent current under different clock periods is within a preset current range, judging that the logic in the logic digital unit is normal; and if the quiescent current under different clock periods is out of the preset current range, judging that the logic in the logic digital unit is abnormal.
The preset current range needs to be set according to different ADCs, and values of the preset current ranges in the different ADCs are different.
Example 2:
different from embodiment 1, embodiment 1 realizes the logic judgment by extracting the quiescent current IDDQ of the logic digital unit 20, but in this embodiment, the logic of the logic digital unit is judged by the output signal of the logic digital unit, and the modules of the reliability verification system are completely the same as those in embodiment 1, and are not described again here.
The reliability verification method based on the analog-to-digital converter in this embodiment specifically includes the following steps:
and S1, providing a test signal and sending the test signal to a logic digital unit in the analog-to-digital converter.
The Pattern generator 30 outputs a test signal after receiving the CONVST signal, and the gate selects the output signal of the Pattern generator as the input signal of the logic digital unit 20 in the reliability verification state, and further injects 0/1 codes into the logic digital unit 20.
And S2, extracting the output signal of the logic digital unit.
Because the injected code pattern is a toggle pattern of 0/1, each node of the data path will toggle (including combinational logic in the middle of D flip-flops, etc.) in different clock CLK periods, and whether the logic of the logic digital unit is normal can be determined by testing the output signal DOUT _ DFT of the logic digital unit 20.
And S3, judging whether the logic in the logic digital unit is normal according to the output signal.
Judging whether the logic in the logic digital unit is normal or not through the output signal specifically comprises the following steps:
if the code pattern of the output signal DOUT _ DFT is the same as that of the test signal, judging that the logic in the logic digital unit is normal; if the pattern of the output signal DOUT _ DFT is different from the pattern of the test signal, the logic in the logic digital unit is determined to be abnormal.
It should be understood that, in the above embodiments, the quiescent current IDDQ and the output signal DOUT _ DFT of the logic digital unit are extracted separately for reliability verification, and in other embodiments, the quiescent current IDDQ and the output signal DOUT _ DFT may be extracted simultaneously for reliability verification, and when both satisfy the condition, the logic of the logic digital unit is determined to be normal, otherwise, the logic is determined to be abnormal.
The technical scheme shows that the invention has the following beneficial effects:
the invention introduces a reliability verification mechanism aiming at the logic digital unit of the ADC, the verification circuit is simple and effective, and the reliability verification of the logic digital unit can be realized by testing the quiescent current IDDQ and/or comparing the output code pattern;
the invention can provide guidance for positioning the abnormal problem of the ADC, can rapidly distinguish the problems of an analog-digital converter analog unit, a logic digital unit and the whole logic link from a chip to an upper computer, and greatly shortens the time for positioning the abnormal problem of the ADC;
the invention can be applied to the verification of the logic reliability of the ADC with different structures.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A reliability verification method based on an analog-to-digital converter is characterized by comprising the following steps:
s1, providing a test signal and sending the test signal to a logic digital unit in the analog-to-digital converter;
s2, extracting the quiescent current and/or output signals of the logic digital unit;
and S3, judging whether the logic in the logic digital unit is normal according to the quiescent current and/or the output signal under different clock cycles.
2. The analog-to-digital converter-based reliability verification method according to claim 1, wherein the step S3 comprises:
judging whether the logic in the logic digital unit is normal or not according to the quiescent currents in different clock periods;
if the quiescent current under different clock periods is within a preset current range, judging that the logic in the logic digital unit is normal;
and if the quiescent current under different clock periods is out of the preset current range, judging that the logic in the logic digital unit is abnormal.
3. The analog-to-digital converter-based reliability verification method according to claim 1, wherein the step S3 comprises:
judging whether the logic in the logic digital unit is normal or not according to the output signal;
if the code pattern of the output signal is the same as that of the test signal, judging that the logic in the logic digital unit is normal;
and if the code pattern of the output signal is different from the code pattern of the test signal, judging that the logic in the logic digital unit is abnormal.
4. The analog-to-digital converter based reliability verification method according to any of claims 1 to 3, wherein the test signal is 0/1 codes output by a pattern generator.
5. The analog-to-digital converter based reliability verification method according to any of claims 1 to 3, characterized in that the method further comprises:
the logic digital unit receives a test signal or an output signal of the analog unit through the gate;
under the reliability verification state, the logic digital unit receives a test signal through a gate;
under the normal working state of the analog-digital converter, the logic digital unit receives the output signal of the analog unit through the gate.
6. An analog-to-digital converter based reliability verification system, the system comprising:
the test signal providing unit is used for providing a test signal and sending the test signal to a logic digital unit in the analog-to-digital converter;
the current/signal extraction unit is used for extracting the quiescent current and/or the output signal of the logic digital unit;
and the logic judgment unit is used for judging whether the logic in the logic digital unit is normal or not according to the quiescent current and/or the output signal under different clock cycles.
7. The analog-to-digital converter based reliability verification system of claim 6, wherein the logic determination unit is configured to:
judging whether the logic in the logic digital unit is normal or not according to the quiescent currents in different clock periods;
if the quiescent current under different clock periods is within a preset current range, judging that the logic in the logic digital unit is normal;
and if the quiescent current under different clock periods is out of the preset current range, judging that the logic in the logic digital unit is abnormal.
8. The analog-to-digital converter based reliability verification system of claim 6, wherein the logic determination unit is configured to:
judging whether the logic in the logic digital unit is normal or not according to the output signal;
if the code pattern of the output signal is the same as that of the test signal, judging that the logic in the logic digital unit is normal;
and if the code pattern of the output signal is different from the code pattern of the test signal, judging that the logic in the logic digital unit is abnormal.
9. The analog-to-digital converter based reliability verification system according to any of claims 6 to 8, characterized in that the test signal providing unit is a pattern generator, and the test signal provided by the pattern generator is 0/1 codes.
10. The analog-to-digital converter based reliability verification system according to any of claims 6 to 8, characterized in that the system further comprises a gate, the input terminals of which are connected to the analog unit and the test signal providing unit, respectively, and the output terminal of which is connected to the logic digital unit.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106802388A (en) * | 2016-12-23 | 2017-06-06 | 北京时代民芯科技有限公司 | A kind of test module of hybrid digital-analog integrated circuit |
| CN109581205A (en) * | 2018-11-16 | 2019-04-05 | 北京时代民芯科技有限公司 | A kind of high-speed digital-analog conversion circuit single-ion transient state effect appraisal procedure and system |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106802388A (en) * | 2016-12-23 | 2017-06-06 | 北京时代民芯科技有限公司 | A kind of test module of hybrid digital-analog integrated circuit |
| CN109581205A (en) * | 2018-11-16 | 2019-04-05 | 北京时代民芯科技有限公司 | A kind of high-speed digital-analog conversion circuit single-ion transient state effect appraisal procedure and system |
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