CN106783613A - 一种iii‑v族半导体moshemt器件及其制备方法 - Google Patents
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Abstract
本发明公开一种III‑V族半导体MOSHEMT器件及其制备方法,其组分渐变缓冲层降低III‑V半导体之间晶格失配,减少位错引进的缺陷。同时该器件结构不仅降低MOS界面态密度,并且通过对外延材料采用高In组分In0.7Ga0.3As/In0.6Ga0.4As/In0.5Ga0.5As复合沟道设计以及势垒层和缓冲层平面处的双掺杂设计充分的提高了2‑DEG的浓度与电子迁移率,降低了沟道的方块电阻。本发明具有二维电子气浓度高、沟道电子迁移率大、器件特征频率和振荡频率高和制造工艺简单易于实现等特点。
Description
技术领域
本发明涉及半导体器件技术领域,具体涉及一种III-V族半导体MOSHEMT器件及其制备方法。
背景技术
目前半导体工业的主流是硅技术,随着半导体技术最小尺寸发展到纳米尺度,硅集成电路技术日益逼近其理论和技术的双重极限。而III-V族半导体材料相比硅材料具有更高的电子迁移率(6-60倍)和在低电场和强场下具有更加优异的电子输运性能等特性,因此,III-V族半导体材料将是新一代超高频低功耗集成电子系统的必然选择。
然而,传统的GaAs HEMT的沟道二维电子气浓度和电子迁移率,受材料结构的影响无法做到使得导电沟道电子迁移率与二维电子气浓度均很大,限制了GaAs HEMT器件在微波通信中的发展。需要在III-V族半导体上采用新的器件结构,以充分发挥III-V族半导体材料的特性,增强沟道中二维电子气浓度与电子迁移率。由于InP衬底的制造成本较高,材质较脆,不利于的推广,所以利用在GaAs衬底采用新的器件结构,使得GaAs HEMT器件具有很强的实用性与利用价值。
发明内容
本发明所要解决的技术问题是现有HEM器件导电沟道电子迁移率与二维电子气浓度无法同时做到更大的问题,提供一种III-V族半导体MOSHEMT器件及其制备方法。
为解决上述问题,本发明是通过以下技术方案实现的:
一种III-V族半导体MOSHEMT器件的制备方法,包括如下步骤:
步骤S1:在单晶衬底上外延形成变In组分InxAl1-xAs缓冲层;
步骤S2:在变In组分InxAl1-xAs缓冲层上外延形成In0.52Al0.48As缓冲层;
步骤S3:在In0.52Al0.48As缓冲层上外延生长第一层In0.5Ga0.5As沟道层;
步骤S4:在第一层In0.7Ga0.3As沟道层外延生长第二层In0.6Ga0.4As沟道层;
步骤S5:在第二层In0.6Ga0.4As沟道层外延生长第三层In0.5Ga0.5As沟道层;
步骤S6:在第三层In0.5Ga0.5As沟道层外延形成In0.52Al0.48As势垒层;
步骤S7:在In0.52Al0.48As势垒层上外延形成重掺杂的窄带隙欧姆接触层;
步骤S8:在步骤S7所得的外延结构的窄带隙欧姆接触层中刻出有源区,该有源区刻至In0.52Al0.48As势垒层;
步骤S9:在窄带隙欧姆接触层的上方形成源漏金属;
步骤S10:对源漏金属进行腐蚀,形成栅槽;
步骤S11:在有源区和栅槽中生长栅介质;
步骤S12:在栅介质上形成T形的栅金属。
在步骤S5之前还进一步包括,在In0.52Al0.48As缓冲层中形成第一平面掺杂层的步骤。
在步骤S6之前还进一步包括,在第三层In0.5Ga0.5As沟道层中形成第二平面掺杂层的步骤。
步骤S8中,采用光刻或刻蚀在窄带隙欧姆接触层中刻出有源区。
步骤S12中,栅金属采用两次电子束曝光一次显影形成。
步骤S1中,单晶衬底为GaAs族的单晶衬底。
一种III-V族半导体MOSHEMT器件,包括单晶衬底、变In组分InxAl1-xAs缓冲层、In0.52Al0.48As缓冲层、第一层In0.7Ga0.3As沟道层、第二层In0.6Ga0.4As沟道层、第三层In0.5Ga0.5As沟道层、In0.52Al0.48As势垒层、窄带隙欧姆接触层、源漏金属、栅介质和栅金属;单晶衬底、变In组分InxAl1-xAs缓冲层、In0.52Al0.48As缓冲层、第一层In0.7Ga0.3As沟道层、第二层In0.6Ga0.4As沟道层、第三层In0.5Ga0.5As沟道层、In0.52Al0.48As势垒层和窄带隙欧姆接触层自下而上依次叠放;窄带隙欧姆接触层的中间部分开设有有源区;源漏金属设置在窄带隙欧姆接触层,源漏金属的中间部分开设有栅槽;栅介质填充在有源区和栅槽中;栅金属呈T形,其下部嵌入栅介质中。
上述方案中,In0.52Al0.48As缓冲层的上部设有第一平面掺杂层。
上述方案中,第三层In0.5Ga0.5As沟道层的上部设有第二平面掺杂层。
上述方案中,单晶衬底为GaAs族的单晶衬底。
与现有技术相比,本发明的组分渐变缓冲层降低III-V半导体之间晶格失配,减少位错引进的缺陷。同时该器件结构不仅降低MOS界面态密度,并且通过对外延材料采用高In组分In0.7Ga0.3As/In0.6Ga0.4As/In0.5Ga0.5As复合沟道设计以及势垒层和缓冲层平面处的双掺杂设计充分的提高了2-DEG的浓度与电子迁移率,降低了沟道的方块电阻。本发明具有二维电子气浓度高、沟道电子迁移率大、器件特征频率和振荡频率高和制造工艺简单易于实现等特点。
附图说明
图1是一种III-V族半导体MOSHEMT器件的结构示意图。
图2是一种III-V族半导体MOSHEMT器件的制备流程图。
具体实施方式
一种III-V族半导体MOSHEMT器件,如图1所示,包括单晶衬底101、变In组分InxAl1-xAs缓冲层102、In0.52Al0.48As缓冲层103、第一平面掺杂层104、第一层In0.7Ga0.3As沟道层105、第二层In0.6Ga0.4As沟道层106、第三层In0.5Ga0.5As沟道层107、第二平面掺杂层108、In0.52Al0.48As势垒层109、窄带隙欧姆接触层110、源漏金属111、栅介质112和栅金属113。
单晶衬底101、变In组分InxAl1-xAs缓冲层102、In0.52Al0.48As缓冲层103、第一层In0.7Ga0.3As沟道层105、第二层In0.5Ga0.5As沟道层106、第三层In0.6Ga0.4As沟道层107、In0.52Al0.48As势垒层109和窄带隙欧姆接触层110自下而上依次叠放。单晶衬底101为GaAs族的单晶衬底101。第一平面掺杂层104设置在In0.52Al0.48As缓冲层103的上部。第二平面掺杂层108设置在第三层In0.4Ga0.6As沟道层107的上部。
窄带隙欧姆接触层110的中间部分开设有有源区。源漏金属111设置在窄带隙欧姆接触层110,源漏金属111的中间部分开设有栅槽。栅介质112填充在有源区和栅槽中。栅金属113呈T形,其下部嵌入栅介质112中。
一种III-V族半导体MOSHEMT器件的制备方法,如图2所示,其具体包括如下步骤:
S1:在GaAs族衬底片上外延形成变In组分InxAl1-xAs缓冲层102
S2:在变In组分InxAl1-xAs缓冲层102上外延形成In0.52Al0.48As缓冲层103;
S3:在In0.52Al0.48As缓冲层上外延生长第一层In0.5Ga0.5As沟道层105;
S4:在第一层In0.7Ga0.3As沟道层105外延生长第二层In0.6Ga0.4As沟道层106;
S5:在第二层In0.6Ga0.4As沟道层106外延生长第三层In0.5Ga0.5As沟道层107;
S6:在第三层In0.5Ga0.5As沟道层107外延形成In0.52Al0.48As势垒层109;
S7:在In0.52Al0.48As势垒层109上外延形成重掺杂的窄带隙欧姆接触层110;
S8:在以上外延结构上的窄带隙欧姆接触层110处利用光刻和刻蚀工艺形成有源区;有源区得到的方法可以是干法刻蚀,也可以使湿法刻蚀;
S9:在窄带隙欧姆接触层110上形成源漏金属111;源漏金属111采用Ti/Pt/Au金属系统;
S10:在源漏金属111中采用湿法腐蚀方法对栅槽进行腐蚀;
S11:在腐蚀完栅槽后,采用ALD沉积系统在栅槽中生长高K栅介质112;
S12:在高K栅介质112上形成T形的栅金属113。栅金属113采用PMMA/MMA/PMMA胶两次电子束曝光一次显影。
Claims (10)
1.一种III-V族半导体MOSHEMT器件的制备方法,其特征是,包括如下步骤:
步骤S1:在单晶衬底(101)上外延形成变In组分InxAl1-xAs缓冲层(102);
步骤S2:在变In组分InxAl1-xAs缓冲层(102)上外延形成In0.52Al0.48As缓冲层(103);
步骤S3:在In0.52Al0.48As缓冲层(103)上外延生长第一层In0.5Ga0.5As沟道层(105);
步骤S4:在第一层In0.7Ga0.3As沟道层(105)外延生长第二层In0.6Ga0.4As沟道层(106);
步骤S5:在第二层In0.6Ga0.4As沟道层(106)外延生长第三层In0.5Ga0.5As沟道层(107);
步骤S6:在第三层In0.5Ga0.5As沟道层(107)外延形成In0.52Al0.48As势垒层(109);
步骤S7:在In0.52Al0.48As势垒层(109)上外延形成重掺杂的窄带隙欧姆接触层(110);
步骤S8:在步骤S7所得的外延结构的窄带隙欧姆接触层(110)中刻出有源区,该有源区刻至In0.52Al0.48As势垒层(109);
步骤S9:在窄带隙欧姆接触层(110)的上方形成源漏金属(111);
步骤S10:对源漏金属(111)进行腐蚀,形成栅槽;
步骤S11:在有源区和栅槽中生长栅介质(112);
步骤S12:在栅介质(112)上形成T形的栅金属(113)。
2.根据权利要求1所述一种III-V族半导体MOSHEMT器件的制备方法,其特征是:在步骤S5之前还进一步包括,在In0.52Al0.48As缓冲层(103)中形成第一平面掺杂层(104)的步骤。
3.根据权利要求1所述一种III-V族半导体MOSHEMT器件的制备方法,其特征是:在步骤S6之前还进一步包括,在第三层In0.5Ga0.5As沟道层(107)中形成第二平面掺杂层(108)的步骤。
4.根据权利要求1所述一种III-V族半导体MOSHEMT器件的制备方法,其特征是:步骤S8中,采用光刻或刻蚀在窄带隙欧姆接触层(110)中刻出有源区。
5.根据权利要求1所述一种III-V族半导体MOSHEMT器件的制备方法,其特征是:步骤S12中,栅金属(113)采用两次电子束曝光一次显影形成。
6.根据权利要求1所述一种III-V族半导体MOSHEMT器件的制备方法,其特征是:步骤S1中,单晶衬底(101)为GaAs族的单晶衬底(101)。
7.一种III-V族半导体MOSHEMT器件,其特征是,包括单晶衬底(101)、变In组分InxAl1- xAs缓冲层(102)、In0.52Al0.48As缓冲层(103)、第一层In0.7Ga0.3As沟道层(105)、第二层In0.6Ga0.4As沟道层(106)、第三层In0.5Ga0.5As沟道层(107)、In0.52Al0.48As势垒层(109)、窄带隙欧姆接触层(110)、源漏金属(111)、栅介质(112)和栅金属(113);
单晶衬底(101)、变In组分InxAl1-xAs缓冲层(102)、In0.52Al0.48As缓冲层(103)、第一层In0.7Ga0.3As沟道层(105)、第二层In0.6Ga0.4As沟道层(106)、第三层In0.5Ga0.5As沟道层(107)、In0.52Al0.48As势垒层(109)和窄带隙欧姆接触层(110)自下而上依次叠放;
窄带隙欧姆接触层(110)的中间部分开设有有源区;源漏金属(111)设置在窄带隙欧姆接触层(110),源漏金属(111)的中间部分开设有栅槽;栅介质(112)填充在有源区和栅槽中;栅金属(113)呈T形,其下部嵌入栅介质(112)中。
8.根据权利要求7所述一种III-V族半导体MOSHEMT器件,其特征是:In0.52Al0.48As缓冲层(103)的上部设有第一平面掺杂层(104)。
9.根据权利要求7所述一种III-V族半导体MOSHEMT器件,其特征是:第三层In0.5Ga0.5As沟道层(107)的上部设有第二平面掺杂层(108)。
10.根据权利要求7所示的一种III-V族半导体MOSHEMT器件,其特征是,单晶衬底(101)为GaAs族的单晶衬底(101)。
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Application publication date: 20170531 Assignee: GUILIN G-LINK TECHNOLOGY Co.,Ltd. Assignor: GUILIN University OF ELECTRONIC TECHNOLOGY Contract record no.: X2023980046628 Denomination of invention: A III-V semiconductor MOSHEMT device and its preparation method Granted publication date: 20221213 License type: Common License Record date: 20231108 |