CN106772269B - Equivalent sampling circuit for echo signal acquisition by using ground penetrating radar - Google Patents
Equivalent sampling circuit for echo signal acquisition by using ground penetrating radar Download PDFInfo
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- CN106772269B CN106772269B CN201710122963.2A CN201710122963A CN106772269B CN 106772269 B CN106772269 B CN 106772269B CN 201710122963 A CN201710122963 A CN 201710122963A CN 106772269 B CN106772269 B CN 106772269B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/285—Receivers
- G01S7/292—Extracting wanted echo-signals
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01V—GEOPHYSICS; GRAVITATIONAL MEASUREMENTS; DETECTING MASSES OR OBJECTS; TAGS
- G01V3/00—Electric or magnetic prospecting or detecting; Measuring magnetic field characteristics of the earth, e.g. declination, deviation
- G01V3/12—Electric or magnetic prospecting or detecting; Measuring magnetic field characteristics of the earth, e.g. declination, deviation operating with electromagnetic waves
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Abstract
The invention discloses a novel sequential equivalent sampling circuit for processing radar echo signals, wherein the whole sampling circuit comprises a digital signal control circuit, a ps-level pulse generating circuit, a sampling hold circuit and an ADC (analog-to-digital converter) circuit; the digital control signal is a square wave signal with adjustable delay generated by combining a programmable logic gate array with an external crystal oscillator; the ps pulse generating circuit converts the delayed square wave signal into a pulse signal with a ps stage of delay; the sampling and holding circuit is connected with the ps pulse and takes the ps pulse as a sampling and holding signal; the sampling hold circuit stretches and connects the high-frequency pulse signal with the ADC, and finally sends the pulse signal into the analog-to-digital conversion chip. The sequential sampling circuit is very suitable for carrying out A/D conversion on high-frequency signals by using a low-speed ADC, and is beneficial to reducing the cost of the design of the whole sampling circuit.
Description
Technical Field
The invention relates to the field of electronics, in particular to an equivalent sampling circuit for acquiring and processing high-frequency signals by applying ground penetrating radar echo signals.
The background technology is as follows:
in recent years, ultra-wideband ground penetrating radar is applied to structural detection of traffic facilities as a nondestructive detection technology, and since the received signal is ultra-wideband, the pulse is extremely narrow and the frequency is extremely wide. If the ground penetrating radar signal is collected in a real-time sampling manner as used by the conventional ground penetrating radar system, the sampling frequency is at least 2 times greater than the signal frequency. For ultra wideband applications, such as signals with bandwidths greater than 1GHz, high-speed integrated A/D chips or high-speed sampling devices with sampling rates greater than 2GHz are often required due to sampling theorem limitations. While the integrated a/D chip at the current sampling rate of 2GHz is costly, typically in the hundreds of dollars. High-speed sampling equipment also has the defects of high cost, large volume and the like. In addition, the main indexes of a/D conversion include sampling rate and sampling accuracy, and these two indexes are a pair of contradictions in a/D development, so that the a/D chip is often high in sampling rate and low in accuracy, or high in sampling accuracy but low in sampling rate, or is considered in a compromise.
From the current technology and products, the low-speed and low-resolution data acquisition technology is quite mature, the implementation is easy, the single-chip ADC can meet the requirements, and the stability and the reliability of the products are undoubted. While high-speed data acquisition techniques are the leading edge of the information base. At present, the high-speed data acquisition technology in China is relatively backward, is a bottleneck of information technology in China, and has important good and wide prospects in the military and civil fields in China. Currently, the most widely used high-speed data sampling technology is a multi-AD parallel sampling technology and a random sampling technology. However, the data of both of these techniques rely on accurate control circuitry and signal reconstruction circuitry, and thus algorithms in control and signal processing are complex.
The existing data acquisition in foreign countries has the disadvantages of high price, large volume, complex operation, and incapability of well unifying the sampling frequency and the sampling precision. Therefore, although the technology development is relatively early in abroad, a sampling circuit which is relatively cheap and simple to operate still needs to be studied.
In summary, a great deal of work is done by researchers and companies at home and abroad in the aspect of research of the high-speed data acquisition system, but the difference between home and abroad in the aspect of the high-speed data acquisition technology is still great. Domestic high-speed sampling technology is not mature and the feasibility of an acquisition system is not high. And the foreign high-speed data acquisition technology has high feasibility, but is complex to operate and high in price. Therefore, the design of a simple high-speed data sampling system has great significance.
Disclosure of Invention
The invention aims to provide an equivalent sampling circuit capable of simply and efficiently sampling echo signals of a ground penetrating radar.
In order to achieve the above purpose, the present invention adopts the following technical scheme: an equivalent sampling circuit for echo signal acquisition by using a ground penetrating radar, comprising: a two-stage low noise amplifier, a high-speed sampling gate circuit, an ADC conversion circuit, a digital signal control circuit and a ps pulse generation circuit;
the two-stage low-noise amplifier, the high-speed sampling gate circuit and the ADC conversion circuit are connected in sequence, and the ps pulse generating circuit is respectively connected with the digital signal control circuit and the high-speed sampling gate circuit;
the two-stage low-noise amplifier is connected with an antenna for receiving radar echo signals and is used for amplifying signals on the antenna, and the amplified signals are sent to the input end of the high-speed sampling gate circuit through the coupling capacitor to be sampled;
the digital signal control circuit utilizes a programmable logic gate array to combine with an external crystal oscillator to generate a square wave signal with adjustable delay;
the ps pulse generating circuit is used for converting the delayed square wave signal into a ps-stage pulse signal with delay;
the high-speed sampling gate circuit is used for forming a sampling and holding signal with opposite phase by the delayed ps-stage pulse signal, collecting a high-frequency signal part of the amplified radar signal, elongating the high-frequency signal part and sending the high-frequency signal part to the ADC conversion circuit.
Further, the digital signal control circuit adopts a programmable logic gate array to control D0-D9 of the MC100E195B chip to control the delay of the square wave signal.
Further, the delay is a 10ps step delay.
Further, the ps pulse generating circuit comprises an avalanche circuit, the avalanche circuit comprises an avalanche triode, a direct current bias circuit and a differential shaping network, the stepping delay square wave signal extracts the edge of a pulse through the differential shaping network, the duty ratio of the square wave signal is reduced, and the delayed square wave signal is used as an input signal of the avalanche triode and is shaped by combining the avalanche multiplication effect of the avalanche triode with the shaping network to form a delay ps-stage pulse signal.
Further, the differential constant τ of the differential shaping network is less than the width of the positive pulse edge.
Further, the high-speed sampling gate circuit comprises a triode Q2 and a sampling gate circuit, the base level of the triode Q2 is connected with the ps pulse generating circuit, the collector is connected with the sampling gate circuit, and the emitter is grounded.
Further, the sampling gate circuit comprises a triode Q3, a triode Q4, a triode Q5 and a holding capacitor, wherein the collector of the triode Q2 is connected with the base of the triode Q4, the emitter of the triode Q4 is connected with the emitter of the triode Q3, the collector of the triode Q4 is connected with the emitter of the triode Q5, the collectors of the triodes Q3 and the base of the triode Q5 are connected with a two-stage low-noise amplifier, and the emitter of the triode Q5 is connected with the holding capacitor.
Further, when the delay ps-level pulse signal is high, the triode Q2 is turned on, the triode Q3 is turned on, the triode Q4 is turned off, the amplified radar signal is grounded from the triode Q3 when the triode Q3 is turned on, the voltage on the holding capacitor is kept unchanged, and the whole circuit is in a holding state; when the delay ps-stage pulse signal is 0, the triode Q2 is cut off, the triode Q3 is cut off, and the triode Q5 is conducted, and the amplified radar signal passes through the triode Q5 to the output end, namely the radar signal is sampled by the sampling circuit.
Further, the storage capacitor is connected with an insulated gate field effect transistor Q6, the triode Q6 is connected with a differential amplifier, and the output end of the amplified signal is connected with an ADC conversion circuit.
Further, the f of transistors Q2 to Q6 t Greater than 10Ghz.
After the echo signals of the ground penetrating radar are received by the antenna, the echo signals of a few millivolts received by the antenna are amplified to hundreds of millivolts by the two-stage amplifier, and are processed by the sampling gate circuit.
The whole digital part mainly comprises an FPGA control stepping delay chip, and according to a MC100E195B chip manual, the delay of square waves can be regulated by controlling the chip D9-D0 management, and the delayed square wave signals are connected with a ps pulse generating circuit to form 10ps stepping delay ps-level pulse signals. The ps pulse generating circuit is connected with the high-speed sampling gate circuit; the pulse signal forms a pair of sampling and holding signals with opposite phases through Q2, and the sampling gate circuit is composed of triodes Q3, Q4 and Q5 and a holding capacitor; q3 is conducted and Q4 is cut off when ps pulse is output, Q5 is in a cut-off state and is in a holding state at the moment, when ps is 0, Q3 is cut off, Q4 is conducted, Q5 is in a conducting state to form an emitter follower, the emitter follower samples signals amplified by the two-stage amplifying circuit to charge a holding capacitor C20, and the circuit is in a sampling state at the moment; the sample and hold circuit interacts to elongate the return signal waveform of the radar signal. The sample-and-hold circuit is connected with the ADC, so that a signal with lower frequency is provided for the ADC to collect, the collected digital signal is processed by the FPGA, and finally the waveform on the radar signal is recovered.
The invention adopts a simple circuit to effectively realize the acquisition of high-speed data, and the whole sampling system has low cost and high feasibility and is very beneficial to the acquisition and the processing of radar signals.
Drawings
Fig. 1 is a block diagram of an equivalent sampling circuit.
Fig. 2 is a circuit diagram of a two-stage low noise amplifier.
Fig. 3 is a schematic diagram of a time delay chip connection.
Fig. 4 is a schematic diagram of a differential amplifier.
Fig. 5 is a schematic diagram of a sampling system.
Fig. 6 is a diagram of the final simulation result of the whole equivalent sampling circuit.
FIG. 7 shows the amplitude and width of the sampling pulses.
The specific embodiment is as follows:
in order to further illustrate the technical means and the effects adopted by the present invention, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and the specific embodiments.
The whole sampling system is divided into: a two-stage low noise amplifier, a high-speed sampling gate circuit, a digital signal control circuit, a ps pulse generating circuit, an ADC conversion circuit and the like.
The two-stage low-noise amplifying circuit is connected with an antenna for receiving radar echo signals and amplifies signals on the antenna. As shown in FIG. 2, MGA62563 is adopted, the normal working range is 20 mA-80 mA, the working frequency is 0.1-3 Ghz, the single-stage gain is 22db to form a two-stage amplifier, signals of tens of millivolts received by an antenna are amplified to hundreds of millivolts, and the signals are sampled by a high-speed sampling gate circuit;
the two-stage amplifying circuit is connected with the high-speed sampling gate circuit, and the amplified signal is sent to the input end of the sampling circuit to be sampled through the coupling capacitor C23, as shown in FIG. 5;
as shown in FIG. 3, the MC100E195B is adopted in the whole delay circuit, and 10ps stepping delay can be realized by using a D9-D0 tube of an FPGA control chip; the square wave signal generated by the crystal oscillator passes through MC100E195B to generate a square wave signal with step delay of 10 ps.
As shown in fig. 5, the step delay square wave signal extracts the edge of the pulse through differential shaping networks (C12, R14) in the ps generating circuit, reduces the duty ratio of the square wave signal, and better excites the avalanche transistor. The differential constant τ is smaller than the width of the positive pulse edge. The avalanche circuit is composed of an avalanche triode, a direct current bias circuit and a shaping network, and can generate Gaussian pulse. After Gaussian pulse generation, a ps-level pulse signal can be obtained by matching with a shaping network (C16 and R19), and the width and the amplitude of the pulse are determined by the RC constant tau of the shaping network.
After ps pulse is generated, the ps pulse signal and the direct current bias signal are overlapped, on one hand, the ps pulse signal is supplied to the holding tube to serve as a holding signal, meanwhile, the ps pulse signal is input to the base electrode of Q2, and a sampling signal with opposite phases appears through the collector electrode of Q2, so that a pair of holding signals and sampling signals with opposite phases can be obtained.
As shown in fig. 5, the sample-hold signal is connected to the sampling circuit, when the pulse signal is high, Q2 is turned on, Q3 is turned on, Q4 is turned off, and when Q3 is turned on, the amplified radar signal goes from Q3 to ground, the voltage on the holding capacitor is kept unchanged, and the whole circuit is in a holding state; when the signal pulse is 0, the Q2 is cut off, the Q3 is cut off, the Q5 is conducted, the amplified radar signal is transmitted to the output end through the Q5, namely the radar signal is sampled by the sampling circuit, the voltage on the holding capacitor C20 depends on the voltage on the emitter-collector follower, the whole circuit is in a sampling state, and the signal about 1Ghz is collected by the whole circuit, so that the f of the transistor used by the whole circuit t Must be greater than 10Ghz;
the holding capacitor is connected with the JFET (Q6), and the high-impedance resistor is connected behind the holding capacitor, so that the voltage on the holding capacitor is more beneficial to holding, and the whole circuit cannot be held because the voltage is discharged to the rear stage during holding and sampling. The voltage across the holding capacitor is passed through the JFET to form a emitter follower, where the amplitude of the holding voltage we can obtain is about 200 mv. In order to fully utilize the ADC rate to connect about 200mv of signal with a dual-input dual-output differential amplifier LMH6550 to amplify the signal, as shown in FIG. 4, the amplification factor of the differential circuit is as follows:
the output end of the amplified signal is connected with the ADS822E, and finally, the processing of the high-frequency signal by using the low-speed ADC can be realized.
And finally, simulating the output of the circuit equivalent sampling circuit by ADS simulation software of Agilent company to obtain an output waveform as shown in figure 6.
In theory, the speed of the whole switching circuit mainly depends on the performance of the whole switching tube, the width of ps pulse and the minimum delay of a delay chip; as long as the switching speed of the triode is fast enough, the generated ps pulse is narrow enough, and the selected delay chip can provide small enough delay, we can collect the signal with infinite frequency;
and finally, the sample hold signal is processed by the ADC, and finally, the high-frequency signal is processed by the low-speed ADC.
It should be understood that parts of the specification not specifically set forth herein are all prior art.
While specific embodiments of the present invention have been described above, it will be appreciated by those skilled in the art that these are merely illustrative, and that many modifications and variations can be made to these embodiments without departing from the principles and spirit of the invention. The scope of the invention is limited only by the appended claims.
Claims (6)
1. An equivalent sampling circuit for acquiring echo signals of an application ground penetrating radar, which is characterized by comprising: a two-stage low noise amplifier, a high-speed sampling gate circuit, an ADC conversion circuit, a digital signal control circuit and a ps pulse generation circuit;
the two-stage low-noise amplifier, the high-speed sampling gate circuit and the ADC conversion circuit are connected in sequence, and the ps pulse generating circuit is respectively connected with the digital signal control circuit and the high-speed sampling gate circuit;
the two-stage low-noise amplifier is connected with an antenna for receiving radar echo signals and is used for amplifying signals on the antenna, and the amplified signals are sent to the input end of the high-speed sampling gate circuit through the coupling capacitor to be sampled;
the digital signal control circuit utilizes a programmable logic gate array to combine with an external crystal oscillator to generate a square wave signal with adjustable delay;
the ps pulse generating circuit is used for converting the delayed square wave signal into a ps-stage pulse signal with delay;
the high-speed sampling gate circuit is used for forming a sampling and holding signal with opposite phase by the delayed ps-stage pulse signal, collecting a high-frequency signal part of the amplified radar signal, elongating the high-frequency signal part and then sending the high-frequency signal part to the ADC conversion circuit;
the high-speed sampling gate circuit comprises a triode Q2 and a sampling gate circuit, wherein the base level of the triode Q2 is connected with the ps pulse generating circuit, the collector is connected with the sampling gate circuit, and the emitter is grounded;
the sampling gate circuit comprises a triode Q3, a triode Q4, a triode Q5 and a holding capacitor, wherein the collector of the triode Q2 is connected with the base level of the triode Q4, the emitter of the triode Q4 is connected with the emitter of the triode Q3, the collector of the triode Q4 is connected with the emitter of the triode Q5, the collectors of the triode Q3 and the base level of the triode Q5 are connected with a two-stage low-noise amplifier, and the emitter of the triode Q5 is connected with the holding capacitor; when the delay ps-stage pulse signal is high, the triode Q2 is conducted, the triode Q3 is conducted, the triode Q4 is cut off, the amplified radar signal is grounded from the triode Q3 when the triode Q3 is conducted, the voltage on the holding capacitor is kept unchanged, and the whole circuit is in a holding state; when the delay ps-stage pulse signal is 0, the triode Q2 is cut off, the triode Q3 is cut off, and the triode Q5 is conducted, and the amplified radar signal passes through the triode Q5 to the output end, namely the radar signal is sampled by the sampling circuit;
the rear end of the holding capacitor is connected with an insulated gate field effect transistor Q6, the triode Q6 is connected with a differential amplifier, and the output end of an amplified signal is connected with an ADC conversion circuit.
2. The equivalent sampling circuit of claim 1, wherein: the digital signal control circuit adopts a programmable logic gate array to control D0-D9 of the MC100E195B chip to control the delay of the square wave signal.
3. The equivalent sampling circuit of claim 2, wherein: the delay is a 10ps step delay.
4. The equivalent sampling circuit of claim 1, wherein: the ps pulse generating circuit comprises an avalanche circuit, the avalanche circuit comprises an avalanche triode, a direct current bias circuit and a differential shaping network, the stepping delay square wave signal is used for extracting the edge of a pulse through the differential shaping network, the duty ratio of the square wave signal is reduced, and the delayed square wave signal is used as an input signal of the avalanche triode and is shaped by combining the avalanche multiplication effect of the avalanche triode with the shaping network to form a delay ps-stage pulse signal.
5. The equivalent sampling circuit of claim 4, wherein: the differential constant τ of the differential shaping network is smaller than the width of the positive pulse edge.
6. The equivalent sampling circuit of claim 1, wherein: f of the triodes Q2 to Q6 t Greater than 10Ghz.
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| CN107272485A (en) * | 2017-06-16 | 2017-10-20 | 中国科学院苏州生物医学工程技术研究所 | A kind of pulse signal acquisition device and method based on low speed ADC |
| CN108459304A (en) * | 2018-06-04 | 2018-08-28 | 南京邮电大学 | A kind of ultra-wideband pulse generation circuit can be used for Ground Penetrating Radar detection |
| CN109633569B (en) * | 2018-12-25 | 2021-04-20 | 北京华航无线电测量研究所 | Large dynamic ground penetrating radar sampling front end gain control method and circuit |
| CN109901472B (en) * | 2019-03-20 | 2021-06-04 | 电子科技大学 | Sequence equivalent sampling system based on FPGA |
| CN110347096A (en) * | 2019-08-08 | 2019-10-18 | 南京邮电大学 | A kind of equivalent sampling circuit based on delays time to control |
| CN112180220B (en) * | 2020-08-31 | 2022-09-20 | 山东信通电子股份有限公司 | Time domain reflection signal data acquisition method and device |
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| CN200966037Y (en) * | 2006-11-10 | 2007-10-24 | 江苏北方湖光光电有限公司 | High frequency sampler |
| CN1987516A (en) * | 2007-02-27 | 2007-06-27 | 呼秀山 | Equivalent sampling pulse distance measuring laser system |
| JP2009074950A (en) * | 2007-09-21 | 2009-04-09 | Fuji Heavy Ind Ltd | Equivalent-time sampling radar and sample hold circuit for equivalent time sampling |
| CN101581781B (en) * | 2009-05-23 | 2011-08-10 | 桂林电子科技大学 | Method and device for receiving pulse ultra-wideband radar signal |
| CN102466748B (en) * | 2010-11-03 | 2016-08-03 | 北京普源精电科技有限公司 | There is the digital oscilloscope of equivalent sampling function and for the equivalent sampling method of digital oscilloscope |
| CN103027670A (en) * | 2012-12-13 | 2013-04-10 | 中国人民解放军第四军医大学 | Micropower impact-type biological radar front end |
| CN103542911B (en) * | 2013-11-01 | 2016-04-13 | 合肥工业大学 | Based on the guided wave radar material level gauge echo signal processing system and method for first order derivative |
| CN103926568B (en) * | 2014-04-30 | 2016-08-24 | 中国科学院电子学研究所 | Balanced feeding sampling receiver |
| CN104734692B (en) * | 2015-01-28 | 2017-09-29 | 西北核技术研究所 | Based on frequency-difference method and DDS the high sampling rate equivalent sampling method realized and system |
| CN206523629U (en) * | 2017-03-03 | 2017-09-26 | 南京邮电大学 | A kind of equivalent sampling circuit of application ground penetrating radar echo signals collection |
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