JP2009074950A - Equivalent-time sampling radar and sample hold circuit for equivalent time sampling - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively prevent high-frequency noise from flowing in from the ground, in a radar using an equivalent-time sampling system. <P>SOLUTION: The equivalent-time sampling radar for performing time scanning has a differential circuit 12 for holding voltage that has the same absolute value level and a different sign as compared with an input voltage in sampling in the interval period of sampling. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an equivalent time sampling radar and a sample hold circuit for equivalent time sampling.

  Sampling generally performed in signal processing is processing for sampling an analog signal at an arbitrary time with respect to an analog input signal and holding the voltage of the analog signal. This processing is used, for example, for analog / digital conversion (A / D conversion) for converting an analog signal into a digital signal, or equivalent time sampling as disclosed in Patent Document 1. Here, the equivalent time sampling refers to a process of converting a short cycle repetitive signal into a long cycle repetitive signal having a longer cycle. One point is sampled for each cycle of the short cycle repetition signal, and this sampling timing is shifted from the repetition point. Such a shift process is called time scanning. As a result, the short-cycle repetitive signal is expanded on the time axis and converted into a long-cycle signal having the same waveform, so that the resolution (distance resolution in the radar) can be improved.

  Patent Document 2 discloses a reception system, specifically, an equivalent time sampling radar that realizes equivalent time sampling by time scanning of a received signal. In this method, transmission pulses are periodically transmitted at regular intervals, and the individual transmission pulses reflected by the target are received as reception signals. Then, the received signal is sampled at a timing slightly offset every cycle. As a result, a waveform having the same shape as the original is expanded and reproduced on the time axis.

  Patent Document 3 discloses a specific configuration of a sample-and-hold circuit in a UWB (Ultra-Wideband) reception system. In this circuit, a hold capacitor for holding a sampled signal is provided between a signal line connected to the output terminal of the sample hold circuit and ground (ground potential).

  Patent Document 4 discloses a specific configuration in which time scanning in equivalent time sampling is performed not on the reception side but on the transmission side. In this method, the transmission pulse is transmitted at a timing slightly offset every cycle. After that, the individual transmission pulses reflected by the target are received as reception signals, and the reception signals are periodically sampled at regular intervals. As a result, a waveform having the same shape as the original is expanded and reproduced on the time axis.

JP-A-1-235863 JP-T-2002-516453 US Pat. No. 5,523,760 (FIG. 9A) JP-T-2001-526767

  In general, the circuit configuration of the receiving system in the radar preferably prevents the generation of high-frequency noise. This is because the received signal is weak compared to the transmitted wave, and is therefore susceptible to high frequency noise. From this point of view, the equivalent time sampling radar that performs time scanning on the receiving side disclosed in Patent Document 2 needs to generate a sawtooth wave that easily generates high-frequency noise in the receiving circuit. This is the first problem. In addition, immediately before switching time scanning, the sampling interval becomes extremely short, and there is a problem that high-frequency distortion occurs in the sampling waveform after time expansion. This is the second problem. In order to solve the above two problems, Patent Document 4 discloses a configuration in which time scanning in equivalent time sampling is performed not on the reception side but on the transmission side.

  In general, in a sample and hold circuit in equivalent time sampling, the voltage must be kept constant over the entire time of (repetition period + time scanning amount), so that the hold capacitor needs to have a large capacity. However, the hold capacitor for holding the sampled signal is provided between the signal line connected to the output terminal of the sample hold circuit and the ground in the circuit disclosed in Patent Document 4 as well as in Patent Document 3. Yes. In a high-frequency circuit, a circuit configuration in which a large-capacitance capacitor is provided between the signal line and the ground is equivalent to directly attaching the signal line to the ground because the impedance of the capacitor is small in proportion to the frequency. Therefore, in the circuit configuration according to the prior art in which a large-capacitance capacitor is provided between the signal line and the ground, high-frequency noise from the ground flows into the signal processing system connected to the signal line through the large-capacitance capacitor. There is a problem. This problem has become apparent when the configuration of Patent Document 4 in which a sawtooth wave that easily generates high-frequency noise is generated on the transmission side is adopted. This is because the above-described problem also occurred in Patent Document 2 and Patent Document 3, but in these cases, high-frequency noise due to the sawtooth wave is dominant and has not been manifested.

  An object of the present invention is to realize an equivalent time sampling circuit capable of effectively blocking the inflow of high frequency noise from the ground in a sample and hold circuit that performs equivalent time sampling.

  In order to solve this problem, the first invention provides an equivalent time sampling radar that performs time scanning. This equivalent time sampling radar has a differentiating circuit that holds a voltage having the same magnitude and different sign from the input voltage at the time of sampling during the sampling interval.

  Here, in the first invention, the differentiation circuit is a node that connects the antenna circuit that receives the received signal, the pulse amplitude modulation circuit that prevents the signal from flowing into the circuit during the sampling interval, and the circuit unit in the subsequent stage. It is preferable that it is connected between. At this time, the differentiation circuit is connected to the input signal line to which the received signal is input, the hold capacitor for holding the input voltage of the received signal, the output signal line to which the held voltage is output, the output signal line and the ground. It is preferable to have a first resistor.

  The pulse amplitude modulation circuit preferably has an output signal line, a clock line, a switching circuit, and a second resistor. The clock line is supplied with sampling pulses that define the sampling time. The switching circuit is connected between the output signal line and the clock line, and is turned on during the sampling period of the sampling pulse and turned off during the holding period of the sampling pulse. By this switching processing, the input signal is allowed to flow into the receiving circuit during the sampling period, and the input signal is prevented from flowing into the receiving circuit during the sampling interval period. The second resistor connects the clock line and ground. The switching circuit is preferably a diode connected in parallel with the circuit unit at the subsequent stage relative to the differentiation circuit.

  The second invention provides a sample and hold circuit for equivalent time sampling. This equivalent time sampling sample hold circuit has an input end, an output end, a pulse supply end, a capacitor, a switching circuit, a first resistor, and a second resistor. The input terminal receives an input signal to be subjected to sampling processing. The output terminal outputs an output signal after sampling processing. A sampling pulse that defines a sampling time is supplied to the pulse supply end. The capacitor has one electrode connected to the input end and the other electrode directly connected to the output end. This capacitor blocks the DC component between the input end and the output end, and holds the sampled signal. The switching circuit is connected between the output terminal and the pulse supply terminal, and is turned on during the sampling period of the sampling pulse, flows in the input signal to the receiving circuit, is turned off during the holding period of the sampling pulse, and is input to the receiving circuit. To prevent the inflow. The first resistor has one end connected to the input end and the other end grounded. The first resistor functions as a matching resistor that adjusts the impedance of the input end. The second resistor has one end connected to the output end and the other end grounded. The second resistor functions as a time constant resistor associated with the capacitor and also functions as a bias resistor.

  According to the present invention, the capacitor connected between the input end and the output end functions as a hold capacitor that holds the sampled signal. Thereby, it is possible to effectively prevent high-frequency noise from the ground from flowing into the signal processing system connected to the signal line.

  Further, according to the present invention, the hold capacitor constituting the differentiating circuit can prevent a direct current component between the input end and the output end.

  FIG. 1 is a configuration diagram of an equivalent time sampling radar according to the present embodiment. This sampling radar is composed of a transmission system composed of circuit units 1 to 4, a transmission antenna 5, a reception antenna (antenna circuit) 6, a reception system composed of circuit units 7 to 8, and a distance measurement unit 9. Yes. In this radar, equivalent time sampling is executed not by time scanning at the reception system but by time scanning at the transmission system.

  The transmission system performs time scanning and shifts the generation timing of the transmission signal for each period. The transmission system includes a reference clock generation circuit 1, a time scanning circuit 2, a transmission pulse generation circuit 3, and a band pass filter 4. The reference clock generation circuit 1 generates a rectangular reference clock having a fixed period. The time scanning circuit 2 performs time scanning on the input reference clock and outputs a transmission clock that is a pulse width modulation wave of the reference clock. The transmission pulse generation circuit 3 generates a transmission pulse according to the generation timing of the transmission clock. The transmission pulse is radiated to the outside as a transmission wave from the transmission antenna 5 after passing through a filtering process in the band pass filter 4.

  On the other hand, the receiving system includes a band pass filter 7 and a receiving circuit 8. A transmission wave reflected by the target T is received by the reception antenna 6 as a reception signal. This received signal is input to the receiving circuit 8 after passing through a filtering process in the band pass filter 7. The reception circuit 8 is mainly composed of a sample-and-hold circuit 10 and an analog-digital converter 8c (hereinafter referred to as A / D converter 8c), and an amplifier 8a for amplifying an input reception signal is provided in the preceding stage, An input limiter 8b for protecting the A / D converter 8c and the like is provided. The sample hold circuit 10 temporarily holds the voltage of the reception signal during the sampling period by the sampling pulse based on the reference clock from the reference clock generation circuit 1, and the sampling interval at which the input signal is prevented from flowing into the reception circuit. Output to a subsequent circuit unit (amplifier 8a, etc.) during the period. The A / D converter 8c samples the input received signal at a constant interval over a plurality of periods, thereby generating an expanded received signal having a longer period. This expanded received signal is obtained by expanding and reproducing a waveform having the same shape as the original on the time axis.

  The distance measuring unit 9 measures the distance to the target T based on the expanded reception signal output from the A / D converter 8c. As is well known, the distance to the target T is uniquely calculated based on the round-trip propagation time until the transmission wave radiated from the transmission antenna 5 is reflected by the target T and received by the reception antenna 6. The

  FIG. 2 is a configuration diagram of the sample and hold circuit 10. The sample and hold circuit 10 includes three ends of an input end, an output end, and a pulse supply end, a resistor 11, a differentiation circuit 12, a pulse amplitude modulation circuit 13, and a capacitor 14.

The differentiation circuit 12 is connected between the input end and the output end. Specifically, it is connected between the reception antenna 6 that receives the reception signal and a node that connects the pulse amplitude modulation circuit 13 and the circuit unit (for example, the amplifier 8a) of the subsequent stage. The differentiating circuit 12 holds a voltage having the same magnitude and different sign as the received signal voltage during the sampling period, and outputs it to the subsequent circuit unit during the sampling interval period during which the input signal is prevented from flowing into the receiving circuit. To do. The differentiation circuit 12 includes a hold capacitor 12a and a resistor 12b. The hold capacitor 12a holds the voltage of the received signal during the sampling period. It functions as a blocking capacitor that blocks a DC component between the input terminal and the output terminal, and also functions as a hold capacitor that holds a sampled signal. Note that the capacity of the cold capacitor 12a of this embodiment is sufficiently large. The resistor 12b connects the output signal line and the ground. The resistor 12b functions as a time constant resistor linked to the hold capacitor 12a and also functions as a bias resistor.

  The pulse amplitude modulation circuit 13 is connected between the differentiation circuit 12 and the output signal line (more precisely, it is connected in parallel with the circuit unit at the subsequent stage with respect to the differentiation circuit 12), and the input signal is input during the sampling period. And the input signal is prevented from flowing into the receiving circuit during the sampling interval. The pulse amplitude modulation circuit 13 includes a switching circuit 13a and a resistor 13b. The switching circuit 13a is connected between the output terminal and the pulse supply terminal, and is turned on during the sampling period of the sampling pulse, flows an input signal into the receiving circuit, is turned off during the holding period of the sampling pulse, and is input to the receiving circuit. Block signal inflow. The switching circuit 13a is connected between the clock line and the output signal line (more precisely, it is connected in parallel with the subsequent circuit unit), and is connected in parallel with the subsequent circuit unit with respect to the differentiation circuit 12. Yes. As the switching circuit 13a, for example, a diode can be used. In this case, the anode of the diode is connected to the output terminal and the cathode thereof is connected to the pulse supply terminal. The resistor 13b has one end connected to the cathode (point A) of the diode and the other end grounded. The capacitor 14 is connected between the clock line and the pulse amplitude modulation circuit 13 (the cathode of the diode). As a result, at point A, a one-shot pulse is generated only when the sampling pulse from the clock line falls.

  3A and 3B are explanatory diagrams of input / output signals of the sample and hold circuit 10. FIG. 3A shows a waveform of a received signal (input voltage) at the input terminal, and FIG. 3B shows a capacitor 14 and a switching circuit 13a. The waveform of the sampling pulse during the interval (point A), and FIG. 5C shows the waveform of the output signal at the output end. In the hold period in which the sampling pulse is at a high level, the potential at the output end maintains the potential at the end of the immediately preceding sample period, regardless of the potential of the reception signal supplied to the input end. On the other hand, during the sampling period in which the sampling pulse is at a low level, the capacitor 10a is written by the received signal, and the potential at the output terminal also varies accordingly.

  The conventional sampling circuit is not limited to an equivalent time sampling radar, and an integration circuit is used. The integration circuit outputs a voltage proportional to the integration value with respect to time of the input voltage (reception signal). When the integrating circuit includes a resistor and a capacitor (hold capacitor) C, the resistor is connected between the input end and the output end, and the capacitor C is connected to the output end at one end and the ground is connected to the other end. . By making the discharge time constant of the capacitor C sufficiently larger than the sampling period, the input voltage in the sampling period of the period immediately before the current sampling can be held in the capacitor C. However, the impedance Z of the capacitor is Z = 1 / jwC. Therefore, when the input voltage becomes high frequency (w is large), the impedance Z approaches 0, which is the same as short-circuiting.

  In the present embodiment, the differentiation circuit 12 is used by replacing the resistors and capacitors in the integration circuit. The differentiation circuit 12 outputs a voltage proportional to the differential value with respect to time of the input voltage. If the differentiating circuit 12 makes the discharge time constant of the hold capacitor sufficiently larger than the sampling period, a voltage having the same magnitude but different sign from the input voltage at the time of sampling as shown in FIG. Can be held.

  In the differentiating circuit 12, a resistor 12b is connected between the output terminal and the ground. The impedance of the resistor 12b is independent of the frequency. Therefore, in the differentiating circuit 12, even if the frequency of the sampling pulse increases, the inflow of high frequency noise from the ground to the signal processing system (input end and output end) can be effectively suppressed by the resistor 12b. Moreover, according to this embodiment, since the hold capacitor which comprises a differentiation circuit is connected between the input terminal and the output terminal, the direct current | flow component in the meantime can be blocked | prevented. The sampling pulse described above may be directly supplied from the reference clock generation circuit 1 or may be supplied separately based on a signal from the time scanning circuit 2.

Configuration diagram of equivalent time sampling radar according to this embodiment Configuration diagram of sample hold circuit Illustration of input / output signals of sample hold circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Reference clock generation circuit 2 Time scanning circuit 3 Transmission pulse generation circuit 4,7 Band pass filter 5 Transmission antenna 6 Reception antenna 8 Reception circuit 8a Amplifier 8b Input limiter 8c Analog-digital converter 9 Distance measurement part 10 Sample hold circuit 11, 12b, 13b Resistance 12 Differentiation circuit 12a Capacitor 13 Pulse amplitude modulation circuit 13a Switching circuit 14 Capacitor

Claims (6)

In an equivalent time sampling radar that performs time scanning,
An equivalent-time sampling radar having a differentiating circuit for holding a voltage having an absolute value that is the same as an input voltage at the time of sampling but having a different sign during the sampling interval. The differentiation circuit is:
It is connected between an antenna circuit that receives a received signal and a node that connects a pulse amplitude modulation circuit that prevents the signal from flowing into the circuit during a sampling interval and a circuit unit in the subsequent stage. The equivalent time sampling radar according to claim 1. The differentiation circuit is:
An input signal line to which the received signal is input;
A hold capacitor for holding the input voltage of the received signal;
An output signal line for outputting the held voltage;
3. The equivalent time sampling radar according to claim 1, further comprising a first resistor connected to the output signal line and ground. The pulse amplitude modulation circuit includes:
The differential circuit is connected in parallel with the subsequent circuit unit,
The output signal line;
A clock line to which a sampling pulse defining the sampling time is supplied;
A switching circuit that is connected between the output signal line and the clock line, and is turned on in the sampling period of the sampling pulse and turned off in the holding period of the sampling pulse;
The equivalent time sampling radar according to claim 3, further comprising a second resistor that connects the clock line and ground. The switching circuit is
5. The equivalent time sampling radar according to claim 4, wherein the equivalent time sampling radar is a diode connected in parallel with a circuit unit at a subsequent stage with respect to the differentiation circuit. In the sample and hold circuit for equivalent time sampling,
An input terminal to which an input signal to be sampled is input;
An output terminal for outputting an output signal after sampling processing;
A pulse supply end to which a sampling pulse defining a sampling time is supplied;
One electrode is connected to the input terminal, the other electrode is directly connected to the output terminal, a capacitor for blocking a direct current component between the input terminal and the output terminal and holding the sampled signal; ,
A switching circuit that is connected between the output end and the pulse supply end, and is turned on during the sampling period of the sampling pulse and turned off during the hold period of the sampling pulse;
A first resistor having one end connected to the input end and the other end grounded and functioning as a matching resistor for adjusting the impedance of the input end;
One end is connected to the output end and the other end is grounded, and has a second resistor that functions as a time constant resistor linked to the capacitor and also functions as a bias resistor for biasing the output end. A sample and hold circuit for equivalent time sampling.

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